SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are seven I2C modules integrated in the device MAIN domain - I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, and I2C6. Figure 12-126 shows the integration of I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, and I2C6.
Table 12-240 through Table 12-242 summarize the integration of I2C[0-6] in the device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
I2C0 | PSC0 | PD0 | LPSC7 | CBASS0 |
I2C1 | PSC0 | PD0 | LPSC7 | CBASS0 |
I2C2 | PSC0 | PD0 | LPSC7 | CBASS0 |
I2C3 | PSC0 | PD0 | LPSC7 | CBASS0 |
I2C4 | PSC0 | PD0 | LPSC7 | CBASS0 |
I2C5 | PSC0 | PD0 | LPSC7 | CBASS0 |
I2C6 | PSC0 | PD0 | LPSC7 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
I2C0 | I2C0_OCP_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | I2C0 interface clock |
I2C0_SYS_CLK | MAIN_PLL1_HSDIV0_CLKOUT/2 | PLL1 | I2C0 functional clock | |
I2C1 | I2C1_OCP_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | I2C1 interface clock |
I2C1_SYS_CLK | MAIN_PLL1_HSDIV0_CLKOUT/2 | PLL1 | I2C1 functional clock | |
I2C2 | I2C2_OCP_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | I2C2 interface clock |
I2C2_SYS_CLK | MAIN_PLL1_HSDIV0_CLKOUT/2 | PLL1 | I2C2 functional clock | |
I2C3 | I2C3_OCP_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | I2C3 interface clock |
I2C3_SYS_CLK | MAIN_PLL1_HSDIV0_CLKOUT/2 | PLL1 | I2C3 functional clock | |
I2C4 | I2C4_OCP_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | I2C4 interface clock |
I2C4_SYS_CLK | MAIN_PLL1_HSDIV0_CLKOUT/2 | PLL1 | I2C4 functional clock | |
I2C5 | I2C5_OCP_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | I2C5 interface clock |
I2C5_SYS_CLK | MAIN_PLL1_HSDIV0_CLKOUT/2 | PLL1 | I2C5 functional clock | |
I2C6 | I2C6_OCP_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | I2C6 interface clock |
I2C6_SYS_CLK | MAIN_PLL1_HSDIV0_CLKOUT/2 | PLL1 | I2C6 functional clock | |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
I2C0 | I2C0_RST | MOD_G_RST | LPSC7 | I2C0 reset |
I2C1 | I2C1_RST | MOD_G_RST | LPSC7 | I2C1 reset |
I2C2 | I2C2_RST | MOD_G_RST | LPSC7 | I2C2 reset |
I2C3 | I2C3_RST | MOD_G_RST | LPSC7 | I2C3 reset |
I2C4 | I2C4_RST | MOD_G_RST | LPSC7 | I2C4 reset |
I2C5 | I2C5_RST | MOD_G_RST | LPSC7 | I2C5 reset |
I2C6 | I2C6_RST | MOD_G_RST | LPSC7 | I2C6 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
I2C0 | I2C0_POINTRPEND_0 | GIC500_SPI_IN_232 | COMPUTE_CLUSTER0 | I2C0 Interrupt request | Level |
R5FSS0_CORE0_INTR_IN_150 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_150 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_56 | MAIN2MCU_LVL_INTRTR0 | ||||
I2C1 | I2C1_POINTRPEND_0 | GIC500_SPI_IN_233 | COMPUTE_CLUSTER0 | I2C1 Interrupt request | Level |
R5FSS0_CORE0_INTR_IN_151 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_151 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_57 | MAIN2MCU_LVL_INTRTR0 | ||||
I2C2 | I2C2_POINTRPEND_0 | GIC500_SPI_IN_234 | COMPUTE_CLUSTER0 | I2C2 Interrupt request | Level |
R5FSS0_CORE0_INTR_IN_256 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_256 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_58 | MAIN2MCU_LVL_INTRTR0 | ||||
I2C3 | I2C3_POINTRPEND_0 | GIC500_SPI_IN_235 | COMPUTE_CLUSTER0 | I2C3 Interrupt request | Level |
R5FSS0_CORE0_INTR_IN_257 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_257 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_59 | MAIN2MCU_LVL_INTRTR0 | ||||
I2C4 | I2C4_POINTRPEND_0 | GIC500_SPI_IN_236 | COMPUTE_CLUSTER0 | I2C4 Interrupt request | Level |
R5FSS0_CORE0_INTR_IN_258 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_258 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_60 | MAIN2MCU_LVL_INTRTR0 | ||||
I2C5 | I2C5_POINTRPEND_0 | GIC500_SPI_IN_237 | COMPUTE_CLUSTER0 | I2C5 Interrupt request | Level |
R5FSS0_CORE0_INTR_IN_259 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_259 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_61 | MAIN2MCU_LVL_INTRTR0 | ||||
I2C6 | I2C6_POINTRPEND_0 | GIC500_SPI_IN_238 | COMPUTE_CLUSTER0 | I2C6 Interrupt request | Level |
R5FSS0_CORE0_INTR_IN_260 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_260 | R5FSS0_CORE1 | ||||
MAIN2MCU_LVL_INTRTR0_IN_62 | MAIN2MCU_LVL_INTRTR0 |