SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
When CPSW is configured as a store and forward switch, the switch latency is defined as the amount of time between the end of packet reception of the received packet to the start of the output packet transmit.
The store and forward latency is shown in Table 12-945:
Mode | Latency |
---|---|
Gig (1000) | 880 ns |
100 | 1.3 µs |
10 | 6.5 µs |