SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5419 lists the memory-mapped registers for the GTC0_GTC_CFG2. All register offset addresses not listed in Table 12-5419 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
GTC0_GTC_CFG2 | 00AA 0000h |
Offset | Acronym | Register Name | GTC0_GTC_CFG2 Physical Address |
---|---|---|---|
0h | GTC_CNTCVS_LO | Counter count value (low) status register | 00AA 0000h |
4h | GTC_CNTCVS_HI | Counter count value (high) status register | 00AA 0004h |
GTC_CNTCVS_LO is shown in Figure 12-2835 and described in Table 12-5421.
Return to Summary Table.
Indicates the current system counter count value. It reflects the same value as the CNTCV_LO register.
Instance | Physical Address |
---|---|
GTC_R10_CFG1 | 00AA 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTVALUE | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNTVALUE | R | 0h | Indicates bits [31:0] of the system counter value. |
GTC_CNTCVS_HI is shown in Figure 12-2836 and described in Table 12-5423.
Return to Summary Table.
Indicates the current system counter count value. It reflects the same value as the CNTCV_HI register.
Instance | Physical Address |
---|---|
GTC_R10_CFG1 | 00AA 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTVALUE | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNTVALUE | R | 0h | Indicates bits [63:32] of the system counter value. |