SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 6-125 lists the memory-mapped registers for the A72SS. All register offset addresses not listed in Table 6-125 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8000h |
Offset | Acronym | Register Name | COMPUTE_CLUSTER0_ A72SS0_CORE1_ ECC_AGGR Physical Address |
---|---|---|---|
0h | A72SS_CORE1_ECC_REV | Aggregator revision register | 4D 2001 8000h |
8h | A72SS_CORE1_ECC_VECTOR | ECC vector register | 4D 2001 8008h |
Ch | A72SS_CORE1_ECC_STAT | Misc status register | 4D 2001 800Ch |
3Ch | A72SS_CORE1_ECC_SEC_EOI_REG | SEC EOI register | 4D 2001 803Ch |
40h | A72SS_CORE1_ECC_SEC_STATUS_REG0 | SEC interrupt status register 0 | 4D 2001 8040h |
80h | A72SS_CORE1_ECC_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 4D 2001 8080h |
C0h | A72SS_CORE1_ECC_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 4D 2001 80C0h |
13Ch | A72SS_CORE1_ECC_DED_EOI_REG | DED EOI register | 4D 2001 813Ch |
140h | A72SS_CORE1_ECC_DED_STATUS_REG0 | DED interrupt status register 0 | 4D 2001 8140h |
180h | A72SS_CORE1_ECC_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 4D 2001 8180h |
1C0h | A72SS_CORE1_ECC_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 4D 2001 81C0h |
200h | A72SS_CORE1_ECC_AGGR_ENABLE_SET | AGGR interrupt enable set register | 4D 2001 8200h |
204h | A72SS_CORE1_ECC_AGGR_ENABLE_CLR | AGGR interrupt enable clear register | 4D 2001 8204h |
208h | A72SS_CORE1_ECC_AGGR_STATUS_SET | AGGR interrupt status set register | 4D 2001 8208h |
20Ch | A72SS_CORE1_ECC_AGGR_STATUS_CLR | AGGR interrupt status clear register | 4D 2001 820Ch |
A72SS_CORE1_ECC_REV is shown in Figure 6-54 and described in Table 6-127.
Return to Summary Table.
IP revision register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A0EA00h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A0EA00h | TI internal data. Identifies revision of peripheral. |
A72SS_CORE1_ECC_VECTOR is shown in Figure 6-55 and described in Table 6-129.
Return to Summary Table.
ECC vector register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
A72SS_CORE1_ECC_STAT is shown in Figure 6-56 and described in Table 6-131.
Return to Summary Table.
Misc status register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 800Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-2Ah | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 19h | Indicates the number of RAMs serviced by the ECC aggregator |
A72SS_CORE1_ECC_SEC_EOI_REG is shown in Figure 6-57 and described in Table 6-133.
Return to Summary Table.
SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 803Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
A72SS_CORE1_ECC_SEC_STATUS_REG0 is shown in Figure 6-58 and described in Table 6-135.
Return to Summary Table.
SEC interrupt status register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EDC_CTRL_ECCAGGR_CPU1_PEND | ||||||
R/W-X | R/W1S-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | EDC_CTRL_ECCAGGR_CPU1_PEND | R/W1S | 0h | Interrupt pending status for edc_ctrl_eccaggr_cpu1_pend |
23 | CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend |
22 | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend |
21 | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend |
20 | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend |
19 | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_tag_spram_bank3_ecc_svbus_pend |
18 | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_tag_spram_bank2_ecc_svbus_pend |
17 | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_tag_spram_bank1_ecc_svbus_pend |
16 | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_tag_spram_bank0_ecc_svbus_pend |
15 | CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank7_ecc_svbus_pend |
14 | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank6_ecc_svbus_pend |
13 | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank5_ecc_svbus_pend |
12 | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank4_ecc_svbus_pend |
11 | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank3_ecc_svbus_pend |
10 | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank2_ecc_svbus_pend |
9 | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank1_ecc_svbus_pend |
8 | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank0_ecc_svbus_pend |
7 | CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_tag_spram_bank1_ecc_svbus_pend |
6 | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_tag_spram_bank0_ecc_svbus_pend |
5 | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank5_ecc_svbus_pend |
4 | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank4_ecc_svbus_pend |
3 | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank3_ecc_svbus_pend |
2 | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank2_ecc_svbus_pend |
1 | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank1_ecc_svbus_pend |
0 | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank0_ecc_svbus_pend |
A72SS_CORE1_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 6-59 and described in Table 6-137.
Return to Summary Table.
SEC interrupt enable set register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EDC_CTRL_ECCAGGR_CPU1_ENABLE_SET | ||||||
R/W-X | R/W1S-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | EDC_CTRL_ECCAGGR_CPU1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for edc_ctrl_eccaggr_cpu1_pend |
23 | CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend |
22 | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend |
21 | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend |
20 | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend |
19 | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_tag_spram_bank3_ecc_svbus_pend |
18 | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_tag_spram_bank2_ecc_svbus_pend |
17 | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_tag_spram_bank1_ecc_svbus_pend |
16 | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_tag_spram_bank0_ecc_svbus_pend |
15 | CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank7_ecc_svbus_pend |
14 | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank6_ecc_svbus_pend |
13 | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank5_ecc_svbus_pend |
12 | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank4_ecc_svbus_pend |
11 | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank3_ecc_svbus_pend |
10 | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank2_ecc_svbus_pend |
9 | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank1_ecc_svbus_pend |
8 | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank0_ecc_svbus_pend |
7 | CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_tag_spram_bank1_ecc_svbus_pend |
6 | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_tag_spram_bank0_ecc_svbus_pend |
5 | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank5_ecc_svbus_pend |
4 | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank4_ecc_svbus_pend |
3 | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank3_ecc_svbus_pend |
2 | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank2_ecc_svbus_pend |
1 | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank1_ecc_svbus_pend |
0 | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank0_ecc_svbus_pend |
A72SS_CORE1_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 6-60 and described in Table 6-139.
Return to Summary Table.
SEC interrupt enable clear register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 80C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EDC_CTRL_ECCAGGR_CPU1_ENABLE_CLR | ||||||
R/W-X | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | EDC_CTRL_ECCAGGR_CPU1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for edc_ctrl_eccaggr_cpu1_pend |
23 | CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend |
22 | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend |
21 | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend |
20 | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend |
19 | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_tag_spram_bank3_ecc_svbus_pend |
18 | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_tag_spram_bank2_ecc_svbus_pend |
17 | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_tag_spram_bank1_ecc_svbus_pend |
16 | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_tag_spram_bank0_ecc_svbus_pend |
15 | CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank7_ecc_svbus_pend |
14 | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank6_ecc_svbus_pend |
13 | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank5_ecc_svbus_pend |
12 | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank4_ecc_svbus_pend |
11 | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank3_ecc_svbus_pend |
10 | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank2_ecc_svbus_pend |
9 | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank1_ecc_svbus_pend |
8 | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank0_ecc_svbus_pend |
7 | CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_tag_spram_bank1_ecc_svbus_pend |
6 | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_tag_spram_bank0_ecc_svbus_pend |
5 | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank5_ecc_svbus_pend |
4 | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank4_ecc_svbus_pend |
3 | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank3_ecc_svbus_pend |
2 | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank2_ecc_svbus_pend |
1 | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank1_ecc_svbus_pend |
0 | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank0_ecc_svbus_pend |
A72SS_CORE1_ECC_DED_EOI_REG is shown in Figure 6-61 and described in Table 6-141.
Return to Summary Table.
DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 813Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
A72SS_CORE1_ECC_DED_STATUS_REG0 is shown in Figure 6-62 and described in Table 6-143.
Return to Summary Table.
DED interrupt status register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EDC_CTRL_ECCAGGR_CPU1_PEND | ||||||
R/W-X | R/W1S-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | EDC_CTRL_ECCAGGR_CPU1_PEND | R/W1S | 0h | Interrupt pending status for edc_ctrl_eccaggr_cpu1_pend |
23 | CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend |
22 | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend |
21 | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend |
20 | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend |
19 | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_tag_spram_bank3_ecc_svbus_pend |
18 | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_tag_spram_bank2_ecc_svbus_pend |
17 | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_tag_spram_bank1_ecc_svbus_pend |
16 | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_tag_spram_bank0_ecc_svbus_pend |
15 | CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank7_ecc_svbus_pend |
14 | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank6_ecc_svbus_pend |
13 | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank5_ecc_svbus_pend |
12 | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank4_ecc_svbus_pend |
11 | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank3_ecc_svbus_pend |
10 | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank2_ecc_svbus_pend |
9 | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank1_ecc_svbus_pend |
8 | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ls_data_spram_bank0_ecc_svbus_pend |
7 | CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_tag_spram_bank1_ecc_svbus_pend |
6 | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_tag_spram_bank0_ecc_svbus_pend |
5 | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank5_ecc_svbus_pend |
4 | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank4_ecc_svbus_pend |
3 | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank3_ecc_svbus_pend |
2 | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank2_ecc_svbus_pend |
1 | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank1_ecc_svbus_pend |
0 | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for cpu1_if_data_spram_bank0_ecc_svbus_pend |
A72SS_CORE1_ECC_DED_ENABLE_SET_REG0 is shown in Figure 6-63 and described in Table 6-145.
Return to Summary Table.
DED interrupt enable set register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EDC_CTRL_ECCAGGR_CPU1_ENABLE_SET | ||||||
R/W-X | R/W1S-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | EDC_CTRL_ECCAGGR_CPU1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for edc_ctrl_eccaggr_cpu1_pend |
23 | CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend |
22 | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend |
21 | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend |
20 | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend |
19 | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_tag_spram_bank3_ecc_svbus_pend |
18 | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_tag_spram_bank2_ecc_svbus_pend |
17 | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_tag_spram_bank1_ecc_svbus_pend |
16 | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_tag_spram_bank0_ecc_svbus_pend |
15 | CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank7_ecc_svbus_pend |
14 | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank6_ecc_svbus_pend |
13 | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank5_ecc_svbus_pend |
12 | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank4_ecc_svbus_pend |
11 | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank3_ecc_svbus_pend |
10 | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank2_ecc_svbus_pend |
9 | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank1_ecc_svbus_pend |
8 | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ls_data_spram_bank0_ecc_svbus_pend |
7 | CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_tag_spram_bank1_ecc_svbus_pend |
6 | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_tag_spram_bank0_ecc_svbus_pend |
5 | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank5_ecc_svbus_pend |
4 | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank4_ecc_svbus_pend |
3 | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank3_ecc_svbus_pend |
2 | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank2_ecc_svbus_pend |
1 | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank1_ecc_svbus_pend |
0 | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_if_data_spram_bank0_ecc_svbus_pend |
A72SS_CORE1_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 6-64 and described in Table 6-147.
Return to Summary Table.
DED interrupt enable clear register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 81C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EDC_CTRL_ECCAGGR_CPU1_ENABLE_CLR | ||||||
R/W-X | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | EDC_CTRL_ECCAGGR_CPU1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for edc_ctrl_eccaggr_cpu1_pend |
23 | CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend |
22 | CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend |
21 | CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend |
20 | CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend |
19 | CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_tag_spram_bank3_ecc_svbus_pend |
18 | CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_tag_spram_bank2_ecc_svbus_pend |
17 | CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_tag_spram_bank1_ecc_svbus_pend |
16 | CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_tag_spram_bank0_ecc_svbus_pend |
15 | CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank7_ecc_svbus_pend |
14 | CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank6_ecc_svbus_pend |
13 | CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank5_ecc_svbus_pend |
12 | CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank4_ecc_svbus_pend |
11 | CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank3_ecc_svbus_pend |
10 | CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank2_ecc_svbus_pend |
9 | CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank1_ecc_svbus_pend |
8 | CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ls_data_spram_bank0_ecc_svbus_pend |
7 | CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_tag_spram_bank1_ecc_svbus_pend |
6 | CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_tag_spram_bank0_ecc_svbus_pend |
5 | CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank5_ecc_svbus_pend |
4 | CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank4_ecc_svbus_pend |
3 | CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank3_ecc_svbus_pend |
2 | CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank2_ecc_svbus_pend |
1 | CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank1_ecc_svbus_pend |
0 | CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_if_data_spram_bank0_ecc_svbus_pend |
A72SS_CORE1_ECC_AGGR_ENABLE_SET is shown in Figure 6-65 and described in Table 6-149.
Return to Summary Table.
AGGR interrupt enable set register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
A72SS_CORE1_ECC_AGGR_ENABLE_CLR is shown in Figure 6-66 and described in Table 6-151.
Return to Summary Table.
AGGR interrupt enable clear register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
A72SS_CORE1_ECC_AGGR_STATUS_SET is shown in Figure 6-67 and described in Table 6-153.
Return to Summary Table.
AGGR interrupt status set register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 8208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors |
A72SS_CORE1_ECC_AGGR_STATUS_CLR is shown in Figure 6-68 and described in Table 6-155.
Return to Summary Table.
AGGR interrupt status clear register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR | 4D 2001 820Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors |