SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3724 lists the memory-mapped registers for the PCIE_ECC_AGGR0. All register offset addresses not listed in Table 12-3724 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2000h |
Offset | Acronym | Register Name | PCIE1_CORE_ECC_AGGR0 Physical Address |
---|---|---|---|
0h | PCIE_ECC0_REV | Aggregator Revision Register | 02A0 2000h |
8h | PCIE_ECC0_VECTOR | ECC Vector Register | 02A0 2008h |
Ch | PCIE_ECC0_STAT | Misc Status | 02A0 200Ch |
10h + formula | PCIE_ECC0_RESERVED_SVBUS_y | Reserved Area for Serial VBUS Registers | 02A0 2010h + formula |
3Ch | PCIE_ECC0_SEC_EOI_REG | EOI Register | 02A0 203Ch |
40h | PCIE_ECC0_SEC_STATUS_REG0 | Interrupt Status Register 0 | 02A0 2040h |
80h | PCIE_ECC0_SEC_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 02A0 2080h |
C0h | PCIE_ECC0_SEC_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 02A0 20C0h |
13Ch | PCIE_ECC0_DED_EOI_REG | EOI Register | 02A0 213Ch |
140h | PCIE_ECC0_DED_STATUS_REG0 | Interrupt Status Register 0 | 02A0 2140h |
180h | PCIE_ECC0_DED_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 02A0 2180h |
1C0h | PCIE_ECC0_DED_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 02A0 21C0h |
200h | PCIE_ECC0_AGGR_ENABLE_SET | AGGR interrupt enable set Register | 02A0 2200h |
204h | PCIE_ECC0_AGGR_ENABLE_CLR | AGGR interrupt enable clear Register | 02A0 2204h |
208h | PCIE_ECC0_AGGR_STATUS_SET | AGGR interrupt status set Register | 02A0 2208h |
20Ch | PCIE_ECC0_AGGR_STATUS_CLR | AGGR interrupt status clear Register | 02A0 220Ch |
PCIE_ECC0_REV is shown in Figure 12-1885 and described in Table 12-3726.
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Revision parameters
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-5h | R-2h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 5h | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 1h | Minor version |
PCIE_ECC0_VECTOR is shown in Figure 12-1886 and described in Table 12-3728.
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ECC PCIE_ECC0_VECTOR Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R/W-X | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R/W-X | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R/W | X | |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
PCIE_ECC0_STAT is shown in Figure 12-1887 and described in Table 12-3730.
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Misc Status
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 200Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-X | R-5h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | X | |
10-0 | NUM_RAMS | R | 5h | Indicates the number of RAMS serviced by the ECC aggregator |
PCIE_ECC0_RESERVED_SVBUS_y is shown in Figure 12-1888 and described in Table 12-3732.
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Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.
Offset = 10h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Serial VBUS register data |
PCIE_ECC0_SEC_EOI_REG is shown in Figure 12-1889 and described in Table 12-3734.
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EOI Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 203Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
PCIE_ECC0_SEC_STATUS_REG0 is shown in Figure 12-1890 and described in Table 12-3736.
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Interrupt Status Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXI2VBUSM_MST_PEND | DIBRAM_RAMECC_PEND | AXISFIFO_RAMECC_PEND | AXIMFIFO_RAMECC_PEND | EDC_CTRL_PEND | ||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | AXI2VBUSM_MST_PEND | R/W1S | 0h | Interrupt Pending Status for axi2vbusm_mst_pend |
3 | DIBRAM_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for dibram_ramecc_pend |
2 | AXISFIFO_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for axisfifo_ramecc_pend |
1 | AXIMFIFO_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for aximfifo_ramecc_pend |
0 | EDC_CTRL_PEND | R/W1S | 0h | Interrupt Pending Status for edc_ctrl_pend |
PCIE_ECC0_SEC_ENABLE_SET_REG0 is shown in Figure 12-1891 and described in Table 12-3738.
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Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXI2VBUSM_MST_ENABLE_SET | DIBRAM_RAMECC_ENABLE_SET | AXISFIFO_RAMECC_ENABLE_SET | AXIMFIFO_RAMECC_ENABLE_SET | EDC_CTRL_ENABLE_SET | ||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | AXI2VBUSM_MST_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for axi2vbusm_mst_pend |
3 | DIBRAM_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for dibram_ramecc_pend |
2 | AXISFIFO_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for axisfifo_ramecc_pend |
1 | AXIMFIFO_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for aximfifo_ramecc_pend |
0 | EDC_CTRL_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for edc_ctrl_pend |
PCIE_ECC0_SEC_ENABLE_CLR_REG0 is shown in Figure 12-1892 and described in Table 12-3740.
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Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 20C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXI2VBUSM_MST_ENABLE_CLR | DIBRAM_RAMECC_ENABLE_CLR | AXISFIFO_RAMECC_ENABLE_CLR | AXIMFIFO_RAMECC_ENABLE_CLR | EDC_CTRL_ENABLE_CLR | ||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | AXI2VBUSM_MST_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for axi2vbusm_mst_pend |
3 | DIBRAM_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for dibram_ramecc_pend |
2 | AXISFIFO_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for axisfifo_ramecc_pend |
1 | AXIMFIFO_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for aximfifo_ramecc_pend |
0 | EDC_CTRL_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for edc_ctrl_pend |
PCIE_ECC0_DED_EOI_REG is shown in Figure 12-1893 and described in Table 12-3742.
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EOI Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 213Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
PCIE_ECC0_DED_STATUS_REG0 is shown in Figure 12-1894 and described in Table 12-3744.
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Interrupt Status Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXI2VBUSM_MST_PEND | DIBRAM_RAMECC_PEND | AXISFIFO_RAMECC_PEND | AXIMFIFO_RAMECC_PEND | EDC_CTRL_PEND | ||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | AXI2VBUSM_MST_PEND | R/W1S | 0h | Interrupt Pending Status for axi2vbusm_mst_pend |
3 | DIBRAM_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for dibram_ramecc_pend |
2 | AXISFIFO_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for axisfifo_ramecc_pend |
1 | AXIMFIFO_RAMECC_PEND | R/W1S | 0h | Interrupt Pending Status for aximfifo_ramecc_pend |
0 | EDC_CTRL_PEND | R/W1S | 0h | Interrupt Pending Status for edc_ctrl_pend |
PCIE_ECC0_DED_ENABLE_SET_REG0 is shown in Figure 12-1895 and described in Table 12-3746.
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Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXI2VBUSM_MST_ENABLE_SET | DIBRAM_RAMECC_ENABLE_SET | AXISFIFO_RAMECC_ENABLE_SET | AXIMFIFO_RAMECC_ENABLE_SET | EDC_CTRL_ENABLE_SET | ||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | AXI2VBUSM_MST_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for axi2vbusm_mst_pend |
3 | DIBRAM_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for dibram_ramecc_pend |
2 | AXISFIFO_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for axisfifo_ramecc_pend |
1 | AXIMFIFO_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for aximfifo_ramecc_pend |
0 | EDC_CTRL_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for edc_ctrl_pend |
PCIE_ECC0_DED_ENABLE_CLR_REG0 is shown in Figure 12-1896 and described in Table 12-3748.
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Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 21C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AXI2VBUSM_MST_ENABLE_CLR | DIBRAM_RAMECC_ENABLE_CLR | AXISFIFO_RAMECC_ENABLE_CLR | AXIMFIFO_RAMECC_ENABLE_CLR | EDC_CTRL_ENABLE_CLR | ||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | AXI2VBUSM_MST_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for axi2vbusm_mst_pend |
3 | DIBRAM_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for dibram_ramecc_pend |
2 | AXISFIFO_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for axisfifo_ramecc_pend |
1 | AXIMFIFO_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for aximfifo_ramecc_pend |
0 | EDC_CTRL_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for edc_ctrl_pend |
PCIE_ECC0_AGGR_ENABLE_SET is shown in Figure 12-1897 and described in Table 12-3750.
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AGGR interrupt enable set Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
PCIE_ECC0_AGGR_ENABLE_CLR is shown in Figure 12-1898 and described in Table 12-3752.
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AGGR interrupt enable clear Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
PCIE_ECC0_AGGR_STATUS_SET is shown in Figure 12-1899 and described in Table 12-3754.
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AGGR interrupt status set Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 2208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wincr | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | interrupt status set for parity errors |
PCIE_ECC0_AGGR_STATUS_CLR is shown in Figure 12-1900 and described in Table 12-3756.
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AGGR interrupt status clear Register
Instance | Physical Address |
---|---|
PCIE1_CORE_ECC_AGGR0 | 02A0 220Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wdecr | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | interrupt status clear for parity errors |