SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Figure 8-3 shows a high-level view of the MSMC module that includes the main interfaces, memory, and subunits.
MSMC directly incorporates on-chip SRAM controllers to provide the compute cluster with low-latency memory. In addition, the individual memory banks can maintain coherence with the connected caching masters as well as the system slave ports.