SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5539 lists the memory-mapped registers for the TIMER. All register offset addresses not listed in Table 12-5539 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
TIMER0_CFG | 0240 0000h |
TIMER1_CFG | 0241 0000h |
TIMER2_CFG | 0242 0000h |
TIMER3_CFG | 0243 0000h |
TIMER4_CFG | 0244 0000h |
TIMER5_CFG | 0245 0000h |
TIMER6_CFG | 0246 0000h |
TIMER7_CFG | 0247 0000h |
TIMER8_CFG | 0248 0000h |
TIMER9_CFG | 0249 0000h |
TIMER10_CFG | 024A 0000h |
TIMER11_CFG | 024B 0000h |
TIMER12_CFG | 024C 0000h |
TIMER13_CFG | 024D 0000h |
TIMER14_CFG | 024E 0000h |
TIMER15_CFG | 024F 0000h |
TIMER16_CFG | 0250 0000h |
TIMER17_CFG | 0251 0000h |
TIMER18_CFG | 0252 0000h |
TIMER19_CFG | 0253 0000h |
MCU_TIMER0_CFG | 4040 0000h |
MCU_TIMER1_CFG | 4041 0000h |
MCU_TIMER2_CFG | 4042 0000h |
MCU_TIMER3_CFG | 4043 0000h |
MCU_TIMER4_CFG | 4044 0000h |
MCU_TIMER5_CFG | 4045 0000h |
MCU_TIMER6_CFG | 4046 0000h |
MCU_TIMER7_CFG | 4047 0000h |
MCU_TIMER8_CFG | 4048 0000h |
MCU_TIMER9_CFG | 4049 0000h |
Offset | Acronym | Register Name | TIMER0_CFG Physical Address | TIMER1_CFG Physical Address | TIMER2_CFG Physical Address |
---|---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 0240 0000h | 0241 0000h | 0242 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 0240 0010h | 0241 0010h | 0242 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 0240 0020h | 0241 0020h | 0242 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 0240 0024h | 0241 0024h | 0242 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 0240 0028h | 0241 0028h | 0242 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 0240 002Ch | 0241 002Ch | 0242 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 0240 0030h | 0241 0030h | 0242 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 0240 0034h | 0241 0034h | 0242 0034h |
38h | TIMER_TCLR | Timer control register | 0240 0038h | 0241 0038h | 0242 0038h |
3Ch | TIMER_TCRR | Timer counter register | 0240 003Ch | 0241 003Ch | 0242 003Ch |
40h | TIMER_TLDR | Timer load register | 0240 0040h | 0241 0040h | 0242 0040h |
44h | TIMER_TTGR | Timer trigger register | 0240 0044h | 0241 0044h | 0242 0044h |
48h | TIMER_TWPS | Timer write-posted register | 0240 0048h | 0241 0048h | 0242 0048h |
4Ch | TIMER_TMAR | Timer match register | 0240 004Ch | 0241 004Ch | 0242 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 0240 0050h | 0241 0050h | 0242 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 0240 0054h | 0241 0054h | 0242 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 0240 0058h | 0241 0058h | 0242 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 0240 005Ch | 0241 005Ch | 0242 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 0240 0060h | 0241 0060h | 0242 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 0240 0064h | 0241 0064h | 0242 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 0240 0068h | 0241 0068h | 0242 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 0240 006Ch | 0241 006Ch | 0242 006Ch |
Offset | Acronym | Register Name | TIMER3_CFG Physical Address | TIMER4_CFG Physical Address | TIMER5_CFG Physical Address |
---|---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 0243 0000h | 0244 0000h | 0245 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 0243 0010h | 0244 0010h | 0245 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 0243 0020h | 0244 0020h | 0245 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 0243 0024h | 0244 0024h | 0245 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 0243 0028h | 0244 0028h | 0245 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 0243 002Ch | 0244 002Ch | 0245 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 0243 0030h | 0244 0030h | 0245 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 0243 0034h | 0244 0034h | 0245 0034h |
38h | TIMER_TCLR | Timer control register | 0243 0038h | 0244 0038h | 0245 0038h |
3Ch | TIMER_TCRR | Timer counter register | 0243 003Ch | 0244 003Ch | 0245 003Ch |
40h | TIMER_TLDR | Timer load register | 0243 0040h | 0244 0040h | 0245 0040h |
44h | TIMER_TTGR | Timer trigger register | 0243 0044h | 0244 0044h | 0245 0044h |
48h | TIMER_TWPS | Timer write-posted register | 0243 0048h | 0244 0048h | 0245 0048h |
4Ch | TIMER_TMAR | Timer match register | 0243 004Ch | 0244 004Ch | 0245 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 0243 0050h | 0244 0050h | 0245 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 0243 0054h | 0244 0054h | 0245 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 0243 0058h | 0244 0058h | 0245 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 0243 005Ch | 0244 005Ch | 0245 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 0243 0060h | 0244 0060h | 0245 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 0243 0064h | 0244 0064h | 0245 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 0243 0068h | 0244 0068h | 0245 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 0243 006Ch | 0244 006Ch | 0245 006Ch |
Offset | Acronym | Register Name | TIMER6_CFG Physical Address | TIMER7_CFG Physical Address | TIMER8_CFG Physical Address |
---|---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 0246 0000h | 0247 0000h | 0248 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 0246 0010h | 0247 0010h | 0248 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 0246 0020h | 0247 0020h | 0248 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 0246 0024h | 0247 0024h | 0248 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 0246 0028h | 0247 0028h | 0248 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 0246 002Ch | 0247 002Ch | 0248 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 0246 0030h | 0247 0030h | 0248 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 0246 0034h | 0247 0034h | 0248 0034h |
38h | TIMER_TCLR | Timer control register | 0246 0038h | 0247 0038h | 0248 0038h |
3Ch | TIMER_TCRR | Timer counter register | 0246 003Ch | 0247 003Ch | 0248 003Ch |
40h | TIMER_TLDR | Timer load register | 0246 0040h | 0247 0040h | 0248 0040h |
44h | TIMER_TTGR | Timer trigger register | 0246 0044h | 0247 0044h | 0248 0044h |
48h | TIMER_TWPS | Timer write-posted register | 0246 0048h | 0247 0048h | 0248 0048h |
4Ch | TIMER_TMAR | Timer match register | 0246 004Ch | 0247 004Ch | 0248 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 0246 0050h | 0247 0050h | 0248 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 0246 0054h | 0247 0054h | 0248 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 0246 0058h | 0247 0058h | 0248 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 0246 005Ch | 0247 005Ch | 0248 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 0246 0060h | 0247 0060h | 0248 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 0246 0064h | 0247 0064h | 0248 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 0246 0068h | 0247 0068h | 0248 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 0246 006Ch | 0247 006Ch | 0248 006Ch |
Offset | Acronym | Register Name | TIMER9_CFG Physical Address | TIMER10_CFG Physical Address | TIMER11_CFG Physical Address |
---|---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 0249 0000h | 024A 0000h | 024B 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 0249 0010h | 024A 0010h | 024B 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 0249 0020h | 024A 0020h | 024B 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 0249 0024h | 024A 0024h | 024B 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 0249 0028h | 024A 0028h | 024B 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 0249 002Ch | 024A 002Ch | 024B 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 0249 0030h | 024A 0030h | 024B 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 0249 0034h | 024A 0034h | 024B 0034h |
38h | TIMER_TCLR | Timer control register | 0249 0038h | 024A 0038h | 024B 0038h |
3Ch | TIMER_TCRR | Timer counter register | 0249 003Ch | 024A 003Ch | 024B 003Ch |
40h | TIMER_TLDR | Timer load register | 0249 0040h | 024A 0040h | 024B 0040h |
44h | TIMER_TTGR | Timer trigger register | 0249 0044h | 024A 0044h | 024B 0044h |
48h | TIMER_TWPS | Timer write-posted register | 0249 0048h | 024A 0048h | 024B 0048h |
4Ch | TIMER_TMAR | Timer match register | 0249 004Ch | 024A 004Ch | 024B 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 0249 0050h | 024A 0050h | 024B 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 0249 0054h | 024A 0054h | 024B 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 0249 0058h | 024A 0058h | 024B 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 0249 005Ch | 024A 005Ch | 024B 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 0249 0060h | 024A 0060h | 024B 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 0249 0064h | 024A 0064h | 024B 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 0249 0068h | 024A 0068h | 024B 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 0249 006Ch | 024A 006Ch | 024B 006Ch |
Offset | Acronym | Register Name | TIMER12_CFG Physical Address | TIMER13_CFG Physical Address | TIMER14_CFG Physical Address |
---|---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 024C 0000h | 024D 0000h | 024E 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 024C 0010h | 024D 0010h | 024E 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 024C 0020h | 024D 0020h | 024E 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 024C 0024h | 024D 0024h | 024E 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 024C 0028h | 024D 0028h | 024E 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 024C 002Ch | 024D 002Ch | 024E 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 024C 0030h | 024D 0030h | 024E 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 024C 0034h | 024D 0034h | 024E 0034h |
38h | TIMER_TCLR | Timer control register | 024C 0038h | 024D 0038h | 024E 0038h |
3Ch | TIMER_TCRR | Timer counter register | 024C 003Ch | 024D 003Ch | 024E 003Ch |
40h | TIMER_TLDR | Timer load register | 024C 0040h | 024D 0040h | 024E 0040h |
44h | TIMER_TTGR | Timer trigger register | 024C 0044h | 024D 0044h | 024E 0044h |
48h | TIMER_TWPS | Timer write-posted register | 024C 0048h | 024D 0048h | 024E 0048h |
4Ch | TIMER_TMAR | Timer match register | 024C 004Ch | 024D 004Ch | 024E 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 024C 0050h | 024D 0050h | 024E 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 024C 0054h | 024D 0054h | 024E 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 024C 0058h | 024D 0058h | 024E 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 024C 005Ch | 024D 005Ch | 024E 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 024C 0060h | 024D 0060h | 024E 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 024C 0064h | 024D 0064h | 024E 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 024C 0068h | 024D 0068h | 024E 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 024C 006Ch | 024D 006Ch | 024E 006Ch |
Offset | Acronym | Register Name | TIMER15_CFG Physical Address | TIMER16_CFG Physical Address | TIMER17_CFG Physical Address |
---|---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 024F 0000h | 0250 0000h | 0251 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 024F 0010h | 0250 0010h | 0251 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 024F 0020h | 0250 0020h | 0251 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 024F 0024h | 0250 0024h | 0251 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 024F 0028h | 0250 0028h | 0251 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 024F 002Ch | 0250 002Ch | 0251 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 024F 0030h | 0250 0030h | 0251 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 024F 0034h | 0250 0034h | 0251 0034h |
38h | TIMER_TCLR | Timer control register | 024F 0038h | 0250 0038h | 0251 0038h |
3Ch | TIMER_TCRR | Timer counter register | 024F 003Ch | 0250 003Ch | 0251 003Ch |
40h | TIMER_TLDR | Timer load register | 024F 0040h | 0250 0040h | 0251 0040h |
44h | TIMER_TTGR | Timer trigger register | 024F 0044h | 0250 0044h | 0251 0044h |
48h | TIMER_TWPS | Timer write-posted register | 024F 0048h | 0250 0048h | 0251 0048h |
4Ch | TIMER_TMAR | Timer match register | 024F 004Ch | 0250 004Ch | 0251 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 024F 0050h | 0250 0050h | 0251 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 024F 0054h | 0250 0054h | 0251 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 024F 0058h | 0250 0058h | 0251 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 024F 005Ch | 0250 005Ch | 0251 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 024F 0060h | 0250 0060h | 0251 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 024F 0064h | 0250 0064h | 0251 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 024F 0068h | 0250 0068h | 0251 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 024F 006Ch | 0250 006Ch | 0251 006Ch |
Offset | Acronym | Register Name | TIMER18_CFG Physical Address | TIMER19_CFG Physical Address |
---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 0252 0000h | 0253 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 0252 0010h | 0253 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 0252 0020h | 0253 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 0252 0024h | 0253 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 0252 0028h | 0253 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 0252 002Ch | 0253 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 0252 0030h | 0253 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 0252 0034h | 0253 0034h |
38h | TIMER_TCLR | Timer control register | 0252 0038h | 0253 0038h |
3Ch | TIMER_TCRR | Timer counter register | 0252 003Ch | 0253 003Ch |
40h | TIMER_TLDR | Timer load register | 0252 0040h | 0253 0040h |
44h | TIMER_TTGR | Timer trigger register | 0252 0044h | 0253 0044h |
48h | TIMER_TWPS | Timer write-posted register | 0252 0048h | 0253 0048h |
4Ch | TIMER_TMAR | Timer match register | 0252 004Ch | 0253 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 0252 0050h | 0253 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 0252 0054h | 0253 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 0252 0058h | 0253 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 0252 005Ch | 0253 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 0252 0060h | 0253 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 0252 0064h | 0253 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 0252 0068h | 0253 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 0252 006Ch | 0253 006Ch |
Offset | Acronym | Register Name | MCU_TIMER0_CFG Physical Address | MCU_TIMER1_CFG Physical Address | MCU_TIMER2_CFG Physical Address |
---|---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 4040 0000h | 4041 0000h | 4042 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 4040 0010h | 4041 0010h | 4042 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 4040 0020h | 4041 0020h | 4042 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 4040 0024h | 4041 0024h | 4042 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 4040 0028h | 4041 0028h | 4042 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 4040 002Ch | 4041 002Ch | 4042 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 4040 0030h | 4041 0030h | 4042 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 4040 0034h | 4041 0034h | 4042 0034h |
38h | TIMER_TCLR | Timer control register | 4040 0038h | 4041 0038h | 4042 0038h |
3Ch | TIMER_TCRR | Timer counter register | 4040 003Ch | 4041 003Ch | 4042 003Ch |
40h | TIMER_TLDR | Timer load register | 4040 0040h | 4041 0040h | 4042 0040h |
44h | TIMER_TTGR | Timer trigger register | 4040 0044h | 4041 0044h | 4042 0044h |
48h | TIMER_TWPS | Timer write-posted register | 4040 0048h | 4041 0048h | 4042 0048h |
4Ch | TIMER_TMAR | Timer match register | 4040 004Ch | 4041 004Ch | 4042 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 4040 0050h | 4041 0050h | 4042 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 4040 0054h | 4041 0054h | 4042 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 4040 0058h | 4041 0058h | 4042 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 4040 005Ch | 4041 005Ch | 4042 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 4040 0060h | 4041 0060h | 4042 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 4040 0064h | 4041 0064h | 4042 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 4040 0068h | 4041 0068h | 4042 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 4040 006Ch | 4041 006Ch | 4042 006Ch |
Offset | Acronym | Register Name | MCU_TIMER3_CFG Physical Address | MCU_TIMER4_CFG Physical Address |
---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 4043 0000h | 4044 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 4043 0010h | 4044 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 4043 0020h | 4044 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 4043 0024h | 4044 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 4043 0028h | 4044 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 4043 002Ch | 4044 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 4043 0030h | 4044 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 4043 0034h | 4044 0034h |
38h | TIMER_TCLR | Timer control register | 4043 0038h | 4044 0038h |
3Ch | TIMER_TCRR | Timer counter register | 4043 003Ch | 4044 003Ch |
40h | TIMER_TLDR | Timer load register | 4043 0040h | 4044 0040h |
44h | TIMER_TTGR | Timer trigger register | 4043 0044h | 4044 0044h |
48h | TIMER_TWPS | Timer write-posted register | 4043 0048h | 4044 0048h |
4Ch | TIMER_TMAR | Timer match register | 4043 004Ch | 4044 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 4043 0050h | 4044 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 4043 0054h | 4044 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 4043 0058h | 4044 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 4043 005Ch | 4044 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 4043 0060h | 4044 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 4043 0064h | 4044 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 4043 0068h | 4044 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 4043 006Ch | 4044 006Ch |
Offset | Acronym | Register Name | MCU_TIMER5_CFG Physical Address | MCU_TIMER6_CFG Physical Address |
---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 4045 0000h | 4046 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 4045 0010h | 4046 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 4045 0020h | 4046 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 4045 0024h | 4046 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 4045 0028h | 4046 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 4045 002Ch | 4046 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 4045 0030h | 4046 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 4045 0034h | 4046 0034h |
38h | TIMER_TCLR | Timer control register | 4045 0038h | 4046 0038h |
3Ch | TIMER_TCRR | Timer counter register | 4045 003Ch | 4046 003Ch |
40h | TIMER_TLDR | Timer load register | 4045 0040h | 4046 0040h |
44h | TIMER_TTGR | Timer trigger register | 4045 0044h | 4046 0044h |
48h | TIMER_TWPS | Timer write-posted register | 4045 0048h | 4046 0048h |
4Ch | TIMER_TMAR | Timer match register | 4045 004Ch | 4046 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 4045 0050h | 4046 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 4045 0054h | 4046 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 4045 0058h | 4046 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 4045 005Ch | 4046 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 4045 0060h | 4046 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 4045 0064h | 4046 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 4045 0068h | 4046 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 4045 006Ch | 4046 006Ch |
Offset | Acronym | Register Name | MCU_TIMER7_CFG Physical Address | MCU_TIMER8_CFG Physical Address | MCU_TIMER9_CFG Physical Address |
---|---|---|---|---|---|
0h | TIMER_TIDR | Revision register | 4047 0000h | 4048 0000h | 4049 0000h |
10h | TIMER_TIOCP_CFG | CBASS0 Configuration register | 4047 0010h | 4048 0010h | 4049 0010h |
20h | TIMER_IRQ_EOI | End-Of-Interrupt register | 4047 0020h | 4048 0020h | 4049 0020h |
24h | TIMER_IRQSTATUS_RAW | Timer raw status register | 4047 0024h | 4048 0024h | 4049 0024h |
28h | TIMER_IRQSTATUS | Timer status register | 4047 0028h | 4048 0028h | 4049 0028h |
2Ch | TIMER_IRQSTATUS_SET | Interrupt enable register | 4047 002Ch | 4048 002Ch | 4049 002Ch |
30h | TIMER_IRQSTATUS_CLR | Interrupt disable register | 4047 0030h | 4048 0030h | 4049 0030h |
34h | TIMER_IRQWAKEEN | Wake-up enable register | 4047 0034h | 4048 0034h | 4049 0034h |
38h | TIMER_TCLR | Timer control register | 4047 0038h | 4048 0038h | 4049 0038h |
3Ch | TIMER_TCRR | Timer counter register | 4047 003Ch | 4048 003Ch | 4049 003Ch |
40h | TIMER_TLDR | Timer load register | 4047 0040h | 4048 0040h | 4049 0040h |
44h | TIMER_TTGR | Timer trigger register | 4047 0044h | 4048 0044h | 4049 0044h |
48h | TIMER_TWPS | Timer write-posted register | 4047 0048h | 4048 0048h | 4049 0048h |
4Ch | TIMER_TMAR | Timer match register | 4047 004Ch | 4048 004Ch | 4049 004Ch |
50h | TIMER_TCAR1 | First captured value of the timer counter | 4047 0050h | 4048 0050h | 4049 0050h |
54h | TIMER_TSICR | Timer synchronous interface control register | 4047 0054h | 4048 0054h | 4049 0054h |
58h | TIMER_TCAR2 | Second captured value of the timer counter | 4047 0058h | 4048 0058h | 4049 0058h |
5Ch | TIMER_TPIR | Timer positive increment register | 4047 005Ch | 4048 005Ch | 4049 005Ch |
60h | TIMER_TNIR | Timer negative increment register | 4047 0060h | 4048 0060h | 4049 0060h |
64h | TIMER_TCVR | Timer CVR counter register | 4047 0064h | 4048 0064h | 4049 0064h |
68h | TIMER_TOCR | Timer overflow counter register | 4047 0068h | 4048 0068h | 4049 0068h |
6Ch | TIMER_TOWR | Timer overflow wrapping register | 4047 006Ch | 4048 006Ch | 4049 006Ch |
TIMER_TIDR is shown in Figure 12-2898 and described in Table 12-5551.
Return to Summary Table.
This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0000h |
TIMER1_CFG | 0241 0000h |
TIMER2_CFG | 0242 0000h |
TIMER3_CFG | 0243 0000h |
TIMER4_CFG | 0244 0000h |
TIMER5_CFG | 0245 0000h |
TIMER6_CFG | 0246 0000h |
TIMER7_CFG | 0247 0000h |
TIMER8_CFG | 0248 0000h |
TIMER9_CFG | 0249 0000h |
TIMER10_CFG | 024A 0000h |
TIMER11_CFG | 024B 0000h |
TIMER12_CFG | 024C 0000h |
TIMER13_CFG | 024D 0000h |
TIMER14_CFG | 024E 0000h |
TIMER15_CFG | 024F 0000h |
TIMER16_CFG | 0250 0000h |
TIMER17_CFG | 0251 0000h |
TIMER18_CFG | 0252 0000h |
TIMER19_CFG | 0253 0000h |
MCU_TIMER0_CFG | 4040 0000h |
MCU_TIMER1_CFG | 4041 0000h |
MCU_TIMER2_CFG | 4042 0000h |
MCU_TIMER3_CFG | 4043 0000h |
MCU_TIMER4_CFG | 4044 0000h |
MCU_TIMER5_CFG | 4045 0000h |
MCU_TIMER6_CFG | 4046 0000h |
MCU_TIMER7_CFG | 4047 0000h |
MCU_TIMER8_CFG | 4048 0000h |
MCU_TIMER9_CFG | 4049 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION | |||||||||||||||||||||||||||||||
R-5000 3900h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REVISION | R | 5000 3900h | IP Revision |
TIMER_TIOCP_CFG is shown in Figure 12-2899 and described in Table 12-5553.
Return to Summary Table.
This register controls the various parameters of the CBASS0/MCU_CBASS0 interface.
Some of the timers features described in this section may not be supported on this family of devices. For more information, see Timers Not Supported Features.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0010h |
TIMER1_CFG | 0241 0010h |
TIMER2_CFG | 0242 0010h |
TIMER3_CFG | 0243 0010h |
TIMER4_CFG | 0244 0010h |
TIMER5_CFG | 0245 0010h |
TIMER6_CFG | 0246 0010h |
TIMER7_CFG | 0247 0010h |
TIMER8_CFG | 0248 0010h |
TIMER9_CFG | 0249 0010h |
TIMER10_CFG | 024A 0010h |
TIMER11_CFG | 024B 0010h |
TIMER12_CFG | 024C 0010h |
TIMER13_CFG | 024D 0010h |
TIMER14_CFG | 024E 0010h |
TIMER15_CFG | 024F 0010h |
TIMER16_CFG | 0250 0010h |
TIMER17_CFG | 0251 0010h |
TIMER18_CFG | 0252 0010h |
TIMER19_CFG | 0253 0010h |
MCU_TIMER0_CFG | 4040 0010h |
MCU_TIMER1_CFG | 4041 0010h |
MCU_TIMER2_CFG | 4042 0010h |
MCU_TIMER3_CFG | 4043 0010h |
MCU_TIMER4_CFG | 4044 0010h |
MCU_TIMER5_CFG | 4045 0010h |
MCU_TIMER6_CFG | 4046 0010h |
MCU_TIMER7_CFG | 4047 0010h |
MCU_TIMER8_CFG | 4048 0010h |
MCU_TIMER9_CFG | 4049 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLEMODE | EMUFREE | SOFTRESET | ||||
R-0h | R/W-2h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | IDLEMODE | R/W | 2h | Power management, req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally, that is, regardless of the IP module internal requirements. Back-up mode, for debug only. 1h = No-idle mode: local target never enters idle state. Back-up mode, for debug only. 2h = Smart-idle mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module should not generate (IRQ- request-related) wake-up events. 3h = Smart-idle wake-up-capable mode: local target idle state eventually follows (acknowledges) the system clock stop requests, depending on the IP module internal requirements. IP module may generate (IRQ- request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP modules wake-up output(s) is (are) implemented. |
1 | EMUFREE | R/W | 0h | Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free, regardless of PINSUSPENDN value. |
0 | SOFTRESET | R/W | 0h | Software reset Read 0h = Reset done, no pending action |
TIMER_IRQ_EOI is shown in Figure 12-2900 and described in Table 12-5555.
Return to Summary Table.
Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration).
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0020h |
TIMER1_CFG | 0241 0020h |
TIMER2_CFG | 0242 0020h |
TIMER3_CFG | 0243 0020h |
TIMER4_CFG | 0244 0020h |
TIMER5_CFG | 0245 0020h |
TIMER6_CFG | 0246 0020h |
TIMER7_CFG | 0247 0020h |
TIMER8_CFG | 0248 0020h |
TIMER9_CFG | 0249 0020h |
TIMER10_CFG | 024A 0020h |
TIMER11_CFG | 024B 0020h |
TIMER12_CFG | 024C 0020h |
TIMER13_CFG | 024D 0020h |
TIMER14_CFG | 024E 0020h |
TIMER15_CFG | 024F 0020h |
TIMER16_CFG | 0250 0020h |
TIMER17_CFG | 0251 0020h |
TIMER18_CFG | 0252 0020h |
TIMER19_CFG | 0253 0020h |
MCU_TIMER0_CFG | 4040 0020h |
MCU_TIMER1_CFG | 4041 0020h |
MCU_TIMER2_CFG | 4042 0020h |
MCU_TIMER3_CFG | 4043 0020h |
MCU_TIMER4_CFG | 4044 0020h |
MCU_TIMER5_CFG | 4045 0020h |
MCU_TIMER6_CFG | 4046 0020h |
MCU_TIMER7_CFG | 4047 0020h |
MCU_TIMER8_CFG | 4048 0020h |
MCU_TIMER9_CFG | 4049 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINE_NUMBER | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | LINE_NUMBER | R/W | 0h | Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0). |
TIMER_IRQSTATUS_RAW is shown in Figure 12-2901 and described in Table 12-5557.
Return to Summary Table.
Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0024h |
TIMER1_CFG | 0241 0024h |
TIMER2_CFG | 0242 0024h |
TIMER3_CFG | 0243 0024h |
TIMER4_CFG | 0244 0024h |
TIMER5_CFG | 0245 0024h |
TIMER6_CFG | 0246 0024h |
TIMER7_CFG | 0247 0024h |
TIMER8_CFG | 0248 0024h |
TIMER9_CFG | 0249 0024h |
TIMER10_CFG | 024A 0024h |
TIMER11_CFG | 024B 0024h |
TIMER12_CFG | 024C 0024h |
TIMER13_CFG | 024D 0024h |
TIMER14_CFG | 024E 0024h |
TIMER15_CFG | 024F 0024h |
TIMER16_CFG | 0250 0024h |
TIMER17_CFG | 0251 0024h |
TIMER18_CFG | 0252 0024h |
TIMER19_CFG | 0253 0024h |
MCU_TIMER0_CFG | 4040 0024h |
MCU_TIMER1_CFG | 4041 0024h |
MCU_TIMER2_CFG | 4042 0024h |
MCU_TIMER3_CFG | 4043 0024h |
MCU_TIMER4_CFG | 4044 0024h |
MCU_TIMER5_CFG | 4045 0024h |
MCU_TIMER6_CFG | 4046 0024h |
MCU_TIMER7_CFG | 4047 0024h |
MCU_TIMER8_CFG | 4048 0024h |
MCU_TIMER9_CFG | 4049 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TCAR_IT_FLAG | OVF_IT_FLAG | MAT_IT_FLAG | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | TCAR_IT_FLAG | R/W | 0h | IRQ status for capture |
1 | OVF_IT_FLAG | R/W | 0h | IRQ status for overflow |
0 | MAT_IT_FLAG | R/W | 0h | IRQ status for match |
TIMER_IRQSTATUS is shown in Figure 12-2902 and described in Table 12-5559.
Return to Summary Table.
Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled).
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0028h |
TIMER1_CFG | 0241 0028h |
TIMER2_CFG | 0242 0028h |
TIMER3_CFG | 0243 0028h |
TIMER4_CFG | 0244 0028h |
TIMER5_CFG | 0245 0028h |
TIMER6_CFG | 0246 0028h |
TIMER7_CFG | 0247 0028h |
TIMER8_CFG | 0248 0028h |
TIMER9_CFG | 0249 0028h |
TIMER10_CFG | 024A 0028h |
TIMER11_CFG | 024B 0028h |
TIMER12_CFG | 024C 0028h |
TIMER13_CFG | 024D 0028h |
TIMER14_CFG | 024E 0028h |
TIMER15_CFG | 024F 0028h |
TIMER16_CFG | 0250 0028h |
TIMER17_CFG | 0251 0028h |
TIMER18_CFG | 0252 0028h |
TIMER19_CFG | 0253 0028h |
MCU_TIMER0_CFG | 4040 0028h |
MCU_TIMER1_CFG | 4041 0028h |
MCU_TIMER2_CFG | 4042 0028h |
MCU_TIMER3_CFG | 4043 0028h |
MCU_TIMER4_CFG | 4044 0028h |
MCU_TIMER5_CFG | 4045 0028h |
MCU_TIMER6_CFG | 4046 0028h |
MCU_TIMER7_CFG | 4047 0028h |
MCU_TIMER8_CFG | 4048 0028h |
MCU_TIMER9_CFG | 4049 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TCAR_IT_FLAG | OVF_IT_FLAG | MAT_IT_FLAG | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | TCAR_IT_FLAG | R/W | 0h | IRQ status for capture |
1 | OVF_IT_FLAG | R/W | 0h | IRQ status for overflow |
0 | MAT_IT_FLAG | R/W | 0h | IRQ status for match |
TIMER_IRQSTATUS_SET is shown in Figure 12-2903 and described in Table 12-5561.
Return to Summary Table.
Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 002Ch |
TIMER1_CFG | 0241 002Ch |
TIMER2_CFG | 0242 002Ch |
TIMER3_CFG | 0243 002Ch |
TIMER4_CFG | 0244 002Ch |
TIMER5_CFG | 0245 002Ch |
TIMER6_CFG | 0246 002Ch |
TIMER7_CFG | 0247 002Ch |
TIMER8_CFG | 0248 002Ch |
TIMER9_CFG | 0249 002Ch |
TIMER10_CFG | 024A 002Ch |
TIMER11_CFG | 024B 002Ch |
TIMER12_CFG | 024C 002Ch |
TIMER13_CFG | 024D 002Ch |
TIMER14_CFG | 024E 002Ch |
TIMER15_CFG | 024F 002Ch |
TIMER16_CFG | 0250 002Ch |
TIMER17_CFG | 0251 002Ch |
TIMER18_CFG | 0252 002Ch |
TIMER19_CFG | 0253 002Ch |
MCU_TIMER0_CFG | 4040 002Ch |
MCU_TIMER1_CFG | 4041 002Ch |
MCU_TIMER2_CFG | 4042 002Ch |
MCU_TIMER3_CFG | 4043 002Ch |
MCU_TIMER4_CFG | 4044 002Ch |
MCU_TIMER5_CFG | 4045 002Ch |
MCU_TIMER6_CFG | 4046 002Ch |
MCU_TIMER7_CFG | 4047 002Ch |
MCU_TIMER8_CFG | 4048 002Ch |
MCU_TIMER9_CFG | 4049 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TCAR_EN_FLAG | OVF_EN_FLAG | MAT_EN_FLAG | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | TCAR_EN_FLAG | R/W | 0h | IRQ enable for compare |
1 | OVF_EN_FLAG | R/W | 0h | IRQ enable for overflow |
0 | MAT_EN_FLAG | R/W | 0h | IRQ enable for match |
TIMER_IRQSTATUS_CLR is shown in Figure 12-2904 and described in Table 12-5563.
Return to Summary Table.
Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0030h |
TIMER1_CFG | 0241 0030h |
TIMER2_CFG | 0242 0030h |
TIMER3_CFG | 0243 0030h |
TIMER4_CFG | 0244 0030h |
TIMER5_CFG | 0245 0030h |
TIMER6_CFG | 0246 0030h |
TIMER7_CFG | 0247 0030h |
TIMER8_CFG | 0248 0030h |
TIMER9_CFG | 0249 0030h |
TIMER10_CFG | 024A 0030h |
TIMER11_CFG | 024B 0030h |
TIMER12_CFG | 024C 0030h |
TIMER13_CFG | 024D 0030h |
TIMER14_CFG | 024E 0030h |
TIMER15_CFG | 024F 0030h |
TIMER16_CFG | 0250 0030h |
TIMER17_CFG | 0251 0030h |
TIMER18_CFG | 0252 0030h |
TIMER19_CFG | 0253 0030h |
MCU_TIMER0_CFG | 4040 0030h |
MCU_TIMER1_CFG | 4041 0030h |
MCU_TIMER2_CFG | 4042 0030h |
MCU_TIMER3_CFG | 4043 0030h |
MCU_TIMER4_CFG | 4044 0030h |
MCU_TIMER5_CFG | 4045 0030h |
MCU_TIMER6_CFG | 4046 0030h |
MCU_TIMER7_CFG | 4047 0030h |
MCU_TIMER8_CFG | 4048 0030h |
MCU_TIMER9_CFG | 4049 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TCAR_EN_FLAG | OVF_EN_FLAG | MAT_EN_FLAG | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | TCAR_EN_FLAG | R/W | 0h | IRQ enable for compare |
1 | OVF_EN_FLAG | R/W | 0h | IRQ enable for overflow |
0 | MAT_EN_FLAG | R/W | 0h | IRQ enable for match |
TIMER_IRQWAKEEN is shown in Figure 12-2905 and described in Table 12-5565.
Return to Summary Table.
Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0034h |
TIMER1_CFG | 0241 0034h |
TIMER2_CFG | 0242 0034h |
TIMER3_CFG | 0243 0034h |
TIMER4_CFG | 0244 0034h |
TIMER5_CFG | 0245 0034h |
TIMER6_CFG | 0246 0034h |
TIMER7_CFG | 0247 0034h |
TIMER8_CFG | 0248 0034h |
TIMER9_CFG | 0249 0034h |
TIMER10_CFG | 024A 0034h |
TIMER11_CFG | 024B 0034h |
TIMER12_CFG | 024C 0034h |
TIMER13_CFG | 024D 0034h |
TIMER14_CFG | 024E 0034h |
TIMER15_CFG | 024F 0034h |
TIMER16_CFG | 0250 0034h |
TIMER17_CFG | 0251 0034h |
TIMER18_CFG | 0252 0034h |
TIMER19_CFG | 0253 0034h |
MCU_TIMER0_CFG | 4040 0034h |
MCU_TIMER1_CFG | 4041 0034h |
MCU_TIMER2_CFG | 4042 0034h |
MCU_TIMER3_CFG | 4043 0034h |
MCU_TIMER4_CFG | 4044 0034h |
MCU_TIMER5_CFG | 4045 0034h |
MCU_TIMER6_CFG | 4046 0034h |
MCU_TIMER7_CFG | 4047 0034h |
MCU_TIMER8_CFG | 4048 0034h |
MCU_TIMER9_CFG | 4049 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TCAR_WUP_ENA | OVF_WUP_ENA | MAT_WUP_ENA | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | TCAR_WUP_ENA | R/W | 0h | Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled. |
1 | OVF_WUP_ENA | R/W | 0h | Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled. |
0 | MAT_WUP_ENA | R/W | 0h | Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled. |
TIMER_TCLR is shown in Figure 12-2906 and described in Table 12-5567.
Return to Summary Table.
This register controls optional features specific to the timer functionality.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0038h |
TIMER1_CFG | 0241 0038h |
TIMER2_CFG | 0242 0038h |
TIMER3_CFG | 0243 0038h |
TIMER4_CFG | 0244 0038h |
TIMER5_CFG | 0245 0038h |
TIMER6_CFG | 0246 0038h |
TIMER7_CFG | 0247 0038h |
TIMER8_CFG | 0248 0038h |
TIMER9_CFG | 0249 0038h |
TIMER10_CFG | 024A 0038h |
TIMER11_CFG | 024B 0038h |
TIMER12_CFG | 024C 0038h |
TIMER13_CFG | 024D 0038h |
TIMER14_CFG | 024E 0038h |
TIMER15_CFG | 024F 0038h |
TIMER16_CFG | 0250 0038h |
TIMER17_CFG | 0251 0038h |
TIMER18_CFG | 0252 0038h |
TIMER19_CFG | 0253 0038h |
MCU_TIMER0_CFG | 4040 0038h |
MCU_TIMER1_CFG | 4041 0038h |
MCU_TIMER2_CFG | 4042 0038h |
MCU_TIMER3_CFG | 4043 0038h |
MCU_TIMER4_CFG | 4044 0038h |
MCU_TIMER5_CFG | 4045 0038h |
MCU_TIMER6_CFG | 4046 0038h |
MCU_TIMER7_CFG | 4047 0038h |
MCU_TIMER8_CFG | 4048 0038h |
MCU_TIMER9_CFG | 4049 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPO_CFG | CAPT_MODE | PT | TRG | TCM | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCPWM | CE | PRE | PTV | AR | ST | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | GPO_CFG | R/W | 0h | General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input. |
13 | CAPT_MODE | R/W | 0h | Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in TIMER_TCAR1. 1h = Capture on second event: Capture the second enabled capture event in TIMER_TCAR1 and the second enabled capture event in TIMER_TCAR2. |
12 | PT | R/W | 0h | Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation. |
11-10 | TRG | R/W | 0h | Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved. |
9-8 | TCM | R/W | 0h | Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h = Capture on falling edges of EVENT_CAPTURE pin 3h = Capture on both edges of EVENT_CAPTURE pin. |
7 | SCPWM | R/W | 0h | Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode. |
6 | CE | R/W | 0h | Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable. |
5 | PRE | R/W | 0h | Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter. |
4-2 | PTV | R/W | 0h | Prescale clock timer value |
1 | AR | R/W | 0h | Autoreload mode 0h = One shot timer 1h = Autoreload timer |
0 | ST | R/W | 0h | Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0), this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer. |
TIMER_TCRR is shown in Figure 12-2907 and described in Table 12-5569.
Return to Summary Table.
This register holds the value of the internal counter.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 003Ch |
TIMER1_CFG | 0241 003Ch |
TIMER2_CFG | 0242 003Ch |
TIMER3_CFG | 0243 003Ch |
TIMER4_CFG | 0244 003Ch |
TIMER5_CFG | 0245 003Ch |
TIMER6_CFG | 0246 003Ch |
TIMER7_CFG | 0247 003Ch |
TIMER8_CFG | 0248 003Ch |
TIMER9_CFG | 0249 003Ch |
TIMER10_CFG | 024A 003Ch |
TIMER11_CFG | 024B 003Ch |
TIMER12_CFG | 024C 003Ch |
TIMER13_CFG | 024D 003Ch |
TIMER14_CFG | 024E 003Ch |
TIMER15_CFG | 024F 003Ch |
TIMER16_CFG | 0250 003Ch |
TIMER17_CFG | 0251 003Ch |
TIMER18_CFG | 0252 003Ch |
TIMER19_CFG | 0253 003Ch |
MCU_TIMER0_CFG | 4040 003Ch |
MCU_TIMER1_CFG | 4041 003Ch |
MCU_TIMER2_CFG | 4042 003Ch |
MCU_TIMER3_CFG | 4043 003Ch |
MCU_TIMER4_CFG | 4044 003Ch |
MCU_TIMER5_CFG | 4045 003Ch |
MCU_TIMER6_CFG | 4046 003Ch |
MCU_TIMER7_CFG | 4047 003Ch |
MCU_TIMER8_CFG | 4048 003Ch |
MCU_TIMER9_CFG | 4049 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMER_COUNTER | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TIMER_COUNTER | R/W | 0h | Value of timer counter |
TIMER_TLDR is shown in Figure 12-2908 and described in Table 12-5571.
Return to Summary Table.
This register holds the timer load value.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0040h |
TIMER1_CFG | 0241 0040h |
TIMER2_CFG | 0242 0040h |
TIMER3_CFG | 0243 0040h |
TIMER4_CFG | 0244 0040h |
TIMER5_CFG | 0245 0040h |
TIMER6_CFG | 0246 0040h |
TIMER7_CFG | 0247 0040h |
TIMER8_CFG | 0248 0040h |
TIMER9_CFG | 0249 0040h |
TIMER10_CFG | 024A 0040h |
TIMER11_CFG | 024B 0040h |
TIMER12_CFG | 024C 0040h |
TIMER13_CFG | 024D 0040h |
TIMER14_CFG | 024E 0040h |
TIMER15_CFG | 024F 0040h |
TIMER16_CFG | 0250 0040h |
TIMER17_CFG | 0251 0040h |
TIMER18_CFG | 0252 0040h |
TIMER19_CFG | 0253 0040h |
MCU_TIMER0_CFG | 4040 0040h |
MCU_TIMER1_CFG | 4041 0040h |
MCU_TIMER2_CFG | 4042 0040h |
MCU_TIMER3_CFG | 4043 0040h |
MCU_TIMER4_CFG | 4044 0040h |
MCU_TIMER5_CFG | 4045 0040h |
MCU_TIMER6_CFG | 4046 0040h |
MCU_TIMER7_CFG | 4047 0040h |
MCU_TIMER8_CFG | 4048 0040h |
MCU_TIMER9_CFG | 4049 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOAD_VALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LOAD_VALUE | R/W | 0h | Timer counter value loaded on overflow in autoreload mode or on TIMER_TTGR write access. LOAD_VALUE must be different than the timer overflow value (FFFF FFFFh). |
TIMER_TTGR is shown in Figure 12-2909 and described in Table 12-5573.
Return to Summary Table.
This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0044h |
TIMER1_CFG | 0241 0044h |
TIMER2_CFG | 0242 0044h |
TIMER3_CFG | 0243 0044h |
TIMER4_CFG | 0244 0044h |
TIMER5_CFG | 0245 0044h |
TIMER6_CFG | 0246 0044h |
TIMER7_CFG | 0247 0044h |
TIMER8_CFG | 0248 0044h |
TIMER9_CFG | 0249 0044h |
TIMER10_CFG | 024A 0044h |
TIMER11_CFG | 024B 0044h |
TIMER12_CFG | 024C 0044h |
TIMER13_CFG | 024D 0044h |
TIMER14_CFG | 024E 0044h |
TIMER15_CFG | 024F 0044h |
TIMER16_CFG | 0250 0044h |
TIMER17_CFG | 0251 0044h |
TIMER18_CFG | 0252 0044h |
TIMER19_CFG | 0253 0044h |
MCU_TIMER0_CFG | 4040 0044h |
MCU_TIMER1_CFG | 4041 0044h |
MCU_TIMER2_CFG | 4042 0044h |
MCU_TIMER3_CFG | 4043 0044h |
MCU_TIMER4_CFG | 4044 0044h |
MCU_TIMER5_CFG | 4045 0044h |
MCU_TIMER6_CFG | 4046 0044h |
MCU_TIMER7_CFG | 4047 0044h |
MCU_TIMER8_CFG | 4048 0044h |
MCU_TIMER9_CFG | 4049 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TTGR_VALUE | |||||||||||||||||||||||||||||||
R/W-Fh | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TTGR_VALUE | R/W | Fh | Writing to the TIMER_TTGR register causes the TIMER_TCRR to be loaded from TIMER_TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TIMER_TCLR register. |
TIMER_TWPS is shown in Figure 12-2910 and described in Table 12-5575.
Return to Summary Table.
This register contains the write posting bits for all writable functional registers.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0048h |
TIMER1_CFG | 0241 0048h |
TIMER2_CFG | 0242 0048h |
TIMER3_CFG | 0243 0048h |
TIMER4_CFG | 0244 0048h |
TIMER5_CFG | 0245 0048h |
TIMER6_CFG | 0246 0048h |
TIMER7_CFG | 0247 0048h |
TIMER8_CFG | 0248 0048h |
TIMER9_CFG | 0249 0048h |
TIMER10_CFG | 024A 0048h |
TIMER11_CFG | 024B 0048h |
TIMER12_CFG | 024C 0048h |
TIMER13_CFG | 024D 0048h |
TIMER14_CFG | 024E 0048h |
TIMER15_CFG | 024F 0048h |
TIMER16_CFG | 0250 0048h |
TIMER17_CFG | 0251 0048h |
TIMER18_CFG | 0252 0048h |
TIMER19_CFG | 0253 0048h |
MCU_TIMER0_CFG | 4040 0048h |
MCU_TIMER1_CFG | 4041 0048h |
MCU_TIMER2_CFG | 4042 0048h |
MCU_TIMER3_CFG | 4043 0048h |
MCU_TIMER4_CFG | 4044 0048h |
MCU_TIMER5_CFG | 4045 0048h |
MCU_TIMER6_CFG | 4046 0048h |
MCU_TIMER7_CFG | 4047 0048h |
MCU_TIMER8_CFG | 4048 0048h |
MCU_TIMER9_CFG | 4049 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | W_PEND_TOWR | W_PEND_TOCR | |||||
R-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
W_PEND_TCVR | W_PEND_TNIR | W_PEND_TPIR | W_PEND_TMAR | W_PEND_TTGR | W_PEND_TLDR | W_PEND_TCRR | W_PEND_TCLR |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | W_PEND_TOWR | R | 0h | Write pending for the TIMER_TOWR register Read 0h = No write pending Read 1h = Write pending. |
8 | W_PEND_TOCR | R | 0h | Write pending for the TIMER_TOCR register Read 0h = No write pending Read 1h = Write pending. |
7 | W_PEND_TCVR | R | 0h | Write pending for the TIMER_TCVR register Read 0h = No write pending Read 1h = Write pending. |
6 | W_PEND_TNIR | R | 0h | Write pending for the TIMER_TNIR register Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending. |
5 | W_PEND_TPIR | R | 0h | Write pending for the TIMER_TPIR register Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending. |
4 | W_PEND_TMAR | R | 0h | Write pending for the TIMER_TMAR register Read 0h = No write pending Read 1h = Write pending. |
3 | W_PEND_TTGR | R | 0h | Write pending for the TIMER_TTGR register Read 0h = No write pending Read 1h = Write pending. |
2 | W_PEND_TLDR | R | 0h | Write pending for the TIMER_TLDR register Read 0h = No write pending Read 1h = Write pending. |
1 | W_PEND_TCRR | R | 0h | Write pending for the TIMER_TCRR register Read 0h = No write pending Read 1h = Write pending. |
0 | W_PEND_TCLR | R | 0h | Write pending for the TIMER_TCLR register Read 0h = No write pending Read 1h = Write pending. |
TIMER_TMAR is shown in Figure 12-2911 and described in Table 12-5577.
Return to Summary Table.
The TIMER_TMAR register holds the match value to be compared with the counter's value.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 004Ch |
TIMER1_CFG | 0241 004Ch |
TIMER2_CFG | 0242 004Ch |
TIMER3_CFG | 0243 004Ch |
TIMER4_CFG | 0244 004Ch |
TIMER5_CFG | 0245 004Ch |
TIMER6_CFG | 0246 004Ch |
TIMER7_CFG | 0247 004Ch |
TIMER8_CFG | 0248 004Ch |
TIMER9_CFG | 0249 004Ch |
TIMER10_CFG | 024A 004Ch |
TIMER11_CFG | 024B 004Ch |
TIMER12_CFG | 024C 004Ch |
TIMER13_CFG | 024D 004Ch |
TIMER14_CFG | 024E 004Ch |
TIMER15_CFG | 024F 004Ch |
TIMER16_CFG | 0250 004Ch |
TIMER17_CFG | 0251 004Ch |
TIMER18_CFG | 0252 004Ch |
TIMER19_CFG | 0253 004Ch |
MCU_TIMER0_CFG | 4040 004Ch |
MCU_TIMER1_CFG | 4041 004Ch |
MCU_TIMER2_CFG | 4042 004Ch |
MCU_TIMER3_CFG | 4043 004Ch |
MCU_TIMER4_CFG | 4044 004Ch |
MCU_TIMER5_CFG | 4045 004Ch |
MCU_TIMER6_CFG | 4046 004Ch |
MCU_TIMER7_CFG | 4047 004Ch |
MCU_TIMER8_CFG | 4048 004Ch |
MCU_TIMER9_CFG | 4049 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMPARE_VALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMPARE_VALUE | R/W | 0h | Value to be compared to the timer counter |
TIMER_TCAR1 is shown in Figure 12-2912 and described in Table 12-5579.
Return to Summary Table.
This register holds the first captured value of the counter register.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0050h |
TIMER1_CFG | 0241 0050h |
TIMER2_CFG | 0242 0050h |
TIMER3_CFG | 0243 0050h |
TIMER4_CFG | 0244 0050h |
TIMER5_CFG | 0245 0050h |
TIMER6_CFG | 0246 0050h |
TIMER7_CFG | 0247 0050h |
TIMER8_CFG | 0248 0050h |
TIMER9_CFG | 0249 0050h |
TIMER10_CFG | 024A 0050h |
TIMER11_CFG | 024B 0050h |
TIMER12_CFG | 024C 0050h |
TIMER13_CFG | 024D 0050h |
TIMER14_CFG | 024E 0050h |
TIMER15_CFG | 024F 0050h |
TIMER16_CFG | 0250 0050h |
TIMER17_CFG | 0251 0050h |
TIMER18_CFG | 0252 0050h |
TIMER19_CFG | 0253 0050h |
MCU_TIMER0_CFG | 4040 0050h |
MCU_TIMER1_CFG | 4041 0050h |
MCU_TIMER2_CFG | 4042 0050h |
MCU_TIMER3_CFG | 4043 0050h |
MCU_TIMER4_CFG | 4044 0050h |
MCU_TIMER5_CFG | 4045 0050h |
MCU_TIMER6_CFG | 4046 0050h |
MCU_TIMER7_CFG | 4047 0050h |
MCU_TIMER8_CFG | 4048 0050h |
MCU_TIMER9_CFG | 4049 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_VALUE1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAPTURE_VALUE1 | R | 0h | First timer counter value captured on an external event trigger |
TIMER_TSICR is shown in Figure 12-2913 and described in Table 12-5581.
Return to Summary Table.
Timer synchronous interface control register
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0054h |
TIMER1_CFG | 0241 0054h |
TIMER2_CFG | 0242 0054h |
TIMER3_CFG | 0243 0054h |
TIMER4_CFG | 0244 0054h |
TIMER5_CFG | 0245 0054h |
TIMER6_CFG | 0246 0054h |
TIMER7_CFG | 0247 0054h |
TIMER8_CFG | 0248 0054h |
TIMER9_CFG | 0249 0054h |
TIMER10_CFG | 024A 0054h |
TIMER11_CFG | 024B 0054h |
TIMER12_CFG | 024C 0054h |
TIMER13_CFG | 024D 0054h |
TIMER14_CFG | 024E 0054h |
TIMER15_CFG | 024F 0054h |
TIMER16_CFG | 0250 0054h |
TIMER17_CFG | 0251 0054h |
TIMER18_CFG | 0252 0054h |
TIMER19_CFG | 0253 0054h |
MCU_TIMER0_CFG | 4040 0054h |
MCU_TIMER1_CFG | 4041 0054h |
MCU_TIMER2_CFG | 4042 0054h |
MCU_TIMER3_CFG | 4043 0054h |
MCU_TIMER4_CFG | 4044 0054h |
MCU_TIMER5_CFG | 4045 0054h |
MCU_TIMER6_CFG | 4046 0054h |
MCU_TIMER7_CFG | 4047 0054h |
MCU_TIMER8_CFG | 4048 0054h |
MCU_TIMER9_CFG | 4049 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | READ_AFTER_IDLE | READ_MODE | POSTED | SFT | RESERVED | ||
R-0h | W-0h | W-0h | R/W-1h | R/W-0h | R-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | READ_AFTER_IDLE | W | 0h | Select if the synchronization mechanism used for first TIMER_TCRR read operation
after idle state is active. Field values: 0h = The synchronization mechanism is enabled. 1h = The synchronization mechanism is disabled. |
3 | READ_MODE | W | 0h | Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read posted. 1h = When the module is configured in non-posted mode (POSTED = '0'), the read operation is executed as read non-posted. |
2 | POSTED | R/W | 1h | Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active. |
1 | SFT | R/W | 0h | This bit resets the TIMER_TSICR[2] POSTED bit to the default value determined by the hardware configuration set at design integration time. 0h = Reset is inactive. 1h = Reset is asserted. |
0 | RESERVED | R | 0h | Reserved |
TIMER_TCAR2 is shown in Figure 12-2914 and described in Table 12-5583.
Return to Summary Table.
This register holds the second captured value of the counter register.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0058h |
TIMER1_CFG | 0241 0058h |
TIMER2_CFG | 0242 0058h |
TIMER3_CFG | 0243 0058h |
TIMER4_CFG | 0244 0058h |
TIMER5_CFG | 0245 0058h |
TIMER6_CFG | 0246 0058h |
TIMER7_CFG | 0247 0058h |
TIMER8_CFG | 0248 0058h |
TIMER9_CFG | 0249 0058h |
TIMER10_CFG | 024A 0058h |
TIMER11_CFG | 024B 0058h |
TIMER12_CFG | 024C 0058h |
TIMER13_CFG | 024D 0058h |
TIMER14_CFG | 024E 0058h |
TIMER15_CFG | 024F 0058h |
TIMER16_CFG | 0250 0058h |
TIMER17_CFG | 0251 0058h |
TIMER18_CFG | 0252 0058h |
TIMER19_CFG | 0253 0058h |
MCU_TIMER0_CFG | 4040 0058h |
MCU_TIMER1_CFG | 4041 0058h |
MCU_TIMER2_CFG | 4042 0058h |
MCU_TIMER3_CFG | 4043 0058h |
MCU_TIMER4_CFG | 4044 0058h |
MCU_TIMER5_CFG | 4045 0058h |
MCU_TIMER6_CFG | 4046 0058h |
MCU_TIMER7_CFG | 4047 0058h |
MCU_TIMER8_CFG | 4048 0058h |
MCU_TIMER9_CFG | 4049 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPTURE_VALUE2 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAPTURE_VALUE2 | R | 0h | Second timer counter value captured on an external event trigger |
TIMER_TPIR is shown in Figure 12-2915 and described in Table 12-5585.
Return to Summary Table.
This register is used for 1-ms tick generation. The TIMER_TPIR register holds the value of the positive increment. The value of this register is added to the value of TIMER_TCVR to determine whether next value loaded in TIMER_TCRR is the subperiod value or the overperiod value.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 005Ch |
TIMER1_CFG | 0241 005Ch |
TIMER2_CFG | 0242 005Ch |
TIMER3_CFG | 0243 005Ch |
TIMER4_CFG | 0244 005Ch |
TIMER5_CFG | 0245 005Ch |
TIMER6_CFG | 0246 005Ch |
TIMER7_CFG | 0247 005Ch |
TIMER8_CFG | 0248 005Ch |
TIMER9_CFG | 0249 005Ch |
TIMER10_CFG | 024A 005Ch |
TIMER11_CFG | 024B 005Ch |
TIMER12_CFG | 024C 005Ch |
TIMER13_CFG | 024D 005Ch |
TIMER14_CFG | 024E 005Ch |
TIMER15_CFG | 024F 005Ch |
TIMER16_CFG | 0250 005Ch |
TIMER17_CFG | 0251 005Ch |
TIMER18_CFG | 0252 005Ch |
TIMER19_CFG | 0253 005Ch |
MCU_TIMER0_CFG | 4040 005Ch |
MCU_TIMER1_CFG | 4041 005Ch |
MCU_TIMER2_CFG | 4042 005Ch |
MCU_TIMER3_CFG | 4043 005Ch |
MCU_TIMER4_CFG | 4044 005Ch |
MCU_TIMER5_CFG | 4045 005Ch |
MCU_TIMER6_CFG | 4046 005Ch |
MCU_TIMER7_CFG | 4047 005Ch |
MCU_TIMER8_CFG | 4048 005Ch |
MCU_TIMER9_CFG | 4049 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POSITIVE_INC_VALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | POSITIVE_INC_VALUE | R/W | 0h | Value of the positive increment |
TIMER_TNIR is shown in Figure 12-2916 and described in Table 12-5587.
Return to Summary Table.
This register is used for 1-ms tick generation. The TIMER_TNIR register holds the value of the negative increment. The value of this register is added to the value of the TIMER_TCVR to determine whether next value loaded in TIMER_TCRR is the subperiod value or the overperiod value.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0060h |
TIMER1_CFG | 0241 0060h |
TIMER2_CFG | 0242 0060h |
TIMER3_CFG | 0243 0060h |
TIMER4_CFG | 0244 0060h |
TIMER5_CFG | 0245 0060h |
TIMER6_CFG | 0246 0060h |
TIMER7_CFG | 0247 0060h |
TIMER8_CFG | 0248 0060h |
TIMER9_CFG | 0249 0060h |
TIMER10_CFG | 024A 0060h |
TIMER11_CFG | 024B 0060h |
TIMER12_CFG | 024C 0060h |
TIMER13_CFG | 024D 0060h |
TIMER14_CFG | 024E 0060h |
TIMER15_CFG | 024F 0060h |
TIMER16_CFG | 0250 0060h |
TIMER17_CFG | 0251 0060h |
TIMER18_CFG | 0252 0060h |
TIMER19_CFG | 0253 0060h |
MCU_TIMER0_CFG | 4040 0060h |
MCU_TIMER1_CFG | 4041 0060h |
MCU_TIMER2_CFG | 4042 0060h |
MCU_TIMER3_CFG | 4043 0060h |
MCU_TIMER4_CFG | 4044 0060h |
MCU_TIMER5_CFG | 4045 0060h |
MCU_TIMER6_CFG | 4046 0060h |
MCU_TIMER7_CFG | 4047 0060h |
MCU_TIMER8_CFG | 4048 0060h |
MCU_TIMER9_CFG | 4049 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NEGATIVE_INV_VALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NEGATIVE_INV_VALUE | R/W | 0h | Value of the negative increment |
TIMER_TCVR is shown in Figure 12-2917 and described in Table 12-5589.
Return to Summary Table.
This register is used for 1-ms tick generation. The TIMER_TCVR register determines whether next value loaded in TIMER_TCRR is the subperiod value or the overperiod value.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0064h |
TIMER1_CFG | 0241 0064h |
TIMER2_CFG | 0242 0064h |
TIMER3_CFG | 0243 0064h |
TIMER4_CFG | 0244 0064h |
TIMER5_CFG | 0245 0064h |
TIMER6_CFG | 0246 0064h |
TIMER7_CFG | 0247 0064h |
TIMER8_CFG | 0248 0064h |
TIMER9_CFG | 0249 0064h |
TIMER10_CFG | 024A 0064h |
TIMER11_CFG | 024B 0064h |
TIMER12_CFG | 024C 0064h |
TIMER13_CFG | 024D 0064h |
TIMER14_CFG | 024E 0064h |
TIMER15_CFG | 024F 0064h |
TIMER16_CFG | 0250 0064h |
TIMER17_CFG | 0251 0064h |
TIMER18_CFG | 0252 0064h |
TIMER19_CFG | 0253 0064h |
MCU_TIMER0_CFG | 4040 0064h |
MCU_TIMER1_CFG | 4041 0064h |
MCU_TIMER2_CFG | 4042 0064h |
MCU_TIMER3_CFG | 4043 0064h |
MCU_TIMER4_CFG | 4044 0064h |
MCU_TIMER5_CFG | 4045 0064h |
MCU_TIMER6_CFG | 4046 0064h |
MCU_TIMER7_CFG | 4047 0064h |
MCU_TIMER8_CFG | 4048 0064h |
MCU_TIMER9_CFG | 4049 0064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTER_VALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNTER_VALUE | R/W | 0h | Value of CVR counter |
TIMER_TOCR is shown in Figure 12-2918 and described in Table 12-5591.
Return to Summary Table.
This register is used to mask the tick interrupt for a selected number of ticks.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 0068h |
TIMER1_CFG | 0241 0068h |
TIMER2_CFG | 0242 0068h |
TIMER3_CFG | 0243 0068h |
TIMER4_CFG | 0244 0068h |
TIMER5_CFG | 0245 0068h |
TIMER6_CFG | 0246 0068h |
TIMER7_CFG | 0247 0068h |
TIMER8_CFG | 0248 0068h |
TIMER9_CFG | 0249 0068h |
TIMER10_CFG | 024A 0068h |
TIMER11_CFG | 024B 0068h |
TIMER12_CFG | 024C 0068h |
TIMER13_CFG | 024D 0068h |
TIMER14_CFG | 024E 0068h |
TIMER15_CFG | 024F 0068h |
TIMER16_CFG | 0250 0068h |
TIMER17_CFG | 0251 0068h |
TIMER18_CFG | 0252 0068h |
TIMER19_CFG | 0253 0068h |
MCU_TIMER0_CFG | 4040 0068h |
MCU_TIMER1_CFG | 4041 0068h |
MCU_TIMER2_CFG | 4042 0068h |
MCU_TIMER3_CFG | 4043 0068h |
MCU_TIMER4_CFG | 4044 0068h |
MCU_TIMER5_CFG | 4045 0068h |
MCU_TIMER6_CFG | 4046 0068h |
MCU_TIMER7_CFG | 4047 0068h |
MCU_TIMER8_CFG | 4048 0068h |
MCU_TIMER9_CFG | 4049 0068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OVF_COUNTER_VALUE | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reads return 0. |
23-0 | OVF_COUNTER_VALUE | R/W | 0h | Number of overflow events |
TIMER_TOWR is shown in Figure 12-2919 and described in Table 12-5593.
Return to Summary Table.
This register holds the number of masked overflow interrupts.
Instance | Physical Address |
---|---|
TIMER0_CFG | 0240 006Ch |
TIMER1_CFG | 0241 006Ch |
TIMER2_CFG | 0242 006Ch |
TIMER3_CFG | 0243 006Ch |
TIMER4_CFG | 0244 006Ch |
TIMER5_CFG | 0245 006Ch |
TIMER6_CFG | 0246 006Ch |
TIMER7_CFG | 0247 006Ch |
TIMER8_CFG | 0248 006Ch |
TIMER9_CFG | 0249 006Ch |
TIMER10_CFG | 024A 006Ch |
TIMER11_CFG | 024B 006Ch |
TIMER12_CFG | 024C 006Ch |
TIMER13_CFG | 024D 006Ch |
TIMER14_CFG | 024E 006Ch |
TIMER15_CFG | 024F 006Ch |
TIMER16_CFG | 0250 006Ch |
TIMER17_CFG | 0251 006Ch |
TIMER18_CFG | 0252 006Ch |
TIMER19_CFG | 0253 006Ch |
MCU_TIMER0_CFG | 4040 006Ch |
MCU_TIMER1_CFG | 4041 006Ch |
MCU_TIMER2_CFG | 4042 006Ch |
MCU_TIMER3_CFG | 4043 006Ch |
MCU_TIMER4_CFG | 4044 006Ch |
MCU_TIMER5_CFG | 4045 006Ch |
MCU_TIMER6_CFG | 4046 006Ch |
MCU_TIMER7_CFG | 4047 006Ch |
MCU_TIMER8_CFG | 4048 006Ch |
MCU_TIMER9_CFG | 4049 006Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OVF_WRAPPING_VALUE | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reads return 0. |
23-0 | OVF_WRAPPING_VALUE | R/W | 0h | Number of masked interrupts |