SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are ten timer modules integrated in the device MCU domain - MCU_TIMER0 through MCU_TIMER9. Figure 12-2888 shows their integration in the device.
Each timer instance is supplied by dedicated TIMERCLKn clock mux. For MCU_TIMERn+1 the TIMERCLKn output is further muxed with the TIMERn_POTIMERPWM output.
Table 12-5519 through Table 12-5521 summarize the integration of MCU_TIMER0 through MCU_TIMER9 in device MCU domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MCU_TIMER0 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER1 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER2 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER3 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER4 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER5 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER6 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER7 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER8 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
MCU_TIMER9 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCU_TIMER0 | MCU_TIMER0_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER0 Interface Clock |
MCU_TIMER0_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER0 Functional Clock. Output of multiplexor MCU_TIMERCLK0 MUX controlled by CTRLMMR_MCU_TIMER0_CLKSEL[2-0] CLK_SEL in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER1 | MCU_TIMER1_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER1 Interface Clock |
MCU_TIMER1_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER1 Functional Clock. Output of multiplexor MCU_TIMERCLK1
MUX controlled by CTRLMMR_MCU_TIMER1_CLKSEL[2-0] CLK_SEL or MCU_TIMER0_POTIMERPWM in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER2 | MCU_TIMER2_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER2 Interface Clock |
MCU_TIMER2_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER2 Functional Clock. Output of multiplexor MCU_TIMERCLK2 MUX controlled by CTRLMMR_MCU_TIMER2_CLKSEL[2-0] CLK_SEL in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER3 | MCU_TIMER3_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER3 Interface Clock |
MCU_TIMER3_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER3 Functional Clock. Output of multiplexor MCU_TIMERCLK3
MUX controlled by CTRLMMR_MCU_TIMER3_CLKSEL[2-0] CLK_SEL or MCU_TIMER2_POTIMERPWM in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER4 | MCU_TIMER4_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER4 Interface Clock |
MCU_TIMER4_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER4 Functional Clock. Output of multiplexor MCU_TIMERCLK4 MUX controlled by CTRLMMR_MCU_TIMER4_CLKSEL[2-0] CLK_SEL in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER5 | MCU_TIMER5_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER5 Interface Clock |
MCU_TIMER5_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER5 Functional Clock. Output of multiplexor MCU_TIMERCLK5
MUX controlled by CTRLMMR_MCU_TIMER5_CLKSEL[2-0] CLK_SEL or MCU_TIMER4_POTIMERPWM in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER6 | MCU_TIMER6_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER6 Interface Clock |
MCU_TIMER6_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER6 Functional Clock. Output of multiplexor MCU_TIMERCLK6 MUX controlled by CTRLMMR_MCU_TIMER6_CLKSEL[2-0] CLK_SEL in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER7 | MCU_TIMER7_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER7 Interface Clock |
MCU_TIMER7_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER7 Functional Clock. Output of multiplexor MCU_TIMERCLK7
MUX controlled by CTRLMMR_MCU_TIMER7_CLKSEL[2-0] CLK_SEL or MCU_TIMER6_POTIMERPWM in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER8 | MCU_TIMER8_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER8 Interface Clock |
MCU_TIMER8_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER8 Functional Clock. Output of multiplexor MCU_TIMERCLK8 MUX controlled by CTRLMMR_MCU_TIMER8_CLKSEL[2-0] CLK_SEL in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
MCU_TIMER9 | MCU_TIMER9_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_TIMER9 Interface Clock |
MCU_TIMER9_FCLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_TIMER9 Functional Clock. Output of multiplexor MCU_TIMERCLK9
MUX controlled by CTRLMMR_MCU_TIMER9_CLKSEL[2-0] CLK_SEL or MCU_TIMER8_POTIMERPWM in Control Module (CTRL_MMR) | |
MCU_SYSCLK0/4 | PLLCTRL0 | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
MCU_PLL2_HSDIV2_CLKOUT | MCU_PLL2_HSDIV2 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
WKUP_LFXOSC0_CLKOUT | WKUP_LFXOSC0 | |||
CPTS_GENF0 | MCU_CPSW0 | |||
CLK_32K_RC | WKUP_RC_OSC_12M | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCU_TIMER0 | MCU_TIMER0_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER0 |
MCU_TIMER1 | MCU_TIMER1_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER1 |
MCU_TIMER2 | MCU_TIMER2_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER2 |
MCU_TIMER3 | MCU_TIMER3_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER3 |
MCU_TIMER4 | MCU_TIMER4_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER4 |
MCU_TIMER5 | MCU_TIMER5_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER5 |
MCU_TIMER6 | MCU_TIMER6_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER6 |
MCU_TIMER7 | MCU_TIMER7_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER7 |
MCU_TIMER8 | MCU_TIMER8_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER8 |
MCU_TIMER9 | MCU_TIMER9_RST | MOD_G_RST | LPSC0 | Asyncronous Reset to MCU_TIMER9 |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_TIMER0 | MCU_TIMER0_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_452 | R5FSS0_CORE0 | MCU_TIMER0 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_452 | R5FSS0_CORE1 | MCU_TIMER0 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_38 | MCU_R5FSS0_CORE0 | MCU_TIMER0 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_38 | MCU_R5FSS0_CORE1 | MCU_TIMER0 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_54 | MCU_ESM0 | MCU_TIMER0 Interrupt Request | Level | ||
GIC500_SPI_IN_848 | COMPUTE_CLUSTER0 | MCU_TIMER0 Interrupt Request | Level | ||
MCU_TIMER1 | MCU_TIMER1_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_453 | R5FSS0_CORE0 | MCU_TIMER1 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_453 | R5FSS0_CORE1 | MCU_TIMER1 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_39 | MCU_R5FSS0_CORE0 | MCU_TIMER1 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_39 | MCU_R5FSS0_CORE1 | MCU_TIMER1 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_55 | MCU_ESM0 | MCU_TIMER1 Interrupt Request | Level | ||
GIC500_SPI_IN_849 | COMPUTE_CLUSTER0 | MCU_TIMER1 Interrupt Request | Level | ||
MCU_TIMER2 | MCU_TIMER2_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_454 | R5FSS0_CORE0 | MCU_TIMER2 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_454 | R5FSS0_CORE1 | MCU_TIMER2 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_40 | MCU_R5FSS0_CORE0 | MCU_TIMER2 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_40 | MCU_R5FSS0_CORE1 | MCU_TIMER2 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_56 | MCU_ESM0 | MCU_TIMER2 Interrupt Request | Level | ||
GIC500_SPI_IN_850 | COMPUTE_CLUSTER0 | MCU_TIMER2 Interrupt Request | Level | ||
MCU_TIMER3 | MCU_TIMER3_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_455 | R5FSS0_CORE0 | MCU_TIMER3 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_455 | R5FSS0_CORE1 | MCU_TIMER3 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_41 | MCU_R5FSS0_CORE0 | MCU_TIMER3 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_41 | MCU_R5FSS0_CORE1 | MCU_TIMER3 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_57 | MCU_ESM0 | MCU_TIMER3 Interrupt Request | Level | ||
GIC500_SPI_IN_851 | COMPUTE_CLUSTER0 | MCU_TIMER3 Interrupt Request | Level | ||
MCU_TIMER4 | MCU_TIMER4_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_456 | R5FSS0_CORE0 | MCU_TIMER4 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_456 | R5FSS0_CORE1 | MCU_TIMER4 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_108 | MCU_R5FSS0_CORE0 | MCU_TIMER4 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_108 | MCU_R5FSS0_CORE1 | MCU_TIMER4 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_58 | MCU_ESM0 | MCU_TIMER4 Interrupt Request | Level | ||
GIC500_SPI_IN_852 | COMPUTE_CLUSTER0 | MCU_TIMER4 Interrupt Request | Level | ||
MCU_TIMER5 | MCU_TIMER5_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_457 | R5FSS0_CORE0 | MCU_TIMER5 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_457 | R5FSS0_CORE1 | MCU_TIMER5 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_109 | MCU_R5FSS0_CORE0 | MCU_TIMER5 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_109 | MCU_R5FSS0_CORE1 | MCU_TIMER5 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_59 | MCU_ESM0 | MCU_TIMER5 Interrupt Request | Level | ||
GIC500_SPI_IN_853 | COMPUTE_CLUSTER0 | MCU_TIMER5 Interrupt Request | Level | ||
MCU_TIMER6 | MCU_TIMER6_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_458 | R5FSS0_CORE0 | MCU_TIMER6 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_458 | R5FSS0_CORE1 | MCU_TIMER6 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_110 | MCU_R5FSS0_CORE0 | MCU_TIMER6 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_110 | MCU_R5FSS0_CORE1 | MCU_TIMER6 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_60 | MCU_ESM0 | MCU_TIMER6 Interrupt Request | Level | ||
GIC500_SPI_IN_854 | COMPUTE_CLUSTER0 | MCU_TIMER6 Interrupt Request | Level | ||
MCU_TIMER7 | MCU_TIMER7_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_459 | R5FSS0_CORE0 | MCU_TIMER7 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_459 | R5FSS0_CORE1 | MCU_TIMER7 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_111 | MCU_R5FSS0_CORE0 | MCU_TIMER7 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_111 | MCU_R5FSS0_CORE1 | MCU_TIMER7 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_61 | MCU_ESM0 | MCU_TIMER7 Interrupt Request | Level | ||
GIC500_SPI_IN_855 | COMPUTE_CLUSTER0 | MCU_TIMER7 Interrupt Request | Level | ||
MCU_TIMER8 | MCU_TIMER8_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_460 | R5FSS0_CORE0 | MCU_TIMER8 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_460 | R5FSS0_CORE1 | MCU_TIMER8 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_112 | MCU_R5FSS0_CORE0 | MCU_TIMER8 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_112 | MCU_R5FSS0_CORE1 | MCU_TIMER8 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_62 | MCU_ESM0 | MCU_TIMER8 Interrupt Request | Level | ||
GIC500_SPI_IN_856 | COMPUTE_CLUSTER0 | MCU_TIMER8 Interrupt Request | Level | ||
MCU_TIMER9 | MCU_TIMER9_INTR_PEND_0 | R5FSS0_CORE0_INTR_IN_461 | R5FSS0_CORE0 | MCU_TIMER9 Interrupt Request | Level |
R5FSS0_CORE1_INTR_IN_461 | R5FSS0_CORE1 | MCU_TIMER9 Interrupt Request | Level | ||
MCU_R5FSS0_CORE0_INTR_IN_113 | MCU_R5FSS0_CORE0 | MCU_TIMER9 Interrupt Request | Level | ||
MCU_R5FSS0_CORE1_INTR_IN_113 | MCU_R5FSS0_CORE1 | MCU_TIMER9 Interrupt Request | Level | ||
MCU_ESM0_LVL_IN_63 | MCU_ESM0 | MCU_TIMER9 Interrupt Request | Level | ||
GIC500_SPI_IN_857 | COMPUTE_CLUSTER0 | MCU_TIMER9 Interrupt Request | Level |