SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-293 lists the memory-mapped registers for the UDMASS_UDMAP0_CFG_RFLOW. All register offset addresses not listed in Table 10-293 should be considered as reserved locations and the register contents should not be modified.
The UDMA-P Rx Flow Table Registers region is accessed by setting the cdma_cfg_rsel signal to 1 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 0000h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_UDMAP0_CFG_RFLOW Physical Address | MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW Physical Address |
---|---|---|---|---|
0h + formula | UDMA_RFA_j | Rx Flow Config Register A | 30D0 0000h + formula | 2840 0000h + formula |
4h + formula | UDMA_RFB_j | Rx Flow Config Register B | 30D0 0004h + formula | 2840 0004h + formula |
8h + formula | UDMA_RFC_j | Rx Flow Config Register C | 30D0 0008h + formula | 2840 0008h + formula |
Ch + formula | UDMA_RFD_j | Rx Flow Config Register D | 30D0 000Ch + formula | 2840 000Ch + formula |
10h + formula | UDMA_RFE_j | Rx Flow Config Register E | 30D0 0010h + formula | 2840 0010h + formula |
14h + formula | UDMA_RFF_j | Rx Flow Config Register F | 30D0 0014h + formula | 2840 0014h + formula |
18h + formula | UDMA_RFG_j | Rx Flow Config Register G | 30D0 0018h + formula | 2840 0018h + formula |
1Ch + formula | UDMA_RFH_j | Rx Flow Config Register H | 30D0 001Ch + formula | 2840 001Ch + formula |
UDMA_RFA_j is shown in Figure 10-97 and described in Table 10-295.
Return to Summary Table.
The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this register are as follows:
Offset = 0h + (j * 40h); where
j = 0h to 95h for NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
j = 0h to 5Fh for MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 0000h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EINFO | PSINFO | ERR_HANDLING | DESC_TYPE | PS_LOC | SOP_OFF | |
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SOP_OFF | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DEST_QNUM | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEST_QNUM | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30 | EINFO | R/W | 0h | Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear, the port DMA will clear the Extended Packet Info Present bit in the PD and will drop any Timestamp or SW Data words that are presented from the back end application. If this bit is set, the port DMA will set the Extended Packet Info Block Present bit in the PD and will copy any Timestamp or SW Data words that are presented across the Rx streaming interface into the Extended Packet Info Block words in the descriptor. If no Timestamp or SW Data words are presented from the back end application, the port DMA will overwrite the fields in the PD with zeroes. |
29 | PSINFO | R/W | 0h | Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear, the port DMA will set the PS word count to 0 in the PD and will drop any PS words that are presented from the back end application. If this bit is set, the port DMA will set the PS word count to the value given by the back end application and will copy the PS words from the back end application to the location |
28 | ERR_HANDLING | R/W | 0h | Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues/pools they were allocated from 1 = Starvation errors result in subsequent re-try of the descriptor allocation operation. In this mode, the DMA will save it's internal operational state back to the internal state RAM without issuing an advance operation to it's internal FIFO buffers. This results in the DMA re-initiating the data transfer at a later time with the intention that additional free buffers and/or descriptors will have been added. |
27-26 | DESC_TYPE | R/W | 0h | Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED |
25 | PS_LOC | R/W | 0h | Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared, the DMA will clear the Protocol Specific Region Location bit in the PD and will place the Protocol Specific Words at the end of the Packet Descriptor. If this bit is set, the DMA will set the Protocol Specific Region Location bit in the PD and will place the Protocol Specific Words at the beginning of the data buffer. When this mode is used, it is required that the resulting target data buffer pointer (which is calculated by adding the host_rx_sop_offset to the original buffer pointer in the Packet Descriptor) is aligned to a 32-bit boundary to avoid unwanted buffer truncation as the DMA will round up to the next 32-bit aligned boundary. |
24-16 | SOP_OFF | R/W | 0h | Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the minimum size of a buffer in the system. Valid values are 0 - 255 bytes. Note that for monolithic packets the value of this field must always be initialized to be greater than or equal to 4 times the maximum number of protocol specific 32-bit words that are required by any of the packet types that will be transferred by this channel. This is important as the primary purpose of this field is to ensure that space is left in the descriptor to place the protocol specific information without overwriting or being overwritten by the Rx data. The secondary purpose of this field is to allow space to be left prior to the data in the descriptor in case header information needs to be added as the packet is passed thorough the system. |
15-0 | DEST_QNUM | R/W | 0h | Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto. |
UDMA_RFB_j is shown in Figure 10-98 and described in Table 10-297.
Return to Summary Table.
The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this register are as follows:
Offset = 4h + (j * 40h); where
j = 0h to 95h for NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
j = 0h to 5Fh for MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 0004h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 0004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SRCTAG_HI | SRCTAG_LO | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSTTAG_HI | DSTTAG_LO | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | SRCTAG_HI | R/W | 0h | Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1. |
23-16 | SRCTAG_LO | R/W | 0h | Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1. |
15-8 | DSTTAG_HI | R/W | 0h | Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1. |
7-0 | DSTTAG_LO | R/W | 0h | Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1. |
UDMA_RFC_j is shown in Figure 10-99 and described in Table 10-299.
Return to Summary Table.
The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this register are as follows:
Offset = 8h + (j * 40h); where
j = 0h to 95h for NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
j = 0h to 5Fh for MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 0008h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 0008h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SRCTAG_HI_SEL | RESERVED | SRCTAG_LO_SEL | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DSTTAG_HI_SEL | RESERVED | DSTTAG_LO_SEL | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SIZE_THRESH_EN | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | SRCTAG_HI_SEL | R/W | 0h | Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in rx_src_tag_hi 2 = overwrite with flow_id[7:0] from back end application 3 = RESERVED 4 = overwrite with src_tag[7:0] from back end application 5-7 = RESERVED |
27 | RESERVED | R/W | X | |
26-24 | SRCTAG_LO_SEL | R/W | 0h | Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in rx_src_tag_lo 2 = overwrite with flow_id[7:0] from back end application 3 = RESERVED 4 = overwrite with src_tag[7:0] from back end application 5-7 = RESERVED |
23 | RESERVED | R/W | X | |
22-20 | DSTTAG_HI_SEL | R/W | 0h | Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in rx_dest_tag_hi 2 = overwrite with flow_id[7:0] from back end application 3 = RESERVED 4 = overwrite with dest_tag[7:0] from back end application 5 = overwrite with dest_tag[15:8] from back end application 6-7 = RESERVED |
19 | RESERVED | R/W | X | |
18-16 | DSTTAG_LO_SEL | R/W | 0h | Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in rx_dest_tag_lo 2 = overwrite with flow_id[7:0] from back end application 3 = RESERVED 4 = overwrite with dest_tag[7:0] from back end application 5 = overwrite with dest_tag[15:8] from back end application 6-7 = RESERVED |
15-3 | RESERVED | R/W | X | |
2-0 | SIZE_THRESH_EN | R/W | 0h | Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the SOP buffer from. Each bit in this field corresponds to 1 of the 3 potential size thresholds that can be compared against. Bit 0 corresponds to rx_size_thresh0 and bit 2 corresponds to rx_size_thresh2. The bits in this field is encoded as follows: 0 = Do not use the threshold. 1 = Use the thresholds to select between the 4 different potential SOP FDQs. If none of the thresholds are enabled, the DMA controller in the port will allocate the SOP buffer from the queue specified by the rx_fdq0_sz0_qnum field. Support for packet size based FDQ selection is OPTIONAL. If the port does not implement this feature, the bits of this field will be hardcoded to 0 and will not be writable by the host. |
UDMA_RFD_j is shown in Figure 10-100 and described in Table 10-301.
Return to Summary Table.
The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this register are as follows:
Offset = Ch + (j * 40h); where
j = 0h to 95h for NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
j = 0h to 5Fh for MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 000Ch + formula |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 000Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDQ0_SZ0_QNUM | FDQ1_QNUM | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FDQ0_SZ0_QNUM | R/W | 0h | Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. |
15-0 | FDQ1_QNUM | R/W | 0h | Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet |
UDMA_RFE_j is shown in Figure 10-101 and described in Table 10-303.
Return to Summary Table.
The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this register are as follows:
Offset = 10h + (j * 40h); where
j = 0h to 95h for NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
j = 0h to 5Fh for MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 0010h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 0010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDQ2_QNUM | FDQ3_QNUM | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FDQ2_QNUM | R/W | 0h | Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet |
15-0 | FDQ3_QNUM | R/W | 0h | Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet |
UDMA_RFF_j is shown in Figure 10-102 and described in Table 10-305.
Return to Summary Table.
The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is OPTIONAL. The fields in this register are as follows:
Offset = 14h + (j * 40h); where
j = 0h to 95h for NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
j = 0h to 5Fh for MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 0014h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 0014h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIZE_THRESH0 | SIZE_THRESH1 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SIZE_THRESH0 | R/W | 0h | Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the value given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by the rx_fdq0_sz0_qnum field. This field is OPTIONAL. |
15-0 | SIZE_THRESH1 | R/W | 0h | Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the rx_size_thresh0 but is less than or equal to the value given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by the rx_fdq0_sz1_qnum field. If enabled, this value must be greater than the value given in the rx_size_thresh0 field. This field is optional. |
UDMA_RFG_j is shown in Figure 10-103 and described in Table 10-307.
Return to Summary Table.
The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is OPTIONAL. The fields in this register are as follows:
Offset = 18h + (j * 40h); where
j = 0h to 95h for NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
j = 0h to 5Fh for MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 0018h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 0018h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIZE_THRESH2 | FDQ0_SZ1_QNUM | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SIZE_THRESH2 | R/W | 0h | Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the value given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by the rx_fdq0_sz2_qnum field. If enabled, this value must be greater than the value given in the rx_size_thresh1 field. This field is optional. |
15-0 | FDQ0_SZ1_QNUM | R/W | 0h | Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional. |
UDMA_RFH_j is shown in Figure 10-104 and described in Table 10-309.
Return to Summary Table.
The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is OPTIONAL. The fields in this register are as follows:
Offset = 1Ch + (j * 40h); where
j = 0h to 95h for NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
j = 0h to 5Fh for MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 30D0 001Ch + formula |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW | 2840 001Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDQ0_SZ2_QNUM | FDQ0_SZ3_QNUM | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FDQ0_SZ2_QNUM | R/W | 0h | Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional. |
15-0 | FDQ0_SZ3_QNUM | R/W | 0h | Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional. |