Table 8-3198 lists the DDRSS0_ECC_AGGR_CTL registers. All register offset addresses not listed in Table 8-3198 should be considered as reserved locations and the register contents should not be modified.
Table 8-3197 DDRSS0_ECC_AGGR_CTL Instances Table 8-3198 DDRSS0_ECC_AGGR_CTL Registers 2.5.5.1 DDRSS_REV Register (Offset = 0h) [reset = 66A02A01h]
DDRSS_REV is shown in Figure 8-1593 and described in Table 8-3200.
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Revision parameters
Table 8-3199 DDRSS_REV InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0000h |
Figure 8-1593 DDRSS_REV Register LEGEND: R = Read Only; -n = value after reset |
Table 8-3200 DDRSS_REV Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 5h | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 1h | Minor version |
2.5.5.2 DDRSS_VECTOR Register (Offset = 8h) [reset = X]
DDRSS_VECTOR is shown in Figure 8-1594 and described in Table 8-3202.
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ECC Vector Register
Table 8-3201 DDRSS_VECTOR InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0008h |
Figure 8-1594 DDRSS_VECTOR Register LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3202 DDRSS_VECTOR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-25 | RESERVED | R | X | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R | X | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
2.5.5.3 DDRSS_STAT Register (Offset = Ch) [reset = X]
DDRSS_STAT is shown in Figure 8-1595 and described in Table 8-3204.
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Misc Status
Table 8-3203 DDRSS_STAT InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 000Ch |
Figure 8-1595 DDRSS_STAT Register LEGEND: R = Read Only; -n = value after reset |
Table 8-3204 DDRSS_STAT Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-11 | RESERVED | R | X | Reserved |
10-0 | NUM_RAMS | R | 5h | Indicates the number of RAMS serviced by the ECC aggregator |
2.5.5.4 DDRSS_RESERVED_SVBUS_y Register (Offset = 10h + formula) [reset = 0h]
DDRSS_RESERVED_SVBUS_y is shown in Figure 8-1596 and described in Table 8-3206.
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Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.
Offset = 10h + (y * 4h); where y = 0h to 7h
Table 8-3205 DDRSS_RESERVED_SVBUS_y InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0010h + formula |
Figure 8-1596 DDRSS_RESERVED_SVBUS_y Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 8-3206 DDRSS_RESERVED_SVBUS_y Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | DATA | R/W | 0h | Serial VBUS register data |
2.5.5.5 DDRSS_SEC_EOI_REG Register (Offset = 3Ch) [reset = X]
DDRSS_SEC_EOI_REG is shown in Figure 8-1597 and described in Table 8-3208.
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EOI Register
Table 8-3207 DDRSS_SEC_EOI_REG InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 003Ch |
Figure 8-1597 DDRSS_SEC_EOI_REG Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3208 DDRSS_SEC_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R | X | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI Register |
2.5.5.6 DDRSS_SEC_STATUS_REG0 Register (Offset = 40h) [reset = X]
DDRSS_SEC_STATUS_REG0 is shown in Figure 8-1598 and described in Table 8-3210.
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Interrupt Status Register 0
Table 8-3209 DDRSS_SEC_STATUS_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0040h |
Figure 8-1598 DDRSS_SEC_STATUS_REG0 Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3210 DDRSS_SEC_STATUS_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-5 | RESERVED | R | X | Reserved |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend |
3 | V2A_EDC_CTRL_PEND | R/W1S | 0h | Interrupt Pending Status for v2a_edc_ctrl_pend |
2 | ASAFE_2_SI_PEND | R/W1S | 0h | Interrupt Pending Status for asafe_2_si_pend |
1 | ASAFE_1_SI_PEND | R/W1S | 0h | Interrupt Pending Status for asafe_1_si_pend |
0 | ASAFE_0_SI_PEND | R/W1S | 0h | Interrupt Pending Status for asafe_0_si_pend |
2.5.5.7 DDRSS_SEC_ENABLE_SET_REG0 Register (Offset = 80h) [reset = X]
DDRSS_SEC_ENABLE_SET_REG0 is shown in Figure 8-1599 and described in Table 8-3212.
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Interrupt Enable Set Register 0
Table 8-3211 DDRSS_SEC_ENABLE_SET_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0080h |
Figure 8-1599 DDRSS_SEC_ENABLE_SET_REG0 Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3212 DDRSS_SEC_ENABLE_SET_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-5 | RESERVED | R | X | Reserved |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend |
3 | V2A_EDC_CTRL_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for v2a_edc_ctrl_pend |
2 | ASAFE_2_SI_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for asafe_2_si_pend |
1 | ASAFE_1_SI_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for asafe_1_si_pend |
0 | ASAFE_0_SI_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for asafe_0_si_pend |
2.5.5.8 DDRSS_SEC_ENABLE_CLR_REG0 Register (Offset = C0h) [reset = X]
DDRSS_SEC_ENABLE_CLR_REG0 is shown in Figure 8-1600 and described in Table 8-3214.
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Interrupt Enable Clear Register 0
Table 8-3213 DDRSS_SEC_ENABLE_CLR_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 00C0h |
Figure 8-1600 DDRSS_SEC_ENABLE_CLR_REG0 Register LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 8-3214 DDRSS_SEC_ENABLE_CLR_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-5 | RESERVED | R | X | Reserved |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend |
3 | V2A_EDC_CTRL_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for v2a_edc_ctrl_pend |
2 | ASAFE_2_SI_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for asafe_2_si_pend |
1 | ASAFE_1_SI_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for asafe_1_si_pend |
0 | ASAFE_0_SI_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for asafe_0_si_pend |
2.5.5.9 DDRSS_DED_EOI_REG Register (Offset = 13Ch) [reset = X]
DDRSS_DED_EOI_REG is shown in Figure 8-1601 and described in Table 8-3216.
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EOI Register
Table 8-3215 DDRSS_DED_EOI_REG InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 013Ch |
Figure 8-1601 DDRSS_DED_EOI_REG Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3216 DDRSS_DED_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R | X | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI Register |
2.5.5.10 DDRSS_DED_STATUS_REG0 Register (Offset = 140h) [reset = X]
DDRSS_DED_STATUS_REG0 is shown in Figure 8-1602 and described in Table 8-3218.
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Interrupt Status Register 0
Table 8-3217 DDRSS_DED_STATUS_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0140h |
Figure 8-1602 DDRSS_DED_STATUS_REG0 Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3218 DDRSS_DED_STATUS_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-5 | RESERVED | R | X | Reserved |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend |
3 | V2A_EDC_CTRL_PEND | R/W1S | 0h | Interrupt Pending Status for v2a_edc_ctrl_pend |
2 | ASAFE_2_SI_PEND | R/W1S | 0h | Interrupt Pending Status for asafe_2_si_pend |
1 | ASAFE_1_SI_PEND | R/W1S | 0h | Interrupt Pending Status for asafe_1_si_pend |
0 | ASAFE_0_SI_PEND | R/W1S | 0h | Interrupt Pending Status for asafe_0_si_pend |
2.5.5.11 DDRSS_DED_ENABLE_SET_REG0 Register (Offset = 180h) [reset = X]
DDRSS_DED_ENABLE_SET_REG0 is shown in Figure 8-1603 and described in Table 8-3220.
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Interrupt Enable Set Register 0
Table 8-3219 DDRSS_DED_ENABLE_SET_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0180h |
Figure 8-1603 DDRSS_DED_ENABLE_SET_REG0 Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3220 DDRSS_DED_ENABLE_SET_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-5 | RESERVED | R | X | Reserved |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend |
3 | V2A_EDC_CTRL_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for v2a_edc_ctrl_pend |
2 | ASAFE_2_SI_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for asafe_2_si_pend |
1 | ASAFE_1_SI_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for asafe_1_si_pend |
0 | ASAFE_0_SI_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for asafe_0_si_pend |
2.5.5.12 DDRSS_DED_ENABLE_CLR_REG0 Register (Offset = 1C0h) [reset = X]
DDRSS_DED_ENABLE_CLR_REG0 is shown in Figure 8-1604 and described in Table 8-3222.
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Interrupt Enable Clear Register 0
Table 8-3221 DDRSS_DED_ENABLE_CLR_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 01C0h |
Figure 8-1604 DDRSS_DED_ENABLE_CLR_REG0 Register LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 8-3222 DDRSS_DED_ENABLE_CLR_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-5 | RESERVED | R | X | Reserved |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend |
3 | V2A_EDC_CTRL_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for v2a_edc_ctrl_pend |
2 | ASAFE_2_SI_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for asafe_2_si_pend |
1 | ASAFE_1_SI_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for asafe_1_si_pend |
0 | ASAFE_0_SI_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for asafe_0_si_pend |
2.5.5.13 DDRSS_AGGR_ENABLE_SET Register (Offset = 200h) [reset = X]
DDRSS_AGGR_ENABLE_SET is shown in Figure 8-1605 and described in Table 8-3224.
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AGGR interrupt enable set Register
Table 8-3223 DDRSS_AGGR_ENABLE_SET InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0200h |
Figure 8-1605 DDRSS_AGGR_ENABLE_SET Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3224 DDRSS_AGGR_ENABLE_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R | X | Reserved |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
2.5.5.14 DDRSS_AGGR_ENABLE_CLR Register (Offset = 204h) [reset = X]
DDRSS_AGGR_ENABLE_CLR is shown in Figure 8-1606 and described in Table 8-3226.
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AGGR interrupt enable clear Register
Table 8-3225 DDRSS_AGGR_ENABLE_CLR InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0204h |
Figure 8-1606 DDRSS_AGGR_ENABLE_CLR Register LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 8-3226 DDRSS_AGGR_ENABLE_CLR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R | X | Reserved |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
2.5.5.15 DDRSS_AGGR_STATUS_SET Register (Offset = 208h) [reset = X]
DDRSS_AGGR_STATUS_SET is shown in Figure 8-1607 and described in Table 8-3228.
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AGGR interrupt status set Register
Table 8-3227 DDRSS_AGGR_STATUS_SET InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 0208h |
Figure 8-1607 DDRSS_AGGR_STATUS_SET Register LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Table 8-3228 DDRSS_AGGR_STATUS_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-4 | RESERVED | R | X | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | interrupt status set for parity errors |
2.5.5.16 DDRSS_AGGR_STATUS_CLR Register (Offset = 20Ch) [reset = X]
DDRSS_AGGR_STATUS_CLR is shown in Figure 8-1608 and described in Table 8-3230.
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AGGR interrupt status clear Register
Table 8-3229 DDRSS_AGGR_STATUS_CLR InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CTL | 4D200B 020Ch |
Figure 8-1608 DDRSS_AGGR_STATUS_CLR Register LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Table 8-3230 DDRSS_AGGR_STATUS_CLR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-4 | RESERVED | R | X | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | interrupt status clear for parity errors |