SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-414 lists the memory-mapped registers for the NAVSS0_UDMASS_RINGACC0_CFG. All register offset addresses not listed in Table 10-414 should be considered as reserved locations and the register contents should not be modified.
The Ring Accelerator Ring Control /Status Registers region is accessed by setting the cfg_rsel signal to 1 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG | 3108 0000h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG | 2844 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_RINGACC0_CFG Physical Address | MCU_NAVSS0_UDMASS_RINGACC0_CFG Physical Address |
---|---|---|---|---|
40h + formula | RINGACC_BA_LO_J | Ring Base Address Lo Register | 3108 0040h + formula | 2844 0040h + formula |
44h + formula | RINGACC_BA_HI_j | Ring Base Address Hi Register | 3108 0044h + formula | 2844 0044h + formula |
48h + formula | RINGACC_SIZE_j | Ring Size Register | 3108 0048h + formula | 2844 0048h + formula |
4Ch + formula | RINGACC_EVENT_j | Ring Event Register | 3108 004Ch + formula | 2844 004Ch + formula |
50h + formula | RINGACC_ORDERID_j | Ring OrderID Register | 3108 0050h + formula | 2844 0050h + formula |
RINGACC_BA_LO_J is shown in Figure 10-152 and described in Table 10-416.
Return to Summary Table.
The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring, or to double the element size of the ring if the qmode is CREDENTIALS or QM modes. A write to this register will reset the associated ring to clear the occupancies and reset the pointers.
Offset = 40h + (j * 100h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG | 3108 0040h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG | 2844 0040h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_LO | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR_LO | R/W | 0h | Tx Ring base address (LSBs) |
RINGACC_BA_HI_j is shown in Figure 10-153 and described in Table 10-418.
Return to Summary Table.
The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring, or to double the element size of the ring if the qmode is CREDENTIALS or QM modes. A write to this register will reset the associated ring to clear the occupancies and reset the pointers.
Offset = 44h + (j * 100h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG | 3108 0044h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG | 2844 0044h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR_HI | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | ADDR_HI | R/W | 0h | Tx Ring base address (MSBs) |
RINGACC_SIZE_j is shown in Figure 10-154 and described in Table 10-420.
Return to Summary Table.
The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and reset the pointers.
Offset = 48h + (j * 100h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG | 3108 0048h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG | 2844 0048h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
QMODE | RESERVED | ELSIZE | RESERVED | ELCNT | |||||||||||
R/W-0h | R/W-X | R/W-0h | R/W-X | R/W-0h | |||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ELCNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | QMODE | R/W | 0h | Defines the mode for this ring or queue. 0h = exposed ring mode for SW direct access 1h = messaging mode when all operations are through bus accesses, allowing multiple producers or consumers. 2h = credentials mode is message mode plus stores credentials with each message, requiring the ring size to be doubled to fit the credentials along with the same number of elements when using the first 2 modes. Any exposed memory should be protected by a firewall from unwanted access. 3h = QM mode where the elements include additional fields that the QM supported above messaging credentials mode. Must be used with 8 byte element size only. NOT SUPPORTED. |
29-27 | RESERVED | R/W | X | |
26-24 | ELSIZE | R/W | 0h | Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED |
23-20 | RESERVED | R/W | X | |
19-0 | ELCNT | R/W | 0h | Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number. |
RINGACC_EVENT_j is shown in Figure 10-155 and described in Table 10-422.
Return to Summary Table.
The Ring Event Register contains the event number for the ring for when it is active or empty.
Offset = 4Ch + (j * 100h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG | 3108 004Ch + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG | 2844 004Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVENT | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | EVENT | R/W | FFFFh | Defines the event for this ring or queue. |
RINGACC_ORDERID_j is shown in Figure 10-156 and described in Table 10-424.
Return to Summary Table.
The Ring OrderID Register contains the bus orderid value for the ring memory access.
Offset = 50h + (j * 100h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG | 3108 0050h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG | 2844 0050h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REPLACE | ORDERID | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | REPLACE | R/W | 0h | Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source transaction for the destination transaction. 1 = use the orderid MMR field value for the destination transaction. |
3-0 | ORDERID | R/W | 0h | Defines the bus orderid value for this ring or queue. |