SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
SerDeses provide PHY functions for the following high-speed interfaces:
Table 12-3873 describes the interface combinations supported by SERDES0.
Interface Alias | CTRLMMR_SERDES0_LN0_CTRL [1:0] | CTRLMMR_SERDES0_LN1_CTRL [1:0] | CTRLMMR_SERDES0_LN2_CTRL [1:0] | CTRLMMR_SERDES0_LN3_CTRL [1:0] | ||||
---|---|---|---|---|---|---|---|---|
LANE_FUNC_SEL | Interface on Lane 0 | LANE_FUNC_SEL | Interface on Lane 1 | LANE_FUNC_SEL | Interface on Lane 2 | LANE_FUNC_SEL | Interface on Lane 3 | |
IP1 | 0x0 | SGMII Lane 3 | 0x0 | SGMII Lane 4 | 0x0 | SGMII Lane 1 | 0x0 | SGMII Lane 2 |
IP2 | 0x1 | PCIe Lane 0 | 0x1 | PCIe Lane 1 | 0x1 | PCIe Lane 2 | 0x1 | PCIe Lane 3 |
IP3 | 0x2 | -(1) | 0x2 | USB0 | 0x2 | -(1) | 0x2 | USB0 |
IP4 | 0x3 | - | 0x3 | - | 0x3 | - | 0x3 | - |
As seen in Table 12-3873, USB0 can be routed to two different lanes. To avoid routing to two lanes at the same time, an additional muxing exists.
Table 12-3874 describes the additional muxing for USB0 to lane 1 or to lane 3.
Settings in Table 12-3874 must be aligned with the settings made in Table 12-3873.
CTRLMMR_USB0_CTRL | |
---|---|
[27] SERDES_SEL | Lane Selected |
0 | Lane 1 (Lane 0 for Type-C) |
1 | Lane 3 (Lane 2 for Type-C) |