SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3883 lists the memory-mapped registers for the FSS (MCU_FSS0). All register offset addresses not listed in Table 12-3883 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_FSS0_CFG | 4700 0000h |
Offset | Acronym | Register Name | MCU_FSS0_CFG Physical Address |
---|---|---|---|
0h | MCU_FSS0_REVISION | Revision Register | 4700 0000h |
4h | MCU_FSS0_SYSCONFIG | Configuration Register | 4700 0004h |
10h | MCU_FSS0_EOI | End Of Interrupt (EOI) MISC Register | 4700 0010h |
14h | MCU_FSS0_STATUS_RAW | Interrupt Source Set Register | 4700 0014h |
18h | MCU_FSS0_STATUS | Interrupt Source Clear Register | 4700 0018h |
1Ch | MCU_FSS0_ENABLE_SET | Interrupt Source Enable Register | 4700 001Ch |
20h | MCU_FSS0_ENABLE_CLR | Interrupt Source Disable Register | 4700 0020h |
30h + formula | MCU_FSS0_ECC_RGSTRT_j | ECC Region Start Register | 4700 0030h to 4700 0054h |
34h + formula | MCU_FSS0_ECC_RGSIZ_j | ECC Region Size Register | 4700 0034h to 4700 0058h |
70h | MCU_FSS0_ECC_BLOCK_ADR | ECC Error Block Address Register | 4700 0070h |
74h | MCU_FSS0_ECC_TYPE | ECC Error Type Register | 4700 0074h |
78h | MCU_FSS0_WRT_TYPE | Error Write Type Register | 4700 0078h |
MCU_FSS0_REVISION is shown in Figure 12-1960 and described in Table 12-3885.
Return to Summary Table.
Revision Register
Used by software to track features, bugs, and compatibility.
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R-6850h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1h | R-1h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 6850h | Module ID |
15-11 | REVRTL | R | 1h | RTL Revision |
10-8 | REVMAJ | R | 1h | Major Revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | REVMIN | R | 1h | Minor Revision |
MCU_FSS0_SYSCONFIG is shown in Figure 12-1961 and described in Table 12-3887.
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Configuration Register
Controls various parameters of the cotroller state.
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OSPI_32B_DISABLE_MODE | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DISXIP | OSPI_DDR_DISABLE_MODE | RESERVED | ECC_DISABLE_ADR | RESERVED | HB_OSPI | ECC_EN | |
R/W-0h | R/W-0h | R-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | OSPI_32B_DISABLE_MODE | R/W | 0h | 0h = OSPI 32-bit mode enabled 1h = OSPI 32-bit mode disabled |
7 | DISXIP | R/W | 0h | 0h = XIP prefetch enabled 1h = XIP prefetch disabled |
6 | OSPI_DDR_DISABLE_MODE | R/W | 0h | 0h = OSPI DDR mode enabled 1h = OSPI DDR mode disabled |
5-4 | RESERVED | R | 0h | Reserved |
3 | ECC_DISABLE_ADR | R/W | 0h | Block Address ECC Calculation 0h = Block address within ECC calculation 1h = Block address not within ECC calculation |
2 | RESERVED | R | 0h | Reserved |
1 | HB_OSPI | R/W | 0h | Path Select 0h = Select OSPI path 1h = Select HyperBus interface path |
0 | ECC_EN | R/W | 0h | ECC Enable 0h = ECC disabled 1h = ECC enabled |
MCU_FSS0_EOI is shown in Figure 12-1962 and described in Table 12-3889.
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End Of Interrupt (EOI) MISC Register
The End Of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to it for misc interrupt sources. An EOI write signal will be generated and another interrupt will be triggered if interrupt sources remain. This register will be reset one cycle after it has been written to.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_VECTOR | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_VECTOR | R/W | 0h | EOI Vector Write with bit position of targeted interrupt (example: external FSS ECC is bit 0). Upon write, level interrupt will clear and if un-serviced will issue another pulse interrupt. |
MCU_FSS0_STATUS_RAW is shown in Figure 12-1963 and described in Table 12-3891.
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Interrupt Source Set Register
The Interrupt Source Set Register allows the interrupt sources to be manually set when writing 1h to a specific bit.
Write 0h = No action
Write 1h = Set event
Read 0h = No event pending
Read 1h = Event pending
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECC_WRITE_NONALIGN | ECC_ERROR_2BIT | ECC_ERROR_1BIT | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | ECC_WRITE_NONALIGN | R/W1S | 0h | ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte. |
1 | ECC_ERROR_2BIT | R/W1S | 0h | ECC Error on 2 Bits Not correctable. |
0 | ECC_ERROR_1BIT | R/W1S | 0h | ECC Error on 1 Bit Correctable. |
MCU_FSS0_STATUS is shown in Figure 12-1964 and described in Table 12-3893.
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Interrupt Source Clear Register
The Interrupt Source Clear Register allows the interrupt sources to be manually cleared when writing 1h to a specific bit.
Write 0h = No action
Write 1h = Clear event
Read 0h = No event pending
Read 1h = Event pending
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECC_WRITE_NONALIGN | ECC_ERROR_2BIT | ECC_ERROR_1BIT | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | ECC_WRITE_NONALIGN | R/W1C | 0h | ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte. |
1 | ECC_ERROR_2BIT | R/W1C | 0h | ECC Error on 2 Bits Not correctable. |
0 | ECC_ERROR_1BIT | R/W1C | 0h | ECC Error on 1 Bit Correctable. |
MCU_FSS0_ENABLE_SET is shown in Figure 12-1965 and described in Table 12-3895.
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Interrupt Source Enable Register
The Interrupt Source Enable Register allows the interrupt sources to be manually enabled when writing 1h to a specific bit.
Write 0h = No action
Write 1h = Enable event
Read 0h = Event is disabled
Read 1h = Event is enabled
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECC_WRITE_NONALIGN | ECC_ERROR_2BIT | ECC_ERROR_1BIT | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | ECC_WRITE_NONALIGN | R/W1S | 0h | ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte. |
1 | ECC_ERROR_2BIT | R/W1S | 0h | ECC Error on 2 Bits Not correctable. |
0 | ECC_ERROR_1BIT | R/W1S | 0h | ECC Error on 1 Bit Correctable. |
MCU_FSS0_ENABLE_CLR is shown in Figure 12-1966 and described in Table 12-3897.
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Interrupt Source Disable Register
The Interrupt Source Disable Register allows the interrupt sources to be manually disabled when writing 1h to a specific bit.
Write 0h = No action
Write 1h = Disable event
Read 0h = Event is disabled
Read 1h = Event is enabled
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECC_WRITE_NONALIGN | ECC_ERROR_2BIT | ECC_ERROR_1BIT | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | ECC_WRITE_NONALIGN | R/W1C | 0h | ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte. |
1 | ECC_ERROR_2BIT | R/W1C | 0h | ECC Error on 2 Bits Not correctable. |
0 | ECC_ERROR_1BIT | R/W1C | 0h | ECC Error on 1 Bit Correctable. |
MCU_FSS0_ECC_RGSTRT_j is shown in Figure 12-1967 and described in Table 12-3899.
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ECC Region Start Register
The ECC Region Start Register defines the start of the ECC region in 4 KB steps.
Offset = 30h + (j × 8h); where j = 0h to 3h
MCU_FSS0_ECC_RGSTRT_0: 4700 0030h
MCU_FSS0_ECC_RGSTRT_1: 4700 0038h
MCU_FSS0_ECC_RGSTRT_2: 4700 0046h
MCU_FSS0_ECC_RGSTRT_3: 4700 0054h
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0030h to 4700 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | R_START | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-0 | R_START | R/W | 0h | ECC Region Start Address This bit field defines the start of the ECC region in 4 KB steps. Address start = {start[19:0], 000h} 0h = start is 0000 0000h 1h = start is 0000 1000h Ah = start is 0000 A000h Note: the offset + size should be <= 4 GB, wrap around is not supported. |
MCU_FSS0_ECC_RGSIZ_j is shown in Figure 12-1968 and described in Table 12-3901.
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ECC Region Size Register
The ECC Region Size Register defines the size of the ECC region in 4 KB steps.
Offset = 34h + (j × 8h); where j = 0h to 3h
MCU_FSS0_ECC_RGSIZ_0: 4700 0034h
MCU_FSS0_ECC_RGSIZ_1: 4700 0042h
MCU_FSS0_ECC_RGSIZ_2: 4700 0050h
MCU_FSS0_ECC_RGSIZ_3: 4700 0058h
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0034h to 4700 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | R_SIZE | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-0 | R_SIZE | R/W | 0h | ECC Region Size This bit field defines the size of the ECC region in 4 KB steps. 0h = size is zero and disabled 1h = size is 4 KB Ah = size is 40 KB F FFFFh = size is 4 GB Note: offset + size should be <= 4 GB, wrap around is not supported. |
MCU_FSS0_ECC_BLOCK_ADR is shown in Figure 12-1969 and described in Table 12-3903.
ECC Error Block Address Register
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The ECC Error Block Address Register holds the current top of stack ECC error block address, this is only valid when the MCU_FSS0_ECC_TYPE[31] ECC_ERR_VALID bit is set.
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_ERROR_BLOCK_ADDR | RESERVED | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | ECC_ERROR_BLOCK_ADDR | R | 0h | ECC Error Block Address ECC 32-byte aligned block address |
4-0 | RESERVED | R | 0h | Reserved |
MCU_FSS0_ECC_TYPE is shown in Figure 12-1970 and described in Table 12-3905.
ECC Error Type Register
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The ECC Error Type Register holds the current top of stack ECC error info, this is only valid when the MCU_FSS0_ECC_TYPE[31] ECC_ERR_VALID bit is set.
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ECC_ERR_VALID | RESERVED | ||||||
R/W1C-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECC_ERR_ADR | ECC_ERR_MAC | ECC_ERR_DA1 | ECC_ERR_DA0 | ECC_ERR_DED | ECC_ERR_SEC | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ECC_ERR_VALID | R/W1C | 0h | ECC Error Valid When set indicates that there is valid ECC error information available. Writing a 1h to this register will pop the top of the stack. |
30-6 | RESERVED | R | 0h | Reserved |
5 | ECC_ERR_ADR | R | 0h | ECC Error Address When set indicates that there was a single error detected within the address field. |
4 | ECC_ERR_MAC | R | 0h | ECC Error MAC When set indicates that there was a single error detected within the MAC field. |
3 | ECC_ERR_DA1 | R | 0h | ECC Error High Data Word When set indicates that there was a single error detected within the High Data word. |
2 | ECC_ERR_DA0 | R | 0h | ECC Error Low Data Word When set indicates that there was a single error detected within the Low Data word. |
1 | ECC_ERR_DED | R | 0h | ECC Error (DED) When set indicates that there was a double error detected for the block. |
0 | ECC_ERR_SEC | R | 0h | ECC Error (SEC) When set indicates that there was a single error detected for the block. |
MCU_FSS0_WRT_TYPE is shown in Figure 12-1971 and described in Table 12-3907.
Return to Summary Table.
Error Write Type Register
The Error Write Type Register holds the current top of stack write error info, this is only valid when the MCU_FSS0_WRT_TYPE[31] WRT_ERR_VALID bit is set.
Instance | Physical Address |
---|---|
MCU_FSS0_CFG | 4700 0078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WRT_ERR_VALID | RESERVED | ||||||
R/W1C-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WRT_ERR_BEN | WRT_ERR_ADR | WRT_ERR_ROUTEID | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRT_ERR_ROUTEID | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | WRT_ERR_VALID | R/W1C | 0h | Write Error Valid When set indicates that there is valid write error information available. Writing a 1h to this register will pop the top of the stack. |
30-14 | RESERVED | R | 0h | Reserved |
13 | WRT_ERR_BEN | R | 0h | Write Error Non-Contiguous Byte Enables When set indicates that there was a write error due to a non-contiguous byte enables. |
12 | WRT_ERR_ADR | R | 0h | Write Error Address When set indicates that there was a write error due to a non-aligned address. |
11-0 | WRT_ERR_ROUTEID | R | 0h | Write Error Route ID Indicates the Route ID for the Master that caused the write error. |