SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The device supports one instance of a Power on Reset (POR) module - WKUP_POR0. WKUP_POR0 is located in WKUP domain. Figure 5-648 shows the integration of WKUP_POR0.
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
WKUP_POR0 | CLK1MEG | CLK_1P8V_1P56M | WKUP_RC_OSC_12M | 1.56-MHz clock from RCOSC |
CLK40K | CLK_1P8V_97P65K | WKUP_RC_OSC_12M | 97.65-kHz clock from RCOSC |
POK Instance | Connected to PRG | Voltage Monitored | Via External Pin | OV/UV |
---|---|---|---|---|
POR_POKLVB_VDD_MCU_UV | PRG_PP_POR | VDD_MCU | No | UV |
POR_POKHV_VDDA_WKUP_POR_UV | PRG_PP_POR | VDDA_POR_WKUP (1.8V) | No | UV |
POR_POKLVA_VDDA_WKUP_POR_OV | PRG_PP_POR | VDDA_POR_WKUP (1.8V) | No | OV |