SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The TS_COMP output is asserted for CPTS_TS_COMP_LEN_REG[23-0] RCLK periods when the TIME_STAMP[31-0] value compares with the CPTS_TS_COMP_VAL_REG[31-0] and the length value is non-zero. The TS_COMP rising edge occurs three RCLK periods after the values compare. A timestamp compare event is pushed into the event FIFO when TS_COMP is asserted. The polarity of the TS_COMP output is determined by the CPTS_CONTROL_REG[2] TS_POLARITY bit. The output is asserted low when the polarity bit is 0.