Table 12-1757 lists the memory-mapped registers for the MCU_CPSW0_CPINT. All register offset addresses not listed in Table 12-1757 should be considered as reserved locations and the register contents should not be modified.
Table 12-1353 MCU_CPSW0_CPINT Instances Table 12-1354 MCU_CPSW0_CPINT Registers 1.6.6.1 CPSW_INT_REVISION Register (Offset = 1000h) [reset = 6690A200h]
CPSW_INT_REVISION is shown in Figure 12-712 and described in Table 12-1356.
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Revision Register
Table 12-1355 CPSW_INT_REVISION InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_CPINT | 4600 1000h |
Figure 12-712 CPSW_INT_REVISION Register LEGEND: R = Read Only; -n = value after reset |
Table 12-1356 CPSW_INT_REVISION Register Field Descriptions 1.6.6.2 CPSW_INT_EOI_REG Register (Offset = 1010h) [reset = X]
CPSW_INT_EOI_REG is shown in Figure 12-713 and described in Table 12-1358.
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End of Interrupt Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Table 12-1357 CPSW_INT_EOI_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_CPINT | 4600 1010h |
Figure 12-713 CPSW_INT_EOI_REG Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1358 CPSW_INT_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-8 | RESERVED | R/W | X | |
7-0 | EOI_VECTOR | R/W | 0h | End of Interrupt Vector |
1.6.6.3 CPSW_INT_INTR_VECTOR_REG Register (Offset = 1014h) [reset = 0h]
CPSW_INT_INTR_VECTOR_REG is shown in Figure 12-714 and described in Table 12-1360.
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Interrupt Vector Register
Table 12-1359 CPSW_INT_INTR_VECTOR_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_CPINT | 4600 1014h |
Figure 12-714 CPSW_INT_INTR_VECTOR_REG Register LEGEND: R = Read Only; -n = value after reset |
Table 12-1360 CPSW_INT_INTR_VECTOR_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | INTR_VECTOR | R | 0h | Interrupt Vector Register |
1.6.6.4 CPSW_INT_ENABLE_REG_OUT_PULSE_0 Register (Offset = 1100h) [reset = X]
CPSW_INT_ENABLE_REG_OUT_PULSE_0 is shown in Figure 12-715 and described in Table 12-1362.
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Enable Register 0
Table 12-1361 CPSW_INT_ENABLE_REG_OUT_PULSE_0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_CPINT | 4600 1100h |
Figure 12-715 CPSW_INT_ENABLE_REG_OUT_PULSE_0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1362 CPSW_INT_ENABLE_REG_OUT_PULSE_0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-3 | RESERVED | R/W | X | |
2 | ENABLE_OUT_PULSE_EN_STAT_PENDA | R/W1S | 0h | Enable Set for out_pulse_en_stat_penda |
1 | ENABLE_OUT_PULSE_EN_MDIO_PENDA | R/W1S | 0h | Enable Set for out_pulse_en_mdio_penda |
0 | ENABLE_OUT_PULSE_EN_EVNT_PENDA | R/W1S | 0h | Enable Set for out_pulse_en_evnt_penda |
1.6.6.5 CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0 Register (Offset = 1300h) [reset = X]
CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0 is shown in Figure 12-716 and described in Table 12-1364.
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Enable Clear Register 0
Table 12-1363 CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_CPINT | 4600 1300h |
Figure 12-716 CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0 Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 12-1364 CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-3 | RESERVED | R/W | X | |
2 | ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR | R/W1C | 0h | Enable Clear for out_pulse_en_stat_penda |
1 | ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR | R/W1C | 0h | Enable Clear for out_pulse_en_mdio_penda |
0 | ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR | R/W1C | 0h | Enable Clear for out_pulse_en_evnt_penda |
1.6.6.6 CPSW_INT_STATUS_REG_OUT_PULSE_0 Register (Offset = 1500h) [reset = X]
CPSW_INT_STATUS_REG_OUT_PULSE_0 is shown in Figure 12-717 and described in Table 12-1366.
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Status Register 0
Table 12-1365 CPSW_INT_STATUS_REG_OUT_PULSE_0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_CPINT | 4600 1500h |
Figure 12-717 CPSW_INT_STATUS_REG_OUT_PULSE_0 Register LEGEND: R = Read Only; -n = value after reset |
Table 12-1366 CPSW_INT_STATUS_REG_OUT_PULSE_0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-3 | RESERVED | R | X | |
2 | STATUS_OUT_PULSE_STAT_PENDA | R | 0h | Status for out_pulse_en_stat_penda |
1 | STATUS_OUT_PULSE_MDIO_PENDA | R | 0h | Status for out_pulse_en_mdio_penda |
0 | STATUS_OUT_PULSE_EVNT_PENDA | R | 0h | Status for out_pulse_en_evnt_penda |
1.6.6.7 CPSW_INT_INTR_VECTOR_REG_OUT_PULSE Register (Offset = 1A80h) [reset = 0h]
CPSW_INT_INTR_VECTOR_REG_OUT_PULSE is shown in Figure 12-718 and described in Table 12-1368.
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Interrupt Vector for out_pulse
Table 12-1367 CPSW_INT_INTR_VECTOR_REG_OUT_PULSE InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_CPINT | 4600 1A80h |
Figure 12-718 CPSW_INT_INTR_VECTOR_REG_OUT_PULSE Register LEGEND: R = Read Only; -n = value after reset |
Table 12-1368 CPSW_INT_INTR_VECTOR_REG_OUT_PULSE Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | INTR_VECTOR_OUT_PULSE | R | 0h | Interrupt Vector |