SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3875 describes the internal reference clock options for SERDES0.
CTRLMMR_SERDES0_CLKSEL | |
---|---|
[1:0] CLK_SEL | Internal Clock to SERDES Core |
0x0 | WKUP_HFOSC0_CLKOUT |
0x1 | HFOSC1_CLKOUT |
0x2 | MAIN_PLL3_HSDIV4_CLKOUT |
0x3 | MAIN_PLL2_HSDIV4_CLKOUT |