SPRUIU1C July   2020  – February 2024 DRA821U , DRA821U-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Support Resources
    4.     Glossary
    5.     Export Control Notice
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Device Main Domain
      1. 1.3.1  Arm Cortex-A72 Subsystem
      2. 1.3.2  Arm Cortex-R5F Processor
      3. 1.3.3  Navigator Subsystem
      4. 1.3.4  Region-based Address Translation Module
      5. 1.3.5  Multicore Shared Memory Controller
      6. 1.3.6  DDR Subsystem
      7. 1.3.7  General Purpose Input/Output Interface
      8. 1.3.8  Inter-Integrated Circuit Interface
      9. 1.3.9  Improved Inter-Integrated Circuit Interface
      10. 1.3.10 Multi-channel Serial Peripheral Interface
      11. 1.3.11 Universal Asynchronous Receiver/Transmitter
      12. 1.3.12 Gigabit Ethernet Switch
      13. 1.3.13 Peripheral Component Interconnect Express Subsystem
      14. 1.3.14 Universal Serial Bus (USB) Subsystem
      15. 1.3.15 SerDes
      16. 1.3.16 General Purpose Memory Controller with Error Location Module
      17. 1.3.17 Multimedia Card/Secure Digital Interface
      18. 1.3.18 Enhanced Capture Module
      19. 1.3.19 Enhanced Pulse-Width Modulation Module
      20. 1.3.20 Enhanced Quadrature Encoder Pulse Module
      21. 1.3.21 Controller Area Network
      22. 1.3.22 Audio Tracking Logic
      23. 1.3.23 Multi-channel Audio Serial Port
      24. 1.3.24 Timers
      25. 1.3.25 Internal Diagnostics Modules
    4. 1.4 Device MCU Domain
      1. 1.4.1  MCU Arm Cortex-R5F Processor
      2. 1.4.2  MCU Region-based Address Translation Module
      3. 1.4.3  MCU Navigator Subsystem
      4. 1.4.4  MCU Analog-to-Digital Converter
      5. 1.4.5  MCU Inter-Integrated Circuit Interface
      6. 1.4.6  MCU Improved Inter-Integrated Circuit Interface
      7. 1.4.7  MCU Multi-channel Serial Peripheral Interface
      8. 1.4.8  MCU Universal Asynchronous Receiver/Transmitter
      9. 1.4.9  MCU Gigabit Ethernet Switch
      10. 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      11. 1.4.11 MCU Controller Area Network
      12. 1.4.12 MCU Timers
      13. 1.4.13 MCU Internal Diagnostics Modules
    5. 1.5 Device WKUP Domain
      1. 1.5.1 WKUP Device Management and Security Controller
      2. 1.5.2 WKUP General Purpose Input/Output Interface
      3. 1.5.3 WKUP Inter-Integrated Circuit Interface
      4. 1.5.4 WKUP Universal Asynchronous Receiver/Transmitter
      5. 1.5.5 WKUP Internal Diagnostics Modules
    6. 1.6 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 WKUP Domain Memory Map
    4. 2.4 Processors View Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Integration
      1. 3.2.1 Interconnect Integration in WKUP Domain
      2. 3.2.2 Interconnect Integration in MCU Domain
      3. 3.2.3 Interconnect Integration in MAIN Domain
    3. 3.3 System Interconnect Functional Description
      1. 3.3.1 Master-Slave Connections
      2. 3.3.2 Quality of Service (QoS)
      3. 3.3.3 Route ID
      4. 3.3.4 Initiator-Side Security Controls and Firewalls
        1. 3.3.4.1 Initiator-Side Security Controls (ISC)
          1. 3.3.4.1.1 Special System Level Priv-ID
          2. 3.3.4.1.2 Priv ID and ISC Assignment
        2. 3.3.4.2 Firewalls (FW)
          1. 3.3.4.2.1 Peripheral Firewalls (FW)
          2. 3.3.4.2.2 Memory or Region-based Firewalls
            1. 3.3.4.2.2.1 Region Based Firewall Functional Description
          3. 3.3.4.2.3 Channelized Firewalls
            1. 3.3.4.2.3.1 Channelized Firewall Functional Description
      5. 3.3.5 Null Error Reporting
      6. 3.3.6 VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
        1. 3.3.6.1 Overview and Feature List
          1. 3.3.6.1.1 Features Supported
          2. 3.3.6.1.2 Features Not Supported
        2. 3.3.6.2 Functional Description
          1. 3.3.6.2.1 Functional Operation
            1. 3.3.6.2.1.1  Overview
            2. 3.3.6.2.1.2  FIFOs
            3. 3.3.6.2.1.3  ID Allocator
            4. 3.3.6.2.1.4  Timer
            5. 3.3.6.2.1.5  Timeout Queue
            6. 3.3.6.2.1.6  Write Scoreboard
            7. 3.3.6.2.1.7  Read Scoreboard
            8. 3.3.6.2.1.8  Flush Mode
            9. 3.3.6.2.1.9  Flushing
            10. 3.3.6.2.1.10 Timeout Error Reporting
            11. 3.3.6.2.1.11 Command Timeout Error Reporting
            12. 3.3.6.2.1.12 Unexpected Response Reporting
            13. 3.3.6.2.1.13 Latency and Stalls
            14. 3.3.6.2.1.14 Bypass
            15. 3.3.6.2.1.15 Safety
        3. 3.3.6.3 Interrupt Conditions
          1. 3.3.6.3.1 Transaction Error Interrupt
            1. 3.3.6.3.1.1 Transaction Timeout
            2. 3.3.6.3.1.2 Unexpected Response
            3. 3.3.6.3.1.3 Command Timeout
        4. 3.3.6.4 Memory Map
          1. 3.3.6.4.1  Revision Register (Base Address + 0x00)
          2. 3.3.6.4.2  Configuration Register (Base Address + 0x04)
          3. 3.3.6.4.3  Info Register (Base Address + 0x08)
          4. 3.3.6.4.4  Enable Register (Base Address + 0x0C)
          5. 3.3.6.4.5  Flush Register (Base Address + 0x10)
          6. 3.3.6.4.6  Timeout Value Register (Base Address + 0x14)
          7. 3.3.6.4.7  Timer Register (Base Address + 0x18)
          8. 3.3.6.4.8  Error Interrupt Raw Status/Set Register (Base Address + 0x20)
          9. 3.3.6.4.9  Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
          10. 3.3.6.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
          11. 3.3.6.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
          12. 3.3.6.4.12 Timeout Error Info Register (Base Address + 0x30)
          13. 3.3.6.4.13 Unexpected Response Info Register (Base Address + 0x34)
          14. 3.3.6.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
          15. 3.3.6.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
          16. 3.3.6.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
          17. 3.3.6.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
          18. 3.3.6.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
        5. 3.3.6.5 Integration Overview
          1. 3.3.6.5.1 Parameterization Requirements
        6. 3.3.6.6 I/O Description
          1. 3.3.6.6.1 Clockstop Idle
          2. 3.3.6.6.2 Flush
          3. 3.3.6.6.3 Module I/O
        7. 3.3.6.7 User’s Guide
          1. 3.3.6.7.1 Programmer’s Guide
            1. 3.3.6.7.1.1 Initialization
            2. 3.3.6.7.1.2 Software Flush
      7. 3.3.7 Timeout Gasket (TOG)
    4. 3.4 System Interconnect Registers
      1. 3.4.1 QoS Registers
      2. 3.4.2 Firewall Exception Registers
      3. 3.4.3 Firewall Region Registers
      4. 3.4.4 Null Error Reporting Registers
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  I2C Boot Device Configuration
      10. 4.3.10 MMC/SD Card Boot Device Configuration
      11. 4.3.11 eMMC Boot Device Configuration
      12. 4.3.12 Ethernet Boot Device Configuration
      13. 4.3.13 USB Boot Device Configuration
      14. 4.3.14 PCIe Boot Device Configuration
      15. 4.3.15 UART Boot Device Configuration
      16. 4.3.16 PLL Configuration
        1. 4.3.16.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.16.2 MCU_PLL1
        3. 4.3.16.3 Main PLL1
        4. 4.3.16.4 Main PLL2
        5. 4.3.16.5 HSDIV Values
        6. 4.3.16.6 190
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  Ethernet Boot Parameter Table
      7. 4.4.7  USB Boot Parameter Table
      8. 4.4.8  MMCSD Boot Parameter Table
      9. 4.4.9  UART Boot Parameter Table
      10. 4.4.10 Hyperflash Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 226
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 WKUP_CTRL_MMR0
        1. 5.1.1.1 WKUP_CTRL_MMR0 Overview
        2. 5.1.1.2 WKUP_CTRL_MMR0 Integration
        3. 5.1.1.3 WKUP_CTRL_MMR0 Functional Description
          1. 5.1.1.3.1 Description for WKUP_CTRL_MMR0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  WKUP_CTRL_MMR0 Module Interrupts
            4. 5.1.1.3.1.4  Clock Selection Registers
            5. 5.1.1.3.1.5  Device Feature Registers
            6. 5.1.1.3.1.6  POK Module Registers
            7. 5.1.1.3.1.7  Power and Reset Related Registers
            8. 5.1.1.3.1.8  PRG Related Registers
            9. 5.1.1.3.1.9  Voltage Glitch Detect Control and Status Registers
            10. 5.1.1.3.1.10 I/O Debounce Control Registers
        4. 5.1.1.4 WKUP_CTRL_MMR0 Registers
      2. 5.1.2 MCU_CTRL_MMR0
        1. 5.1.2.1 MCU_CTRL_MMR0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 Register Types
            1. 5.1.2.3.1.1 Kick Protection Registers
            2. 5.1.2.3.1.2 MCU_CTRL_MMR0 Module Interrupts
            3. 5.1.2.3.1.3 Inter-processor Communication Registers
            4. 5.1.2.3.1.4 Timer I/O Muxing Control Registers
            5. 5.1.2.3.1.5 Clock Muxing and Division Registers
            6. 5.1.2.3.1.6 MCU_CPSW0 MAC Address Registers
        4. 5.1.2.4 MCU_CTRL_MMR0 Registers
        5. 5.1.2.5 MCU_SEC_MMR0_DBG_CTRL Registers
        6. 5.1.2.6 MCU_SEC_MMR0_BOOT_CTRL Registers
      3. 5.1.3 CTRL_MMR0
        1. 5.1.3.1 CTRL_MMR0 Overview
        2. 5.1.3.2 CTRL_MMR0 Integration
        3. 5.1.3.3 CTRL_MMR0 Functional Description
          1. 5.1.3.3.1 Description for CTRL_MMR0 Register Types
            1. 5.1.3.3.1.1  Pad Configuration Registers
            2. 5.1.3.3.1.2  Kick Protection Registers
            3. 5.1.3.3.1.3  CTRL_MMR0 Module Interrupts
            4. 5.1.3.3.1.4  Inter-processor Communication Registers
            5. 5.1.3.3.1.5  Timer I/O Muxing Control Registers
            6. 5.1.3.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.3.3.1.7  Clock Muxing and Division Registers
            8. 5.1.3.3.1.8  Ethernet Port Operation Control Registers
            9. 5.1.3.3.1.9  SERDES Lane Function Control Registers
            10. 5.1.3.3.1.10 DDRSS Dynamic Frequency Change Registers
        4. 5.1.3.4 CTRL_MMR0 Registers
        5. 5.1.3.5 SEC_MMR0_DBG_CTRL Registers
        6. 5.1.3.6 SEC_MMR0_BOOT_CTRL Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Subsystems Overview
          1. 5.2.2.1.1 POK Overview
          2. 5.2.2.1.2 PRG / PRG_PP Overview
          3. 5.2.2.1.3 POR Overview
          4. 5.2.2.1.4 POK / PRG(_PP) /POR Overview
          5. 5.2.2.1.5 Timing
          6. 5.2.2.1.6 Restrictions
        2. 5.2.2.2 Power System Modules
          1. 5.2.2.2.1 Power OK (POK) Modules
            1. 5.2.2.2.1.1 POK Programming Model
              1. 5.2.2.2.1.1.1 POK Threshold Setting Programming Sequence
          2. 5.2.2.2.2 Power on Reset (POR) Module
            1. 5.2.2.2.2.1 POR Overview
            2. 5.2.2.2.2.2 POR Integration
            3. 5.2.2.2.2.3 POR Programming Model
          3. 5.2.2.2.3 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.2.2.3.1 PRG_PP Overview
            2. 5.2.2.2.3.2 PRG_PP Integration
            3. 5.2.2.2.3.3 PRG_PP Programming Model
          4. 5.2.2.2.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.2.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.2.5.1 VTM Overview
              1. 5.2.2.2.5.1.1 VTM Features
              2. 5.2.2.2.5.1.2 VTM Not Supported Features
            2. 5.2.2.2.5.2 VTM Integration
            3. 5.2.2.2.5.3 VTM Functional Description
              1. 5.2.2.2.5.3.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.2.5.3.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.2.5.3.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.2.5.3.3 VTM VID Voltage Domains
              4. 5.2.2.2.5.3.4 VTM Clocking
              5. 5.2.2.2.5.3.5 VTM Retention Interface
              6. 5.2.2.2.5.3.6 VTM ECC Aggregator
              7. 5.2.2.2.5.3.7 VTM Programming Model
                1. 5.2.2.2.5.3.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.2.5.3.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.2.5.3.7.3 Sensors Programming Sequences
              8. 5.2.2.2.5.3.8 AVS-Class0
          6. 5.2.2.2.6 Distributed Power Clock and Reset Controller (DPCR)
        3. 5.2.2.3 Power Control Modules
          1. 5.2.2.3.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.3.1.1 PSC Terminology
            2. 5.2.2.3.1.2 PSC Features
            3. 5.2.2.3.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.3.1.3.1 WKUP_PSC0 Device-Specific Information
              2. 5.2.2.3.1.3.2 PSC0 Device-Specific Information
              3. 5.2.2.3.1.3.3 LPSC Dependences Overview
            4. 5.2.2.3.1.4 PSC: Power Domain and Module States
              1. 5.2.2.3.1.4.1 Power Domain States
              2. 5.2.2.3.1.4.2 Module States
              3. 5.2.2.3.1.4.3 Local Reset
            5. 5.2.2.3.1.5 PSC: Executing State Transitions
              1. 5.2.2.3.1.5.1 Power Domain State Transitions
              2. 5.2.2.3.1.5.2 Module State Transitions
              3. 5.2.2.3.1.5.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.3.1.5.4 Recommendations for Power Domain/Module Sequencing
            6. 5.2.2.3.1.6 PSC: Emulation Support in the PSC
            7. 5.2.2.3.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
              1. 5.2.2.3.1.7.1 ARMi_COREn Power State Transition
              2. 5.2.2.3.1.7.2 A72SS Power State Transition
              3. 5.2.2.3.1.7.3 GIC0 Sequencing to Support A72SS Power Management
              4. 5.2.2.3.1.7.4 MSMC0 Clkstop/Powerdown/Disconnect Sequencing
              5. 5.2.2.3.1.7.5 MCU Cortex-R5F Power Modes
          2. 5.2.2.3.2 Integrated Power Management (DMSC)
            1. 5.2.2.3.2.1 DMSC Power Management Overview
              1. 5.2.2.3.2.1.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Voltage Domains
        3. 5.2.3.3 Power Domains
        4. 5.2.3.4 Clock Sources States
        5. 5.2.3.5 Wake-up Sources
        6. 5.2.3.6 Device Power States and Transitions
          1. 5.2.3.6.1 LPM Entry Sequences
          2. 5.2.3.6.2 LPM Exit Sequences
          3. 5.2.3.6.3 IO Retention
          4. 5.2.3.6.4 DDRSS Self-Refresh
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
        2. 5.2.4.2 Dynamic Frequency Scaling (DFS) Operations
      5. 5.2.5 Thermal Management
      6. 5.2.6 Registers
        1. 5.2.6.1 WKUP_VTM0 Registers
        2. 5.2.6.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
      4. 5.3.4 Reset Control
      5. 5.3.5 BOOTMODE Pins
      6. 5.3.6 Reset Sequences
        1. 5.3.6.1 MCU_PORz Overview
        2. 5.3.6.2 MCU_PORz Sequence
        3. 5.3.6.3 MCU_RESETz Sequence
        4. 5.3.6.4 PORz Sequence
        5. 5.3.6.5 RESET_REQz Sequence
      7. 5.3.7 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 424
          3. 5.4.3.1.3 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillators with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 WKUP and MCU Domains PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.5.4.1.2.2 PLLTS16FFCLAFRACF Type Output Clocks
              3. 5.4.5.4.1.2.3 PLL Lock
              4. 5.4.5.4.1.2.4 HSDIVIDER
              5. 5.4.5.4.1.2.5 ICG Module
              6. 5.4.5.4.1.2.6 PLL Power Down
              7. 5.4.5.4.1.2.7 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Registers
        1. 5.4.6.1 MCU_PLL0_CFG Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 PLLCTRL0 Registers
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
      3. 6.1.3 Compute Cluster Registers
    2. 6.2 Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Integration
      3. 6.2.3 A72SS Functional Description
        1. 6.2.3.1  A72SS Block Diagram
        2. 6.2.3.2  A72SS A72 Cluster
        3. 6.2.3.3  A72SS Interfaces and Async Bridges
        4. 6.2.3.4  A72SS Interrupts
          1. 6.2.3.4.1 A72SS Interrupt Inputs
          2. 6.2.3.4.2 A72SS Interrupt Outputs
        5. 6.2.3.5  A72SS Power Management, Clocking and Reset
          1. 6.2.3.5.1 A72SS Power Management
          2. 6.2.3.5.2 A72SS Clocking
        6. 6.2.3.6  A72SS Debug Support
        7. 6.2.3.7  A72SS Timestamps
        8. 6.2.3.8  A72SS Watchdog
        9. 6.2.3.9  A72SS Internal Diagnostics
          1. 6.2.3.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.3.9.2 A72SS CBASS Diagnostics
          3. 6.2.3.9.3 A72SS SRAM Diagnostics
          4. 6.2.3.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.3.10 A72SS Cache Pre-Warming
        11. 6.2.3.11 A72SS Boot
        12. 6.2.3.12 A72SS IPC with Other CPUs
      4. 6.2.4 A72SS Registers
        1. 6.2.4.1 Arm A72 Cluster Registers
        2. 6.2.4.2 A72SS ECC Aggregator Registers
          1. 6.2.4.2.1 A72SS CLUSTER ECC Registers
          2. 6.2.4.2.2 A72SS CORE0 ECC Registers
          3. 6.2.4.2.3 A72SS CORE1 ECC Registers
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
        2. 6.3.1.2 R5FSS Not Supported Features
      2. 6.3.2 R5FSS Integration
        1. 6.3.2.1 R5FSS Integration in MCU Domain
        2. 6.3.2.2 R5FSS Integration in MAIN Domain
      3. 6.3.3 R5FSS Functional Description
        1. 6.3.3.1  R5FSS Block Diagram
        2. 6.3.3.2  R5FSS Cortex-R5F Core
          1. 6.3.3.2.1 L1 Caches
          2. 6.3.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.3.2.3 R5FSS Special Signals
        3. 6.3.3.3  R5FSS Interfaces
          1. 6.3.3.3.1 R5FSS Master Interfaces
          2. 6.3.3.3.2 R5FSS Slave Interfaces
        4. 6.3.3.4  R5FSS Power, Clocking and Reset
          1. 6.3.3.4.1 R5FSS Power
          2. 6.3.3.4.2 R5FSS Clocking
            1. 6.3.3.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.3.4.3 R5FSS Reset
        5. 6.3.3.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.3.5.1 CPU Output Compare Block
            1. 6.3.3.5.1.1 Operating Modes
            2. 6.3.3.5.1.2 Compare Block Active Mode
            3. 6.3.3.5.1.3 Self Test Mode
            4. 6.3.3.5.1.4 Compare Match Test
            5. 6.3.3.5.1.5 Compare Mismatch Test
            6. 6.3.3.5.1.6 Error Forcing Mode
            7. 6.3.3.5.1.7 Self Test Error Forcing Mode
          2. 6.3.3.5.2 Inactivity Monitor Block
            1. 6.3.3.5.2.1 Operating Modes
            2. 6.3.3.5.2.2 Compare Block Active Mode
            3. 6.3.3.5.2.3 Self Test Mode
            4. 6.3.3.5.2.4 Compare Match Test
            5. 6.3.3.5.2.5 Compare Mismatch Test
            6. 6.3.3.5.2.6 Error Forcing Mode
            7. 6.3.3.5.2.7 Self Test Error Forcing Mode
          3. 6.3.3.5.3 Polarity Inversion Logic
        6. 6.3.3.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.3.6.1 VIM Overview
          2. 6.3.3.6.2 VIM Interrupt Inputs
          3. 6.3.3.6.3 VIM Interrupt Outputs
          4. 6.3.3.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.3.6.5 VIM Interrupt Prioritization
          6. 6.3.3.6.6 VIM ECC Support
          7. 6.3.3.6.7 VIM Lockstep Mode
          8. 6.3.3.6.8 VIM IDLE State
          9. 6.3.3.6.9 VIM Interrupt Handling
            1. 6.3.3.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.3.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.3.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.3.6.9.4 Servicing FIQ
            5. 6.3.3.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.3.7  R5FSS Region Address Translation (RAT)
          1. 6.3.3.7.1 RAT Overview
          2. 6.3.3.7.2 RAT Operation
          3. 6.3.3.7.3 RAT Error Logging
          4. 6.3.3.7.4 RAT Protection
        8. 6.3.3.8  R5FSS ECC Support
        9. 6.3.3.9  R5FSS Memory View
        10. 6.3.3.10 R5FSS Debug and Trace
        11. 6.3.3.11 R5FSS Boot Options
        12. 6.3.3.12 R5FSS Core Memory ECC Events
      4. 6.3.4 R5FSS Registers
        1. 6.3.4.1 R5FSS_CCMR5 Registers
        2. 6.3.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.3.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.3.4.4 R5FSS_VIM Registers
        5. 6.3.4.5 R5FSS_RAT Registers
        6. 6.3.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Integration
        1. 8.1.2.1 MSMC Integration in MAIN Domain
        2. 8.1.2.2 639
      3. 8.1.3 MSMC Functional Description
        1. 8.1.3.1  MSMC Block Diagram
        2. 8.1.3.2  MSMC On-Chip Memory Banking
        3. 8.1.3.3  MSMC Snoop Filter and Data Cache
          1. 8.1.3.3.1 Way Partitioning
          2. 8.1.3.3.2 Cache Size Configuration and Associativity
        4. 8.1.3.4  MSMC Access Protection Checks
        5. 8.1.3.5  MSMC Null Slave
        6. 8.1.3.6  MSMC Resource Arbitration
        7. 8.1.3.7  MSMC Error Detection and Correction
          1. 8.1.3.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.3.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.3.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.3.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.3.8  MSMC Interrupts
          1. 8.1.3.8.1 Raw Interrupt Registers
          2. 8.1.3.8.2 Interrupt Enable Registers
          3. 8.1.3.8.3 Triggered and Enabled Interrupts
        9. 8.1.3.9  MSMC Memory Regions
        10. 8.1.3.10 MSMC Hardware Coherence
          1. 8.1.3.10.1 Snoop Filter Broadcast Mode
        11. 8.1.3.11 MSMC Quality-of-Service
        12. 8.1.3.12 MSMC Memory Regions Protection
        13. 8.1.3.13 MSMC Cache Tag View
      4. 8.1.4 MSMC Registers
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
        1. 8.2.1.1 DDRSS Not Supported Features
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Integration
        1. 8.2.3.1 DDRSS Integration in MAIN Domain
      4. 8.2.4 DDRSS Functional Description
        1. 8.2.4.1 DDRSS MSMC2DDR Bridge
          1. 8.2.4.1.1 VBUSM.C Threads
          2. 8.2.4.1.2 Class of Service (CoS)
          3. 8.2.4.1.3 AXI Write Data All-Strobes
          4. 8.2.4.1.4 Inline ECC for SDRAM Data
            1. 8.2.4.1.4.1 ECC Cache
            2. 8.2.4.1.4.2 ECC Statistics
          5. 8.2.4.1.5 Opcode Checking
          6. 8.2.4.1.6 Address Alias Prevention
          7. 8.2.4.1.7 Data Error Detection and Correction
          8. 8.2.4.1.8 AXI Bus Timeout
        2. 8.2.4.2 DDRSS Interrupts
        3. 8.2.4.3 DDRSS Memory Regions
        4. 8.2.4.4 DDRSS ECC Support
        5. 8.2.4.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.4.6 DDR Controller Functional Description
          1. 8.2.4.6.1  DDR PHY Interface (DFI)
          2. 8.2.4.6.2  Command Queue
            1. 8.2.4.6.2.1 Placement Logic
            2. 8.2.4.6.2.2 Command Selection Logic
          3. 8.2.4.6.3  Low Power Control
          4. 8.2.4.6.4  Transaction Processing
          5. 8.2.4.6.5  BIST Engine
          6. 8.2.4.6.6  ECC Engine
          7. 8.2.4.6.7  Address Mapping
          8. 8.2.4.6.8  Paging Policy
          9. 8.2.4.6.9  DDR Controller Initialization
          10. 8.2.4.6.10 Programming LPDDR4 Memories
            1. 8.2.4.6.10.1 Frequency Set Point (FSP)
              1. 8.2.4.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.4.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.4.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.4.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.4.6.10.3 On-Die Termination
              1. 8.2.4.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.4.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.4.6.10.4 Byte Lane Swapping
            5. 8.2.4.6.10.5 DQS Interval Oscillator
              1. 8.2.4.6.10.5.1 Oscillator State Machine
            6. 8.2.4.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.4.6.10.6.1 Normal Operation
              2. 8.2.4.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.4.7 DDR PHY Functional Description
          1. 8.2.4.7.1  Data Slice
          2. 8.2.4.7.2  Address Slice
            1. 8.2.4.7.2.1 Address Swapping
          3. 8.2.4.7.3  Address/Control Slice
          4. 8.2.4.7.4  Clock Slice
          5. 8.2.4.7.5  DDR PHY Initialization
          6. 8.2.4.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.4.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.4.7.8  Low-Power Modes
          9. 8.2.4.7.9  Training Support
            1. 8.2.4.7.9.1 Write Leveling
            2. 8.2.4.7.9.2 Read Gate Training
            3. 8.2.4.7.9.3 Read Data Eye Training
            4. 8.2.4.7.9.4 Write DQ Training
            5. 8.2.4.7.9.5 CA Training
            6. 8.2.4.7.9.6 CS Training
          10. 8.2.4.7.10 Data Bus Inversion (DBI)
          11. 8.2.4.7.11 I/O Pad Calibration
          12. 8.2.4.7.12 DQS Error
        8. 8.2.4.8 PI Functional Description
          1. 8.2.4.8.1 PI Initialization
      5. 8.2.5 DDRSS Registers
        1. 8.2.5.1 DDR Subsystem Registers
        2. 8.2.5.2 DDR Controller Registers
        3. 8.2.5.3 PI Registers
        4. 8.2.5.4 DDR PHY Registers
        5. 8.2.5.5 DDRSS0_ECC_AGGR_CTL Registers
        6. 8.2.5.6 DDRSS0_ECC_AGGR_VBUS Registers
        7. 8.2.5.7 DDRSS0_ECC_AGGR_CFG Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
        3. 8.3.1.3 PVU Not Supported Features
      2. 8.3.2 PVU Integration
      3. 8.3.3 PVU Functional Description
        1. 8.3.3.1  Functional Operation Overview
        2. 8.3.3.2  PVU Channels
        3. 8.3.3.3  TLB
        4. 8.3.3.4  TLB Entry
        5. 8.3.3.5  TLB Selection
        6. 8.3.3.6  DMA Classes
        7. 8.3.3.7  General virtIDs
        8. 8.3.3.8  TLB Lookup
        9. 8.3.3.9  TLB Miss
        10. 8.3.3.10 Multiple Matching Entries
        11. 8.3.3.11 TLB Disable
        12. 8.3.3.12 TLB Chaining
        13. 8.3.3.13 TLB Permissions
        14. 8.3.3.14 Translation
        15. 8.3.3.15 Memory Attributes
        16. 8.3.3.16 Faulted Transactions
        17. 8.3.3.17 Non-Virtual Transactions
        18. 8.3.3.18 Allowed virtIDs
        19. 8.3.3.19 Software Control
        20. 8.3.3.20 Fault Logging
        21. 8.3.3.21 Alignment Restrictions
      4. 8.3.4 PVU Registers
        1. 8.3.4.1 NAVSS_PVU_CFG Registers
        2. 8.3.4.2 NAVSS0_PVU_CFG_TLBIF Registers
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
      2. 8.4.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Integration
        3. 9.2.1.3 GIC Functional Description
          1. 9.2.1.3.1 GIC Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GIC Interrupt Types
          4. 9.2.1.3.4 GIC Interfaces
          5. 9.2.1.3.5 GIC Interrupt Outputs
          6. 9.2.1.3.6 GIC ECC Support
          7. 9.2.1.3.7 GIC AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GIC Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GIC_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 WKUP_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR0 Integration
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 WKUP_GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 GPIOMUX_INTRTR0 Registers
        3. 9.3.3.3 MAIN2MCU_LVL_INTRTR0 Registers
        4. 9.3.3.4 MAIN2MCU_PLS_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 WKUP Domain Interrupt Maps
        1. 9.4.1.1 WKUP_DMSC0 Interrupt Map
        2. 9.4.1.2 WKUP_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.1.3 WKUP_GPIO0_VIRT Interrupt Map
        4. 9.4.1.4 WKUP_ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_R5FSS0_CORE0 Interrupt Map
        2. 9.4.2.2 MCU_R5FSS0_CORE1 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
      3. 9.4.3 MAIN Domain Interrupt Maps
        1. 9.4.3.1 COMPUTE_CLUSTER0 Interrupt Map
          1. 9.4.3.1.1 GIC500 PPI Interrupt Map
          2. 9.4.3.1.2 GIC500 SPI Interrupt Map
          3. 9.4.3.1.3 SoC Event Output Interrupt Map
        2. 9.4.3.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.3.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.3.4 MAIN2MCU_LVL_INTRTR0 Interrupt Map
        5. 9.4.3.5 MAIN2MCU_PLS_INTRTR0 Interrupt Map
        6. 9.4.3.6 GPIOMUX_INTRTR0 Interrupt Map
        7. 9.4.3.7 GPIO0_VIRT Interrupt Map
        8. 9.4.3.8 ESM0 Interrupt Map
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
          1. 10.1.1.10.1 Channel Classes
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 UDMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA External Transmit Channel Setup
        6. 10.1.3.6  UDMA Transmit External Channel Teardown
        7. 10.1.3.7  UDMA-P Transmit Channel Pause
        8. 10.1.3.8  UDMA-P Transmit Operation (Host Packet Type)
        9. 10.1.3.9  UDMA-P Transmit Operation (Monolithic Packet)
        10. 10.1.3.10 UDMA Transmit Operation (TR Packet)
        11. 10.1.3.11 UDMA Transmit Operation (Direct TR)
        12. 10.1.3.12 UDMA Transmit Error/Exception Handling
          1. 10.1.3.12.1 Null Icnt0 Error
          2. 10.1.3.12.2 Unsupported TR Type
          3. 10.1.3.12.3 Bus Errors
        13. 10.1.3.13 UDMA Receive Channel Setup (All Packet Types)
        14. 10.1.3.14 UDMA Receive Channel Teardown
        15. 10.1.3.15 UDMA-P Receive Channel Pause
        16. 10.1.3.16 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        17. 10.1.3.17 UDMA-P Receive FlowID Firewall Operation
        18. 10.1.3.18 UDMA-P Receive Operation (Host Packet)
        19. 10.1.3.19 UDMA-P Receive Operation (Monolithic Packet)
        20. 10.1.3.20 UDMA Receive Operation (TR Packet)
        21. 10.1.3.21 UDMA Receive Operation (Direct TR)
        22. 10.1.3.22 UDMA Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Conditions
            1. 10.1.3.22.1.1 Bus Errors
            2. 10.1.3.22.1.2 Null Icnt0 Error
            3. 10.1.3.22.1.3 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions Exception Conditions
            1. 10.1.3.22.2.1 Descriptor Starvation
            2. 10.1.3.22.2.2 Protocol Errors
            3. 10.1.3.22.2.3 Dropped Packets
            4. 10.1.3.22.2.4 Reception of EOL Delimiter
            5. 10.1.3.22.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.22.2.6 EOP Asserted Late (Long Packets)
        23. 10.1.3.23 UTC Operation
        24. 10.1.3.24 UTC Receive Error/Exception Handling
          1. 10.1.3.24.1 Error Handling
            1. 10.1.3.24.1.1 Null Icnt0 Error
            2. 10.1.3.24.1.2 Unsupported TR Type
          2. 10.1.3.24.2 Exception Conditions
            1. 10.1.3.24.2.1 Reception of EOL Delimiter
            2. 10.1.3.24.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.24.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1  Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Integration
          1. 10.2.1.2.1 NAVSS Interrupt Router Configuration
          2. 10.2.1.2.2 Global Event Map
          3. 10.2.1.2.3 PSI-L System Thread Map (All NAVSS)
          4. 10.2.1.2.4 NAVSS VBUSM Route ID Table
        3. 10.2.1.3 NAVSS Functional Description
        4. 10.2.1.4 NAVSS Interrupt Configuration
          1. 10.2.1.4.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.4.1.1 NAVSS Interrupts Description
            2. 10.2.1.4.1.2 Application Example
        5. 10.2.1.5 NAVSS Top-level Registers
          1. 10.2.1.5.1 NAVSS0_CFG Registers
          2. 10.2.1.5.2 INTR0_INTR_ROUTER_CFG Registers
          3. 10.2.1.5.3 VIRTID_CFG_MMRS Registers
      2. 10.2.2  MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Integration
          1. 10.2.2.2.1  MCU NAVSS Interrupt Router Configuration
          2. 10.2.2.2.2  MCU NAVSS UDMASS Interrupt Aggregator Configuration
          3. 10.2.2.2.3  MCU NAVSS UDMA Configuration
          4. 10.2.2.2.4  MCU NAVSS Ring Accelerator Configuration
          5. 10.2.2.2.5  MCU NAVSS Proxy Configuration
          6. 10.2.2.2.6  MCU NAVSS Secure Proxy Configuration
          7. 10.2.2.2.7  Global Event Map
          8. 10.2.2.2.8  PSI-L System Thread Map (All NAVSS)
          9. 10.2.2.2.9  MCU NAVSS VBUSM Route ID Table
          10. 10.2.2.2.10 1006
        3. 10.2.2.3 MCU NAVSS Functional Description
        4. 10.2.2.4 MCU NAVSS Top-Level Registers
          1. 10.2.2.4.1 MCU_NAVSS0_CFG Registers
          2. 10.2.2.4.2 MCU_NAVSS0_UDMASS_ECCAGGR0 Registers
      3. 10.2.3  Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Integration
        3. 10.2.3.3 UDMA Functional Description
          1. 10.2.3.3.1 Block Diagram
          2. 10.2.3.3.2 General Functionality
            1. 10.2.3.3.2.1  Operational States
            2. 10.2.3.3.2.2  Tx Channel Allocation
            3. 10.2.3.3.2.3  Rx Channel Allocation
            4. 10.2.3.3.2.4  Tx Teardown
            5. 10.2.3.3.2.5  Rx Teardown
            6. 10.2.3.3.2.6  Tx Clock Stop
            7. 10.2.3.3.2.7  Rx Clock Stop
            8. 10.2.3.3.2.8  Rx Thread Enables
            9. 10.2.3.3.2.9  Events
              1. 10.2.3.3.2.9.1 Local Event Inputs
              2. 10.2.3.3.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.3.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.3.2.10 Emulation Control
          3. 10.2.3.3.3 Packet Oriented Transmit Operation
            1. 10.2.3.3.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.3.4 Packet Oriented Receive Operation
            1. 10.2.3.3.4.1 Rx Packet Drop
            2. 10.2.3.3.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.3.5 Third Party Mode Operation
            1. 10.2.3.3.5.1 Events and Flow Control
              1. 10.2.3.3.5.1.1 Channel Triggering
              2. 10.2.3.3.5.1.2 Internal TR Completion Events
            2. 10.2.3.3.5.2 Transmit Operation
              1. 10.2.3.3.5.2.1 Transfer Request
              2. 10.2.3.3.5.2.2 Transfer Response
              3. 10.2.3.3.5.2.3 Data Transfer
              4. 10.2.3.3.5.2.4 Memory Interface Transactions
              5. 10.2.3.3.5.2.5 Error Handling
            3. 10.2.3.3.5.3 Receive Operation
              1. 10.2.3.3.5.3.1 Transfer Request
              2. 10.2.3.3.5.3.2 Transfer Response
              3. 10.2.3.3.5.3.3 Error Handling
            4. 10.2.3.3.5.4 Data Transfer
              1. 10.2.3.3.5.4.1 Memory Interface Transactions
              2. 10.2.3.3.5.4.2 Rx Packet Drop
        4. 10.2.3.4 UDMA Registers
          1. 10.2.3.4.1 UDMASS_UDMAP0_CFG Registers
          2. 10.2.3.4.2 UDMASS_UDMAP0_CFG_TCHAN Registers
          3. 10.2.3.4.3 UDMASS_UDMAP0_CFG_RCHAN Registers
          4. 10.2.3.4.4 UDMASS_UDMAP0_CFG_RFLOW Registers
          5. 10.2.3.4.5 UDMASS_UDMAP0_CFG_RCHANRT Registers
          6. 10.2.3.4.6 UDMASS_UDMAP0_CFG_TCHANRT Registers
      4. 10.2.4  Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Not Supported Features
          3. 10.2.4.1.3 RINGACC Parameters
        2. 10.2.4.2 RINGACC Integration
        3. 10.2.4.3 RINGACC Functional Description
          1. 10.2.4.3.1 Block Diagram
            1. 10.2.4.3.1.1  Configuration Registers
            2. 10.2.4.3.1.2  Source Command FIFO
            3. 10.2.4.3.1.3  Source Write Data FIFO
            4. 10.2.4.3.1.4  Source Read Data FIFO
            5. 10.2.4.3.1.5  Source Write Status FIFO
            6. 10.2.4.3.1.6  Main State Machine
            7. 10.2.4.3.1.7  Destination Command FIFO
            8. 10.2.4.3.1.8  Destination Write Data FIFO
            9. 10.2.4.3.1.9  Destination Read Data FIFO
            10. 10.2.4.3.1.10 Destination Write Status FIFO
          2. 10.2.4.3.2 RINGACC Functional Operation
            1. 10.2.4.3.2.1 Queue Modes
              1. 10.2.4.3.2.1.1 Ring Mode
              2. 10.2.4.3.2.1.2 Messaging Mode
              3. 10.2.4.3.2.1.3 Credentials Mode
              4. 10.2.4.3.2.1.4 Queue Manager Mode
              5. 10.2.4.3.2.1.5 Peek Support
              6. 10.2.4.3.2.1.6 Index Register Operation
            2. 10.2.4.3.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.3.2.6 Host Doorbell Access
            7. 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.3.2.9 Mismatched Element Size Handling
          3. 10.2.4.3.3 Events
          4. 10.2.4.3.4 Bus Error Handling
          5. 10.2.4.3.5 Monitors
            1. 10.2.4.3.5.1 Threshold Monitor
            2. 10.2.4.3.5.2 Watermark Monitor
            3. 10.2.4.3.5.3 Starvation Monitor
            4. 10.2.4.3.5.4 Statistics Monitor
            5. 10.2.4.3.5.5 Overflow
            6. 10.2.4.3.5.6 Ring Update Port
            7. 10.2.4.3.5.7 Tracing
        4. 10.2.4.4 RINGACC Registers
          1. 10.2.4.4.1 NAVSS0_UDMASS_RINGACC0_CFG Registers
          2. 10.2.4.4.2 NAVSS0_UDMASS_RINGACC0_GCFG Registers
          3. 10.2.4.4.3 NAVSS0_UDMASS_RINGACC0_CFG_MON Registers
          4. 10.2.4.4.4 NAVSS0_UDMASS_RINGACC0_CFG_RT Registers
          5. 10.2.4.4.5 NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Registers
      5. 10.2.5  Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
          3. 10.2.5.1.3 Proxy Not Supported Features
        2. 10.2.5.2 Proxy Integration
        3. 10.2.5.3 Proxy Functional Description
          1. 10.2.5.3.1  Targets
            1. 10.2.5.3.1.1 Ring Accelerator
          2. 10.2.5.3.2  Proxy Sizes
          3. 10.2.5.3.3  Proxy Interleaving
          4. 10.2.5.3.4  Proxy Host States
          5. 10.2.5.3.5  Proxy Host Channel Selection
          6. 10.2.5.3.6  Proxy Host Access
            1. 10.2.5.3.6.1 Proxy Host Writes
            2. 10.2.5.3.6.2 Proxy Host Reads
          7. 10.2.5.3.7  Permission Inheritance
          8. 10.2.5.3.8  Buffer Size
          9. 10.2.5.3.9  Error Events
          10. 10.2.5.3.10 Debug Reads
        4. 10.2.5.4 Proxy Registers
          1. 10.2.5.4.1 NAVSS0_PROXY0_CFG_BUF_CFG Registers
          2. 10.2.5.4.2 NAVSS0_PROXY0_BUF_CFG Registers
          3. 10.2.5.4.3 NAVSS0_PROXY_BUF Registers
          4. 10.2.5.4.4 NAVSS0_PROXY_TARGET0_DATA Registers
      6. 10.2.6  Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
          3. 10.2.6.1.3 Secure Proxy Not Supported Features
        2. 10.2.6.2 Secure Proxy Integration
        3. 10.2.6.3 Secure Proxy Functional Description
          1. 10.2.6.3.1  Targets
            1. 10.2.6.3.1.1 Ring Accelerator
          2. 10.2.6.3.2  Buffers
            1. 10.2.6.3.2.1 Proxy Credits
            2. 10.2.6.3.2.2 Proxy Private Word
            3. 10.2.6.3.2.3 Completion Byte
          3. 10.2.6.3.3  Proxy Thread Sizes
          4. 10.2.6.3.4  Proxy Thread Interleaving
          5. 10.2.6.3.5  Proxy States
          6. 10.2.6.3.6  Proxy Host Access
            1. 10.2.6.3.6.1 Proxy Host Writes
            2. 10.2.6.3.6.2 Proxy Host Reads
            3. 10.2.6.3.6.3 Buffer Accesses
            4. 10.2.6.3.6.4 Target Access
            5. 10.2.6.3.6.5 Error State
          7. 10.2.6.3.7  Permission Inheritance
          8. 10.2.6.3.8  Resource Association
          9. 10.2.6.3.9  Direction
          10. 10.2.6.3.10 Threshold Events
          11. 10.2.6.3.11 Error Events
          12. 10.2.6.3.12 Bus Errors and Credits
          13. 10.2.6.3.13 Debug
        4. 10.2.6.4 Secure Proxy Registers
          1. 10.2.6.4.1 NAVSS0_SEC_PROXY0_CFG_MMRS Registers
          2. 10.2.6.4.2 NAVSS0_SEC_PROXY0_CFG_RT Registers
          3. 10.2.6.4.3 NAVSS0_SEC_PROXY0_CFG_SCFG Registers
          4. 10.2.6.4.4 NAVSS0_SEC_PROXY0_SRC_TARGET_DATA Registers
      7. 10.2.7  Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Integration
        3. 10.2.7.3 INTR_AGGR Functional Description
          1. 10.2.7.3.1 Submodule Descriptions
            1. 10.2.7.3.1.1 Status/Mask Registers
            2. 10.2.7.3.1.2 Interrupt Mapping Block
            3. 10.2.7.3.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.3.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.3.1.5 Global Event Multicast
          2. 10.2.7.3.2 General Functionality
            1. 10.2.7.3.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.3.2.2 Interrupt Status
            3. 10.2.7.3.2.3 Interrupt Masked Status
            4. 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.3.2.5 Interrupt Output Generation
            6. 10.2.7.3.2.6 Global Event Counting
            7. 10.2.7.3.2.7 Local Event to Global Event Conversion
            8. 10.2.7.3.2.8 Global Event Multicast
        4. 10.2.7.4 INTR_AGGR Registers
          1. 10.2.7.4.1  MODSS_INTA_CFG Registers
          2. 10.2.7.4.2  MODSS_INTA_CFG_IMAP Registers
          3. 10.2.7.4.3  MODSS_INTA_CFG_INTR Registers
          4. 10.2.7.4.4  UDMASS_INTA0_CFG Registers
          5. 10.2.7.4.5  UDMASS_INTA0_CFG_INTR Registers
          6. 10.2.7.4.6  UDMASS_INTA0_CFG_IMAP Registers
          7. 10.2.7.4.7  UDMASS_INTA0_CFG_L2G Registers
          8. 10.2.7.4.8  UDMASS_INTA0_CFG_MCAST Registers
          9. 10.2.7.4.9  UDMASS_INTA0_CFG_GCNTCFG Registers
          10. 10.2.7.4.10 UDMASS_INTA0_CFG_GCNTRTI Registers
      8. 10.2.8  Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
        3. 10.2.8.3 PSI-L Configuration Registers
        4. 10.2.8.4 PSI-L CFG_PROXY Registers
      9. 10.2.9  PSIL Subsystem (PSILSS)
        1. 10.2.9.1 PSILSS Overview
          1. 10.2.9.1.1 PSILSS Features
        2. 10.2.9.2 PSILSS Functional Description
          1. 10.2.9.2.1 PSILSS Basic Operation
          2. 10.2.9.2.2 PSILSS Event Routing
          3. 10.2.9.2.3 PSILSS Link Down Detection
          4. 10.2.9.2.4 PSILSS Configuration
        3. 10.2.9.3 PSILSS Registers
          1. 10.2.9.3.1 PDMA_USART_PSILSS0 Registers
          2. 10.2.9.3.2 PDMA_SPI_PSILSS0 Registers
      10. 10.2.10 NAVSS North Bridge (NB)
        1. 10.2.10.1 NB Overview
          1. 10.2.10.1.1 Features Supported
          2. 10.2.10.1.2 NB Parameters
            1. 10.2.10.1.2.1 Compliance to Standards
            2. 10.2.10.1.2.2 Features Not Supported
        2. 10.2.10.2 NB Functional Description
          1. 10.2.10.2.1  VBUSM Slave Interfaces
          2. 10.2.10.2.2  VBUSM Master Interface
          3. 10.2.10.2.3  VBUSM.C Interfaces
            1. 10.2.10.2.3.1 Multi-Threading
            2. 10.2.10.2.3.2 Write Command Crediting
            3. 10.2.10.2.3.3 Early Credit Response
            4. 10.2.10.2.3.4 Priority Escalation
          4. 10.2.10.2.4  Source M2M Bridges
          5. 10.2.10.2.5  Destination M2M Bridge
          6. 10.2.10.2.6  M2C Bridge
          7. 10.2.10.2.7  Memory Attribute Tables
          8. 10.2.10.2.8  Outstanding Read Data Limiter
          9. 10.2.10.2.9  Ordering
          10. 10.2.10.2.10 Quality of Service
          11. 10.2.10.2.11 IDLE Behavior
          12. 10.2.10.2.12 Clock Power Management
        3. 10.2.10.3 NB Registers
          1. 10.2.10.3.1 NAVSS0_NBSS_CFG_REGS0_MMRS Registers
          2. 10.2.10.3.2 NAVSS0_NBSS_NB_CFG_MMRS Registers
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA2 (PDMA_DEBUG_CCMCU) Features
            6. 10.3.1.1.1.6  PDMA5 (PDMA_MCAN) Features
            7. 10.3.1.1.1.7  PDMA6 (PDMA_MCASP_G0) Features
            8. 10.3.1.1.1.8  PDMA9 (PDMA_SPI_G0) Features
            9. 10.3.1.1.1.9  PDMA10 (PDMA_SPI_G1) Features
            10. 10.3.1.1.1.10 PDMA13 (PDMA_USART_G0) Features
            11. 10.3.1.1.1.11 PDMA14 (PDMA_USART_G1) Features
            12. 10.3.1.1.1.12 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Integration
          1. 10.3.1.2.1 PDMA Integration in MCU Domain
          2. 10.3.1.2.2 PDMA Integration in MAIN Domain
        3. 10.3.1.3 PDMA Functional Description
          1. 10.3.1.3.1 PDMA Functional Blocks
            1. 10.3.1.3.1.1 Scheduler
            2. 10.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.3.2 PDMA General Functionality
            1. 10.3.1.3.2.1 Operational States
            2. 10.3.1.3.2.2 Clock Stop
            3. 10.3.1.3.2.3 Emulation Control
          3. 10.3.1.3.3 PDMA Events and Flow Control
            1. 10.3.1.3.3.1 Channel Types
              1. 10.3.1.3.3.1.1 X-Y FIFO Mode
              2. 10.3.1.3.3.1.2 MCAN Mode
              3. 10.3.1.3.3.1.3 AASRC Mode
              4. 10.3.1.3.3.1.4 1288
            2. 10.3.1.3.3.2 Channel Triggering
            3. 10.3.1.3.3.3 Completion Events
          4. 10.3.1.3.4 PDMA Transmit Operation
            1. 10.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.3.4.3 Destination Channel Initialization
              1. 10.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.3.4.3.2 Static Transfer Request Setup
              3. 10.3.1.3.4.3.3 1297
              4. 10.3.1.3.4.3.4 PSI-L Destination Thread Enables
            4. 10.3.1.3.4.4 Data Transfer
              1. 10.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.3.4.4.2 MCAN Mode Channel
                1. 10.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.3.4.4.3 AASRC Mode Channel
            5. 10.3.1.3.4.5 Tx Pause
            6. 10.3.1.3.4.6 Tx Teardown
            7. 10.3.1.3.4.7 Tx Channel Reset
            8. 10.3.1.3.4.8 Tx Debug/State Registers
          5. 10.3.1.3.5 PDMA Receive Operation
            1. 10.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.3.5.2 Source Channel Initialization
              1. 10.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.3.5.2.2 Static Transfer Request Setup
              3. 10.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.3.5.3 Data Transfer
              1. 10.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.3.5.3.2 MCAN Mode Channel
                1. 10.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.3.5.3.3 AASRC Mode Channel
            4. 10.3.1.3.5.4 Rx Pause
            5. 10.3.1.3.5.5 Rx Teardown
            6. 10.3.1.3.5.6 Rx Channel Reset
            7. 10.3.1.3.5.7 Rx Debug/State Register
          6. 10.3.1.3.6 PDMA ECC Support
        4. 10.3.1.4 PDMA Registers
          1. 10.3.1.4.1 PDMA5 ECC Registers
          2. 10.3.1.4.2 PDMA9 ECC Registers
          3. 10.3.1.4.3 PDMA10 ECC Registers
          4. 10.3.1.4.4 PDMA PSI-L TX Configuration Registers
          5. 10.3.1.4.5 PDMA PSI-L RX Configuration Registers
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_DEBUG_CCMCU Event Map
          2. 10.3.2.2.2 PDMA_MCAN Event Map
          3. 10.3.2.2.3 PDMA_MCASP_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G0 Event Map
          5. 10.3.2.2.5 PDMA_SPI_G1 Event Map
          6. 10.3.2.2.6 PDMA_USART_G0 Event Map
          7. 10.3.2.2.7 PDMA_USART_G1 Event Map
          8. 10.3.2.2.8 PDMA_USART_G2 Event Map
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
        2. 11.1.1.2 CPTS Not Supported Features
      2. 11.1.2 CPTS Integration
      3. 11.1.3 CPTS Functional Description
        1. 11.1.3.1  CPTS Architecture
        2. 11.1.3.2  CPTS Initialization
        3. 11.1.3.3  32-bit Time Stamp Value
        4. 11.1.3.4  64-bit Time Stamp Value
          1. 11.1.3.4.1 64-Bit Timestamp Nudge
          2. 11.1.3.4.2 64-bit Timestamp PPM
        5. 11.1.3.5  Event FIFO
        6. 11.1.3.6  Timestamp Compare Output
          1. 11.1.3.6.1 Non-Toggle Mode
          2. 11.1.3.6.2 Toggle Mode
        7. 11.1.3.7  Timestamp Sync Output
        8. 11.1.3.8  Timestamp GENF Output
          1. 11.1.3.8.1 GENFn Nudge
          2. 11.1.3.8.2 GENFn PPM
        9. 11.1.3.9  Time Sync Events
          1. 11.1.3.9.1 Time Stamp Push Event
          2. 11.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.3.9.4 Hardware Time Stamp Push Event
        10. 11.1.3.10 Timestamp Compare Event
        11. 11.1.3.11 CPTS Interrupt Handling
      4. 11.1.4 CPTS Registers
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
        2. 11.2.1.2 Timer Manager Not Supported Features
      2. 11.2.2 Timer Manager Integration
      3. 11.2.3 Timer Manager Functional Description
        1. 11.2.3.1 Timer Manager Function Overview
        2. 11.2.3.2 Timer Counter
          1. 11.2.3.2.1 Timer Counter Rollover
        3. 11.2.3.3 Timer Control Module (FSM)
        4. 11.2.3.4 Timer Reprogramming
          1. 11.2.3.4.1 Periodic Hardware Timers
        5. 11.2.3.5 Event FIFO
        6. 11.2.3.6 Output Event Lookup (OES RAM)
      4. 11.2.4 Timer Manager Programming Guide
        1. 11.2.4.1 Timer Manager Low-level Programming Models
          1. 11.2.4.1.1 Surrounding Modules Global Initialization
          2. 11.2.4.1.2 Initialization Sequence
          3. 11.2.4.1.3 Real-time Operating Requirements
            1. 11.2.4.1.3.1 Timer Touch
            2. 11.2.4.1.3.2 Timer Disable
            3. 11.2.4.1.3.3 Timer Enable
          4. 11.2.4.1.4 Power Up/Power Down Sequence
      5. 11.2.5 Timer Manager Registers
        1. 11.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 11.2.5.2 TIMERMGR_CFG_OES Registers
        3. 11.2.5.3 TIMERMGR_CFG_TIMERS Registers
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
        2. 11.3.2.2 Time Sync Routers Integration
          1. 11.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 11.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 11.3.2.3 Time Sync Routers Registers
          1. 11.3.2.3.1 TIMESYNC_INTRTR0 Registers
          2. 11.3.2.3.2 CMPEVT_INTRTR0 Registers
      3. 11.3.3 Time Sync Event Sources
        1. 11.3.3.1 CMPEVT_INTRTR0 Event Map
        2. 11.3.3.2 TIMESYNC_INTRTR0 Event Map
        3. 11.3.3.3 DMSS0 Sync Event Map
        4. 11.3.3.4 PCIE1 Sync Event Map
        5. 11.3.3.5 MCU_CPSW0 Sync Event Map
        6. 11.3.3.6 CPSW0 Sync Event Map
        7. 11.3.3.7 I/O Sync Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MCU Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in WKUP Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO DeepSleep Mode
          6. 12.1.2.4.6 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1501
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in WKUP Domain
          2. 12.1.3.3.2 I2C Integration in MCU Domain
          3. 12.1.3.3.3 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Not Supported Features
        2. 12.1.4.2 I3C Environment
          1. 12.1.4.2.1 I3C Typical Application
            1. 12.1.4.2.1.1 I3C Pins for Typical Connections
            2. 12.1.4.2.1.2 I3C Interface Typical Connections
            3. 12.1.4.2.1.3 1555
        3. 12.1.4.3 I3C Integration
          1. 12.1.4.3.1 I3C Integration in MCU Domain
          2. 12.1.4.3.2 I3C Integration in MAIN Domain
        4. 12.1.4.4 I3C Functional Description
          1. 12.1.4.4.1  I3C Block Diagram
          2. 12.1.4.4.2  I3C Clock Configuration
            1. 12.1.4.4.2.1 Setting Base Frequencies
            2. 12.1.4.4.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.4.2.3 Open-Drain SCL Timing
            4. 12.1.4.4.2.4 Changing Programmed Frequencies
          3. 12.1.4.4.3  I3C Interrupt Requests
          4. 12.1.4.4.4  I3C Power Configuration
          5. 12.1.4.4.5  I3C Dynamic Address Management
          6. 12.1.4.4.6  I3C Retaining Registers Space
          7. 12.1.4.4.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.4.8  I3C Sending CCC Messages
          9. 12.1.4.4.9  I3C In-Band Interrupt
            1. 12.1.4.4.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.4.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.4.10 I3C Hot-Join Request
          11. 12.1.4.4.11 I3C Immediate Commands
          12. 12.1.4.4.12 I3C Host Commands
          13. 12.1.4.4.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.4.13.1 SDR Private Write Message
            2. 12.1.4.4.13.2 SDR Private Read Message
            3. 12.1.4.4.13.3 SDR Payload Length Adjustment
        5. 12.1.4.5 I3C Programming Guide
          1. 12.1.4.5.1 I3C Power-On Programming Model
          2. 12.1.4.5.2 I3C Static Devices Programming
          3. 12.1.4.5.3 I3C DAA Procedure Initiation
          4. 12.1.4.5.4 I3C SDR Write Message Programming Model
          5. 12.1.4.5.5 I3C SDR Read Message Programming Model
          6. 12.1.4.5.6 I3C DDR Write Message Programming Model
          7. 12.1.4.5.7 I3C DDR Read Message Programming Model
        6. 12.1.4.6 I3C Registers
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Not Supported Features
        2. 12.1.5.2 MCSPI Environment
          1. 12.1.5.2.1 Basic MCSPI Pins for Master Mode
          2. 12.1.5.2.2 Basic MCSPI Pins for Slave Mode
          3. 12.1.5.2.3 MCSPI Internal Connectivity
          4. 12.1.5.2.4 MCSPI Protocol and Data Format
            1. 12.1.5.2.4.1 Transfer Format
          5. 12.1.5.2.5 MCSPI in Controller Mode
          6. 12.1.5.2.6 MCSPI in Peripheral Mode
        3. 12.1.5.3 MCSPI Integration
          1. 12.1.5.3.1 MCSPI Integration in MCU Domain
          2. 12.1.5.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.5.4 MCSPI Functional Description
          1. 12.1.5.4.1 SPI Block Diagram
          2. 12.1.5.4.2 MCSPI Reset
          3. 12.1.5.4.3 MCSPI Controller Mode
            1. 12.1.5.4.3.1 Controller Mode Features
            2. 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.4.3.5 Single-Channel Controller Mode
              1. 12.1.5.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.4.3.5.3 Turbo Mode
            6. 12.1.5.4.3.6 Start-Bit Mode
            7. 12.1.5.4.3.7 Chip-Select Timing Control
            8. 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.4.3.8.1 Clock Ratio Granularity
          4. 12.1.5.4.4 MCSPI Peripheral Mode
            1. 12.1.5.4.4.1 Dedicated Resources
            2. 12.1.5.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.4.6 MCSPI FIFO Buffer Management
            1. 12.1.5.4.6.1 Buffer Almost Full
            2. 12.1.5.4.6.2 Buffer Almost Empty
            3. 12.1.5.4.6.3 End of Transfer Management
            4. 12.1.5.4.6.4 Multiple MCSPI Word Access
            5. 12.1.5.4.6.5 First MCSPI Word Delay
          7. 12.1.5.4.7 MCSPI Interrupts
            1. 12.1.5.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.4.7.1.1 TXx_EMPTY
              2. 12.1.5.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.1.3 RXx_ FULL
              4. 12.1.5.4.7.1.4 End Of Word Count
            2. 12.1.5.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.4.7.2.1 TXx_EMPTY
              2. 12.1.5.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.2.3 RXx_FULL
              4. 12.1.5.4.7.2.4 RX0_OVERFLOW
              5. 12.1.5.4.7.2.5 End Of Word Count
            3. 12.1.5.4.7.3 Interrupt-Driven Operation
            4. 12.1.5.4.7.4 Polling
          8. 12.1.5.4.8 MCSPI DMA Requests
          9. 12.1.5.4.9 MCSPI Power Saving Management
            1. 12.1.5.4.9.1 Normal Mode
            2. 12.1.5.4.9.2 Idle Mode
              1. 12.1.5.4.9.2.1 Force-Idle Mode
        5. 12.1.5.5 MCSPI Programming Guide
          1. 12.1.5.5.1 MCSPI Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 MCSPI Global Initialization
              1. 12.1.5.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.5.5.2 MCSPI Operational Mode Configuration
            1. 12.1.5.5.2.1 MCSPI Operational Modes
              1. 12.1.5.5.2.1.1 Common Transfer Sequence
              2. 12.1.5.5.2.1.2 End of Transfer Sequences
              3. 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.5.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.5.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.5.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.5.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.5.5.2.1.7 Peripheral Receive-Only
              8. 12.1.5.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.5.2.1.8.5 Transmit-Only
                6. 12.1.5.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.5.6 MCSPI Registers
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Not Supported Features
        2. 12.1.6.2 UART Environment
          1. 12.1.6.2.1 UART Functional Interfaces
            1. 12.1.6.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.6.2.1.2 UART Interface Description
            3. 12.1.6.2.1.3 UART Protocol and Data Format
            4. 12.1.6.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.6.2.2 RS-485 Functional Interfaces
            1. 12.1.6.2.2.1 System Using RS-485 Communication
            2. 12.1.6.2.2.2 RS-485 Interface Description
          3. 12.1.6.2.3 IrDA Functional Interfaces
            1. 12.1.6.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.6.2.3.2 IrDA Interface Description
            3. 12.1.6.2.3.3 IrDA Protocol and Data Format
              1. 12.1.6.2.3.3.1 SIR Mode
                1. 12.1.6.2.3.3.1.1 Frame Format
                2. 12.1.6.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.6.2.3.3.1.3 Abort Sequence
                4. 12.1.6.2.3.3.1.4 Pulse Shaping
                5. 12.1.6.2.3.3.1.5 Encoder
                6. 12.1.6.2.3.3.1.6 Decoder
                7. 12.1.6.2.3.3.1.7 IR Address Checking
              2. 12.1.6.2.3.3.2 SIR Free-Format Mode
              3. 12.1.6.2.3.3.3 MIR Mode
                1. 12.1.6.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.6.2.3.3.3.2 SIP Generation
              4. 12.1.6.2.3.3.4 FIR Mode
          4. 12.1.6.2.4 CIR Functional Interfaces
            1. 12.1.6.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.6.2.4.2 CIR Interface Description
            3. 12.1.6.2.4.3 CIR Protocol and Data Format
              1. 12.1.6.2.4.3.1 Carrier Modulation
              2. 12.1.6.2.4.3.2 Pulse Duty Cycle
              3. 12.1.6.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.6.3 UART Integration
          1. 12.1.6.3.1 UART Integration in WKUP Domain
          2. 12.1.6.3.2 UART Integration in MCU Domain
          3. 12.1.6.3.3 UART Integration in MAIN Domain
        4. 12.1.6.4 UART Functional Description
          1. 12.1.6.4.1 UART Block Diagram
          2. 12.1.6.4.2 UART Clock Configuration
          3. 12.1.6.4.3 UART Software Reset
            1. 12.1.6.4.3.1 Independent TX/RX
          4. 12.1.6.4.4 UART Power Management
            1. 12.1.6.4.4.1 UART Mode Power Management
              1. 12.1.6.4.4.1.1 Module Power Saving
              2. 12.1.6.4.4.1.2 System Power Saving
            2. 12.1.6.4.4.2 IrDA Mode Power Management
              1. 12.1.6.4.4.2.1 Module Power Saving
              2. 12.1.6.4.4.2.2 System Power Saving
            3. 12.1.6.4.4.3 CIR Mode Power Management
              1. 12.1.6.4.4.3.1 Module Power Saving
              2. 12.1.6.4.4.3.2 System Power Saving
            4. 12.1.6.4.4.4 Local Power Management
          5. 12.1.6.4.5 UART Interrupt Requests
            1. 12.1.6.4.5.1 UART Mode Interrupt Management
              1. 12.1.6.4.5.1.1 UART Interrupts
              2. 12.1.6.4.5.1.2 Wake-Up Interrupt
            2. 12.1.6.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.4.5.2.1 IrDA Interrupts
              2. 12.1.6.4.5.2.2 Wake-Up Interrupts
            3. 12.1.6.4.5.3 CIR Mode Interrupt Management
              1. 12.1.6.4.5.3.1 CIR Interrupts
              2. 12.1.6.4.5.3.2 Wake-Up Interrupts
          6. 12.1.6.4.6 UART FIFO Management
            1. 12.1.6.4.6.1 FIFO Trigger
              1. 12.1.6.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.4.6.1.2 Receive FIFO Trigger
            2. 12.1.6.4.6.2 FIFO Interrupt Mode
            3. 12.1.6.4.6.3 FIFO Polled Mode Operation
            4. 12.1.6.4.6.4 FIFO DMA Mode Operation
              1. 12.1.6.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.4.6.4.3 DMA Transmission
              4. 12.1.6.4.6.4.4 DMA Reception
          7. 12.1.6.4.7 UART Mode Selection
            1. 12.1.6.4.7.1 Register Access Modes
              1. 12.1.6.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.4.7.1.2 Register Access Submode
              3. 12.1.6.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.4.7.2.1 Registers Available for the UART Function
              2. 12.1.6.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.4.8 UART Protocol Formatting
            1. 12.1.6.4.8.1 UART Mode
              1. 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.1.3 UART Data Formatting
                1. 12.1.6.4.8.1.3.1 Frame Formatting
                2. 12.1.6.4.8.1.3.2 Hardware Flow Control
                3. 12.1.6.4.8.1.3.3 Software Flow Control
                  1. 1.6.4.8.1.3.3.1 Receive (RX)
                  2. 1.6.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.4.8.1.3.4 Autobauding Modes
                5. 12.1.6.4.8.1.3.5 Error Detection
                6. 12.1.6.4.8.1.3.6 Overrun During Receive
                7. 12.1.6.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.4.8.1.3.7.1 Time-Out Counter
                  2. 1.6.4.8.1.3.7.2 Break Condition
            2. 12.1.6.4.8.2 RS-485 Mode
              1. 12.1.6.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.4.8.3 IrDA Mode
              1. 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.3.3 IrDA Data Formatting
                1. 12.1.6.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.4.8.3.3.2  IrDA Reception Control
                3. 12.1.6.4.8.3.3.3  IR Address Checking
                4. 12.1.6.4.8.3.3.4  Frame Closing
                5. 12.1.6.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.4.8.3.3.6  Error Detection
                7. 12.1.6.4.8.3.3.7  Underrun During Transmission
                8. 12.1.6.4.8.3.3.8  Overrun During Receive
                9. 12.1.6.4.8.3.3.9  Status FIFO
                10. 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.4.8.3.3.11 Time-guard
              4. 12.1.6.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.4.8.3.4.1 Abort Sequence
                2. 12.1.6.4.8.3.4.2 Pulse Shaping
                3. 12.1.6.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.4.8.4 CIR Mode
              1. 12.1.6.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.4.8.4.2 CIR Data Formatting
                1. 12.1.6.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.4.8.4.2.2 CIR Transmission
                3. 12.1.6.4.8.4.2.3 CIR Reception
        5. 12.1.6.5 UART Programming Guide
          1. 12.1.6.5.1 UART Global Initialization
            1. 12.1.6.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.6.5.1.2 UART Module Global Initialization
          2. 12.1.6.5.2 UART Mode selection
          3. 12.1.6.5.3 UART Submode selection
          4. 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.5.4.1 DMA mode Settings
            2. 12.1.6.5.4.2 FIFO Trigger Settings
          5. 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.5.5.1 Baud rate settings
            2. 12.1.6.5.5.2 Interrupt settings
            3. 12.1.6.5.5.3 Protocol settings
            4. 12.1.6.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.5.6.1 Hardware Flow Control Configuration
            2. 12.1.6.5.6.2 Software Flow Control Configuration
          7. 12.1.6.5.7 IrDA Programming Model
            1. 12.1.6.5.7.1 SIR mode
              1. 12.1.6.5.7.1.1 Receive
              2. 12.1.6.5.7.1.2 Transmit
            2. 12.1.6.5.7.2 MIR mode
              1. 12.1.6.5.7.2.1 Receive
              2. 12.1.6.5.7.2.2 Transmit
            3. 12.1.6.5.7.3 FIR mode
              1. 12.1.6.5.7.3.1 Receive
              2. 12.1.6.5.7.3.2 Transmit
        6. 12.1.6.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (MCU_CPSW0)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 MCU_CPSW0 Features
          2. 12.2.1.1.2 MCU_CPSW0 Not Supported Features
          3. 12.2.1.1.3 Terminology
        2. 12.2.1.2 MCU_CPSW0 Environment
          1. 12.2.1.2.1 MCU_CPSW0 RMII Interface
          2. 12.2.1.2.2 MCU_CPSW0 RGMII Interface
        3. 12.2.1.3 MCU_CPSW0 Integration
        4. 12.2.1.4 MCU_CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_2G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1 Free Table Entry
                2. 12.2.1.4.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.4.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.4.6.1.9.7 VLAN Table Entry
              10. 12.2.1.4.6.1.10 ALE Policing and Classification
                1. 12.2.1.4.6.1.10.1 ALE Classification
                  1. 2.1.4.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.4.6.1.11 DSCP
              12. 12.2.1.4.6.1.12 Packet Forwarding Processes
                1. 12.2.1.4.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.12.3 Egress Process
                4. 12.2.1.4.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.12.4.1 Learning Process
                  2. 2.1.4.6.1.12.4.2 Updating Process
                  3. 2.1.4.6.1.12.4.3 Touching Process
              13. 12.2.1.4.6.1.13 VLAN Aware Mode
              14. 12.2.1.4.6.1.14 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 1945
                1. 12.2.1.4.6.10.1.1 1946
                  1. 2.1.4.6.10.1.1.1 CRC Insertion
                  2. 2.1.4.6.10.1.1.2 MTXER
                  3. 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
                  4. 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
                  5. 2.1.4.6.10.1.1.5 Back Off
                  6. 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
                  7. 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.4.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.4.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.4.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.4.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.4.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.4.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.4.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.4.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.4.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.4.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.4.6.18.10 2045
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 2073
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.4.8.3 CPPI Checksum Offload
              1. 12.2.1.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.3.1.1 IPV4 UDP
                2. 12.2.1.4.8.3.1.2 IPV4 TCP
                3. 12.2.1.4.8.3.1.3 IPV6 UDP
                4. 12.2.1.4.8.3.1.4 IPV6 TCP
            4. 12.2.1.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.4.8.5 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 MCU_CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 MCU_CPSW0 Registers
          1. 12.2.1.6.1  MCU_CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  MCU_CPSW0_SGMII Registers
          3. 12.2.1.6.3  MCU_CPSW0_MDIO Registers
          4. 12.2.1.6.4  MCU_CPSW0_CPTS Registers
          5. 12.2.1.6.5  MCU_CPSW0_CONTROL Registers
          6. 12.2.1.6.6  MCU_CPSW0_CPINT Registers
          7. 12.2.1.6.7  MCU_CPSW0_RAM Registers
          8. 12.2.1.6.8  MCU_CPSW0_STAT0 Registers
          9. 12.2.1.6.9  MCU_CPSW0_STAT1 Registers
          10. 12.2.1.6.10 MCU_CPSW0_ALE Registers
          11. 12.2.1.6.11 MCU_CPSW0_ECC Registers
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Integration
        4. 12.2.2.4 CPSW0 Functional Description
          1. 12.2.2.4.1 Functional Block Diagram
          2. 12.2.2.4.2 CPSW Ports
            1. 12.2.2.4.2.1 Interface Mode Selection
          3. 12.2.2.4.3 Clocking
            1. 12.2.2.4.3.1 Subsystem Clocking
            2. 12.2.2.4.3.2 Interface Clocking
              1. 12.2.2.4.3.2.1 RGMII Interface Clocking
              2. 12.2.2.4.3.2.2 RMII Interface Clocking
              3. 12.2.2.4.3.2.3 MDIO Clocking
          4. 12.2.2.4.4 Software IDLE
          5. 12.2.2.4.5 Interrupt Functionality
            1. 12.2.2.4.5.1 EVNT_PEND Interrupt
            2. 12.2.2.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.4.5.5 MDIO Interrupts
          6. 12.2.2.4.6 CPSW_5X
            1. 12.2.2.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.4.6.1.1  Error Handling
              2. 12.2.2.4.6.1.2  Bypass Operations
              3. 12.2.2.4.6.1.3  OUI Deny or Accept
              4. 12.2.2.4.6.1.4  Statistics Counting
              5. 12.2.2.4.6.1.5  Automotive Security Features
              6. 12.2.2.4.6.1.6  CPSW Switching Solutions
                1. 12.2.2.4.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.4.6.1.7.1 InterVLAN Routing
                2. 12.2.2.4.6.1.7.2 OAM Operations
              8. 12.2.2.4.6.1.8  Supervisory packets
              9. 12.2.2.4.6.1.9  Address Table Entry
                1. 12.2.2.4.6.1.9.1  Free Table Entry
                2. 12.2.2.4.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.4.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.4.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.4.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.4.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.4.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.4.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.4.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.4.6.1.9.10 EtherType Table Entry
                11. 12.2.2.4.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.4.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.4.6.1.10 Multicast Address
                1. 12.2.2.4.6.1.10.1 Multicast Ranges
              11. 12.2.2.4.6.1.11 Supervisory Packets
              12. 12.2.2.4.6.1.12 Aging and Auto Aging
              13. 12.2.2.4.6.1.13 ALE Policing and Classification
                1. 12.2.2.4.6.1.13.1 ALE Policing
                2. 12.2.2.4.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.4.6.1.13.3 ALE Classification
                  1. 2.2.4.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.4.6.1.14 Mirroring
              15. 12.2.2.4.6.1.15 Trunking
              16. 12.2.2.4.6.1.16 DSCP
              17. 12.2.2.4.6.1.17 Packet Forwarding Processes
                1. 12.2.2.4.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.4.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.4.6.1.17.3 Egress Process
                4. 12.2.2.4.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.4.6.1.17.4.1 Learning Process
                  2. 2.2.4.6.1.17.4.2 Updating Process
                  3. 2.2.4.6.1.17.4.3 Touching Process
              18. 12.2.2.4.6.1.18 VLAN Aware Mode
              19. 12.2.2.4.6.1.19 VLAN Unaware Mode
            2. 12.2.2.4.6.2  Packet Priority Handling
              1. 12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.4.6.3  CPPI Port Ingress
            4. 12.2.2.4.6.4  Packet CRC Handling
              1. 12.2.2.4.6.4.1 Transmit VLAN Processing
                1. 12.2.2.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.4.6.5  FIFO Memory Control
            6. 12.2.2.4.6.6  FIFO Transmit Queue Control
              1. 12.2.2.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.4.6.7.1 IET Configuration
            8. 12.2.2.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.4.6.9  Audio Video Bridging
              1. 12.2.2.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.4.6.10 Ethernet MAC Sliver
              1. 12.2.2.4.6.10.1  CRC Insertion
              2. 12.2.2.4.6.10.2  MTXER
              3. 12.2.2.4.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.4.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.4.6.10.5  Back Off
              6. 12.2.2.4.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.4.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.4.6.10.8  RMII Interface
                1. 12.2.2.4.6.10.8.1 Features
                2. 12.2.2.4.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.4.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.4.6.10.9  RGMII Interface
                1. 12.2.2.4.6.10.9.1 Features
                2. 12.2.2.4.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.4.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.4.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.4.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.4.6.10.10 Frame Classification
              11. 12.2.2.4.6.10.11 Receive FIFO Architecture
            11. 12.2.2.4.6.11 Embedded Memories
            12. 12.2.2.4.6.12 Memory Error Detection and Correction
              1. 12.2.2.4.6.12.1 Packet Header ECC
              2. 12.2.2.4.6.12.2 Packet Protect CRC
              3. 12.2.2.4.6.12.3 Aggregator RAM Control
            13. 12.2.2.4.6.13 Ethernet Port Flow Control
              1. 12.2.2.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.4.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.4.6.14 PFC Trigger Rules
              1. 12.2.2.4.6.14.1 Destination Based Rule
              2. 12.2.2.4.6.14.2 Sum of Outflows Rule
              3. 12.2.2.4.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.4.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.4.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.4.6.16 Ethernet Switch Latency
            17. 12.2.2.4.6.17 MAC Emulation Control
            18. 12.2.2.4.6.18 MAC Command IDLE
            19. 12.2.2.4.6.19 CPSW Network Statistics
              1. 12.2.2.4.6.19.1  Rx-only Statistics Descriptions
                1. 12.2.2.4.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.4.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.4.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.4.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.4.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.4.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.4.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.4.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.4.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.4.6.19.1.11 RX IPG Error
                12. 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.4.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.4.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.4.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.4.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.4.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.4.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.4.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.4.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.4.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.4.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.4.6.19.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.4.6.19.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.4.6.19.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.4.6.19.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.4.6.19.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.4.6.19.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.4.6.19.8  Tx-only Statistics Descriptions
                1. 12.2.2.4.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.4.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.4.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.4.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.4.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.4.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.4.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.4.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.4.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.4.6.19.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
              10. 12.2.2.4.6.19.10 2324
          7. 12.2.2.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.4.7.1  CPSW0 CPTS Integration
            2. 12.2.2.4.7.2  CPTS Architecture
            3. 12.2.2.4.7.3  CPTS Initialization
            4. 12.2.2.4.7.4  32-bit Time Stamp Value
            5. 12.2.2.4.7.5  64-bit Time Stamp Value
            6. 12.2.2.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.4.7.7  64-bit Timestamp PPM
            8. 12.2.2.4.7.8  Event FIFO
            9. 12.2.2.4.7.9  Timestamp Compare Output
              1. 12.2.2.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.4.7.10 Timestamp Sync Output
            11. 12.2.2.4.7.11 Timestamp GENFn Output
              1. 12.2.2.4.7.11.1 GENFn Nudge
              2. 12.2.2.4.7.11.2 GENFn PPM
            12. 12.2.2.4.7.12 Timestamp ESTFn
            13. 12.2.2.4.7.13 Time Sync Events
              1. 12.2.2.4.7.13.1 Time Stamp Push Event
              2. 12.2.2.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.4.7.13.5 Ethernet Port Events
                1. 12.2.2.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.2.4.7.13.5.3 2352
            14. 12.2.2.4.7.14 Timestamp Compare Event
              1. 12.2.2.4.7.14.1 32-Bit Mode
              2. 12.2.2.4.7.14.2 64-Bit Mode
            15. 12.2.2.4.7.15 Host Transmit Event
            16. 12.2.2.4.7.16 CPTS Interrupt Handling
          8. 12.2.2.4.8 CPPI Streaming Packet Interface
            1. 12.2.2.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_5X Egress)
            2. 12.2.2.4.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.4.8.3 CPPI Checksum Offload
              1. 12.2.2.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.4.8.3.1.1 IPV4 UDP
                2. 12.2.2.4.8.3.1.2 IPV4 TCP
                3. 12.2.2.4.8.3.1.3 IPV6 UDP
                4. 12.2.2.4.8.3.1.4 IPV6 TCP
            4. 12.2.2.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.4.8.5 Egress Packet Operations
          9. 12.2.2.4.9 MII Management Interface (MDIO)
            1. 12.2.2.4.9.1 MDIO Frame Formats
            2. 12.2.2.4.9.2 MDIO Functional Description
        5. 12.2.2.5 CPSW0 Programming Guide
          1. 12.2.2.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.5.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.5.3 MDIO Software Interface
            1. 12.2.2.5.3.1 Initializing the MDIO Module
            2. 12.2.2.5.3.2 Writing Data To a PHY Register
            3. 12.2.2.5.3.3 Reading Data From a PHY Register
        6. 12.2.2.6 CPSW0 Registers
          1. 12.2.2.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.2.6.2  CPSW0_SGMII Registers
          3. 12.2.2.6.3  CPSW0_MDIO Registers
          4. 12.2.2.6.4  CPSW0_CPTS Registers
          5. 12.2.2.6.5  CPSW0_CONTROL Registers
          6. 12.2.2.6.6  CPSW0_CPINT Registers
          7. 12.2.2.6.7  CPSW0_RAM Registers
          8. 12.2.2.6.8  CPSW0_STAT Registers
          9. 12.2.2.6.9  CPSW0_ALE Registers
          10. 12.2.2.6.10 CPSW0_PCSR Registers
          11. 12.2.2.6.11 CPSW0_ECC Registers
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.3.2 PCIe Subsystem Environment
        3. 12.2.3.3 PCIe Subsystem Integration
        4. 12.2.3.4 PCIe Subsystem Functional Description
          1. 12.2.3.4.1  PCIe Subsystem Block Diagram
            1. 12.2.3.4.1.1 PCIe Core Module
            2. 12.2.3.4.1.2 PCIe PHY Interface
            3. 12.2.3.4.1.3 CBA Infrastructure
            4. 12.2.3.4.1.4 VBUSM to AXI Bridges
            5. 12.2.3.4.1.5 AXI to VBUSM Bridges
            6. 12.2.3.4.1.6 VBUSP to APB Bridge
            7. 12.2.3.4.1.7 Custom Logic
          2. 12.2.3.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.4.2.1 PCIe Conventional Reset
            2. 12.2.3.4.2.2 PCIe Function Level Reset
            3. 12.2.3.4.2.3 PCIe Reset Isolation
              1. 12.2.3.4.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.4.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.4.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.4.2.4 PCIe Reset Limitations
            5. 12.2.3.4.2.5 PCIe Reset Requirements
          3. 12.2.3.4.3  PCIe Subsystem Power Management
            1. 12.2.3.4.3.1 CBA Power Management
          4. 12.2.3.4.4  PCIe Subsystem Interrupts
            1. 12.2.3.4.4.1 Interrupts Aggregation
            2. 12.2.3.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.3.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.3.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.3.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.3.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.4.4.3.5 PTM Valid Interrupt
            4. 12.2.3.4.4.4 Interrupt Generation in RP Mode
            5. 12.2.3.4.4.5 Interrupt Reception in RP Mode
              1. 12.2.3.4.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.4.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.3.4.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.3.4.4.6.1 PCIe Local Interrupt
              2. 12.2.3.4.4.6.2 PHY Interrupt
              3. 12.2.3.4.4.6.3 Link down Interrupt
              4. 12.2.3.4.4.6.4 Transaction Error Interrupts
              5. 12.2.3.4.4.6.5 Power Management Event Interrupt
              6. 12.2.3.4.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.3.4.4.7 ECC Aggregator Interrupts
            8. 12.2.3.4.4.8 CPTS Interrupt
          5. 12.2.3.4.5  PCIe Subsystem DMA Support
            1. 12.2.3.4.5.1 PCIe DMA Support in RP Mode
            2. 12.2.3.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.3.4.6  PCIe Subsystem Transactions
            1. 12.2.3.4.6.1 PCIe Supported Transactions
            2. 12.2.3.4.6.2 PCIe Transaction Limitations
          7. 12.2.3.4.7  PCIe Subsystem Address Translation
            1. 12.2.3.4.7.1 PCIe Inbound Address Translation
              1. 12.2.3.4.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.4.7.2 PCIe Outbound Address Translation
              1. 12.2.3.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.4.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.4.8.1 End Point SR-IOV Support
            2. 12.2.3.4.8.2 Root Port ATS Support
            3. 12.2.3.4.8.3 VirtID Mapping
          9. 12.2.3.4.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.4.11 PCIe Subsystem Loopback
            1. 12.2.3.4.11.1 PCIe PIPE Loopback
              1. 12.2.3.4.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.4.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.4.12 PCIe Subsystem Error Handling
            1. 12.2.3.4.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.4.13.1 PCIe Parity
            2. 12.2.3.4.13.2 ECC Aggregators
            3. 12.2.3.4.13.3 RAM ECC Inversion
          14. 12.2.3.4.14 LTSSM State Encoding
        5. 12.2.3.5 PCIe Subsystem Registers
          1. 12.2.3.5.1  PCIE_CORE_EP_PF Registers
          2. 12.2.3.5.2  PCIE_CORE_EP_VF Registers
          3. 12.2.3.5.3  PCIE_CORE_RP Registers
          4. 12.2.3.5.4  PCIE_CORE_LM Registers
          5. 12.2.3.5.5  PCIE_CORE_AXI Registers
          6. 12.2.3.5.6  PCIE_INTD Registers
          7. 12.2.3.5.7  PCIE_VMAP Registers
          8. 12.2.3.5.8  PCIE_CPTS Registers
          9. 12.2.3.5.9  PCIE_USER_CFG Registers
          10. 12.2.3.5.10 PCIE_ECC_AGGR0 Registers
          11. 12.2.3.5.11 PCIE_ECC_AGGR1 Registers
          12. 12.2.3.5.12 PCIE_DAT0 Registers
          13. 12.2.3.5.13 PCIE_DAT1 Registers
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Integration
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Type-C Connector Support
          2. 12.2.4.4.2 USB Controller Reset
          3. 12.2.4.4.3 Overcurrent Detection
          4. 12.2.4.4.4 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB_RAMS_INJ_CFG Registers
      5. 12.2.5 Serializer/Deserializer (SerDes)
        1. 12.2.5.1 SerDes Overview
          1. 12.2.5.1.1 SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
        2. 12.2.5.2 SerDes Environment
          1. 12.2.5.2.1 SerDes I/Os
        3. 12.2.5.3 SerDes Integration
          1. 12.2.5.3.1 WIZ Settings
            1. 12.2.5.3.1.1 Interface Selection
            2. 12.2.5.3.1.2 Reference Clock Distribution
            3. 12.2.5.3.1.3 Internal Reference Clock Selection
        4. 12.2.5.4 SerDes Functional Description
          1. 12.2.5.4.1 SerDes Block Diagram
          2. 12.2.5.4.2 SerDes Programming Guide
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MCU Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS ECC Support
            1. 12.3.1.4.2.1 FSS ECC Calculation
          3. 12.3.1.4.3 FSS Modes of Operation
          4. 12.3.1.4.4 FSS Regions
            1. 12.3.1.4.4.1 FSS Regions Boot Size Configuration
          5. 12.3.1.4.5 FSS Memory Regions
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Real-Time Operation
          3. 12.3.1.5.3 FSS Power Up/Down Sequence
        6. 12.3.1.6 FSS Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MCU Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.4.2.2 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
            2. 12.3.2.4.11.2 2576
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        6. 12.3.2.6 OSPI Registers
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 HyperBus Not Supported Features
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Integration
          1. 12.3.3.3.1 HyperBus Integration in MCU Domain
        4. 12.3.3.4 HyperBus Functional Description
          1. 12.3.3.4.1 HyperBus Interrupts
          2. 12.3.3.4.2 HyperBus ECC Support
            1. 12.3.3.4.2.1 ECC Aggregator
          3. 12.3.3.4.3 HyperBus Internal FIFOs
          4. 12.3.3.4.4 HyperBus Data Regions
          5. 12.3.3.4.5 HyperBus True Continuous Read (TCR) Mode
        5. 12.3.3.5 HyperBus Programming Guide
          1. 12.3.3.5.1 HyperBus Initialization Sequence
            1. 12.3.3.5.1.1 HyperFlash Access
            2. 12.3.3.5.1.2 HyperRAM Access
          2. 12.3.3.5.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.5.3 HyperBus Power Up/Down Sequence
        6. 12.3.3.6 HyperBus Registers
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Not Supported Features
        2. 12.3.4.2 GPMC Environment
          1. 12.3.4.2.1 GPMC Modes
          2. 12.3.4.2.2 GPMC I/O Signals
        3. 12.3.4.3 GPMC Integration
          1. 12.3.4.3.1 GPMC Integration in MAIN Domain
        4. 12.3.4.4 GPMC Functional Description
          1. 12.3.4.4.1  GPMC Block Diagram
          2. 12.3.4.4.2  GPMC Clock Configuration
          3. 12.3.4.4.3  GPMC Power Management
          4. 12.3.4.4.4  GPMC Interrupt Requests
          5. 12.3.4.4.5  GPMC Interconnect Port Interface
          6. 12.3.4.4.6  GPMC Address and Data Bus
            1. 12.3.4.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.4.7.2 Access Protocol
              1. 12.3.4.4.7.2.1 Supported Devices
              2. 12.3.4.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.4.7.3 External Signals
              1. 12.3.4.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.4.7.3.1.5 Wait With NAND Device
                6. 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.4.7.3.2 DIR Pin
              3. 12.3.4.4.7.3.3 Reset
              4. 12.3.4.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.4.7.4 Error Handling
          8. 12.3.4.4.8  GPMC Timing Setting
            1. 12.3.4.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.4.8.6  GPMC_CLKOUT
            7. 12.3.4.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.4.8.8.1 Access Time on Read Access
              2. 12.3.4.4.8.8.2 Access Time on Write Access
            9. 12.3.4.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.4.8.10 Bus Keeping Support
          9. 12.3.4.4.9  GPMC NOR Access Description
            1. 12.3.4.4.9.1 Asynchronous Access Description
              1. 12.3.4.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.4.9.2 Synchronous Access Description
              1. 12.3.4.4.9.2.1 Synchronous Single Read
              2. 12.3.4.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.4.9.2.3 Synchronous Single Write
              4. 12.3.4.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.4.9.4 Page and Burst Support
            5. 12.3.4.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.4.10 GPMC pSRAM Access Specificities
          11. 12.3.4.4.11 GPMC NAND Access Description
            1. 12.3.4.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.4.11.1.3 Command Latch Cycle
              4. 12.3.4.4.11.1.4 Address Latch Cycle
              5. 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.4.11.2 NAND Device-Ready Pin
              1. 12.3.4.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.4.11.3 ECC Calculator
              1. 12.3.4.4.11.3.1 Hamming Code
                1. 12.3.4.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.4.11.3.1.2 ECC Enabling
                3. 12.3.4.4.11.3.1.3 ECC Computation
                4. 12.3.4.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.4.11.3.2 BCH Code
                1. 12.3.4.4.11.3.2.1 Requirements
                2. 12.3.4.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.4.11.3.2.2.3 Wrapping Modes
                    1. 4.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.4.11.3.2.2.3.2  Mode 0x1
                    3. 4.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.4.11.3.2.2.3.4  Mode 0x2
                    5. 4.4.11.3.2.2.3.5  Mode 0x3
                    6. 4.4.11.3.2.2.3.6  Mode 0x7
                    7. 4.4.11.3.2.2.3.7  Mode 0x8
                    8. 4.4.11.3.2.2.3.8  Mode 0x4
                    9. 4.4.11.3.2.2.3.9  Mode 0x9
                    10. 4.4.11.3.2.2.3.10 Mode 0x5
                    11. 4.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.4.11.4.2 Prefetch Mode
              3. 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.4.11.4.4 Write-Posting Mode
              5. 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.4.12 GPMC Use Cases and Tips
            1. 12.3.4.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.4.12.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.4.12.1.2 Typical GPMC Setup
                1. 12.3.4.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.4.12.2.1 Supported Memories or Devices
                1. 12.3.4.4.12.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.4.12.2.1.2 NAND Interface Protocol
                3. 12.3.4.4.12.2.1.3 NOR Interface Protocol
                4. 12.3.4.4.12.2.1.4 Other Technologies
        5. 12.3.4.5 GPMC Basic Programming Model
          1. 12.3.4.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.5.2 GPMC Initialization
          3. 12.3.4.5.3 GPMC Configuration in NOR Mode
          4. 12.3.4.5.4 GPMC Configuration in NAND Mode
          5. 12.3.4.5.5 Set Memory Access
          6. 12.3.4.5.6 GPMC Timing Parameters
            1. 12.3.4.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.4.6 GPMC Registers
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Not Supported Features
        2. 12.3.5.2 ELM Integration
          1. 12.3.5.2.1 ELM Integration in MAIN Domain
        3. 12.3.5.3 ELM Functional Description
          1. 12.3.5.3.1 ELM Software Reset
          2. 12.3.5.3.2 ELM Power Management
          3. 12.3.5.3.3 ELM Interrupt Requests
          4. 12.3.5.3.4 ELM Processing Initialization
          5. 12.3.5.3.5 ELM Processing Sequence
          6. 12.3.5.3.6 ELM Processing Completion
        4. 12.3.5.4 ELM Basic Programming Model
          1. 12.3.5.4.1 ELM Low-Level Programming Model
            1. 12.3.5.4.1.1 Processing Initialization
            2. 12.3.5.4.1.2 Read Results
            3. 12.3.5.4.1.3 2786
          2. 12.3.5.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.5.5 ELM Registers
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Not Supported Features
        2. 12.3.6.2 MMCSD Environment
          1. 12.3.6.2.1 Protocol and Data Format
            1. 12.3.6.2.1.1 Protocol
            2. 12.3.6.2.1.2 Data Format
              1. 12.3.6.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.6.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.6.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.6.3 MMCSD Integration
          1. 12.3.6.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.6.4 MMCSD Functional Description
          1. 12.3.6.4.1 Block Diagram
          2. 12.3.6.4.2 Memory Regions
          3. 12.3.6.4.3 Interrupt Requests
          4. 12.3.6.4.4 ECC Support
            1. 12.3.6.4.4.1 ECC Aggregator
          5. 12.3.6.4.5 Advanced DMA
          6. 12.3.6.4.6 eMMC PHY BIST
            1. 12.3.6.4.6.1 BIST Overview
            2. 12.3.6.4.6.2 BIST Modes
              1. 12.3.6.4.6.2.1 DS Mode
              2. 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
              3. 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
              4. 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
              5. 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
              6. 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
              7. 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
              8. 12.3.6.4.6.2.8 HS400 Mode
            3. 12.3.6.4.6.3 BIST Functionality
            4. 12.3.6.4.6.4 Signal Interface
            5. 12.3.6.4.6.5 Programming Flow
              1. 12.3.6.4.6.5.1 DS Mode
                1. 12.3.6.4.6.5.1.1 Configuration
                2. 12.3.6.4.6.5.1.2 BIST Programming
              2. 12.3.6.4.6.5.2 HS Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.2.1 Configuration
                2. 12.3.6.4.6.5.2.2 BIST Programming
              3. 12.3.6.4.6.5.3 HS Mode with DLL
                1. 12.3.6.4.6.5.3.1 Configuration
                2. 12.3.6.4.6.5.3.2 BIST Programming
              4. 12.3.6.4.6.5.4 DDR52 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.4.1 Configuration
                2. 12.3.6.4.6.5.4.2 BIST Programming
              5. 12.3.6.4.6.5.5 DDR52 Mode with DLL
                1. 12.3.6.4.6.5.5.1 Configuration
                2. 12.3.6.4.6.5.5.2 BIST Programming
              6. 12.3.6.4.6.5.6 HS200 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.6.1 Configuration
                2. 12.3.6.4.6.5.6.2 BIST Programming
              7. 12.3.6.4.6.5.7 HS200 Mode with DLL
                1. 12.3.6.4.6.5.7.1 Configuration
                2. 12.3.6.4.6.5.7.2 BIST Programming
              8. 12.3.6.4.6.5.8 HS400 Mode with DLL
                1. 12.3.6.4.6.5.8.1 Configuration
                2. 12.3.6.4.6.5.8.2 BIST Programming
            6. 12.3.6.4.6.6 HS200 BIST Result Check Procedure
        5. 12.3.6.5 MMCSD Programming Guide
          1. 12.3.6.5.1 Sequences
            1. 12.3.6.5.1.1  SD Card Detection
            2. 12.3.6.5.1.2  SD Clock Control
              1. 12.3.6.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.5.1.3  SD Bus Power Control
            4. 12.3.6.5.1.4  Changing Bus Width
            5. 12.3.6.5.1.5  Timeout Setting on DAT Line
            6. 12.3.6.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.5.1.7  SD Transaction Generation
              1. 12.3.6.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.6.5.1.7.1.3 2865
              2. 12.3.6.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.2.1 Not using DMA
                2. 12.3.6.5.1.7.2.2 Using SDMA
                3. 12.3.6.5.1.7.2.3 Using ADMA
            8. 12.3.6.5.1.8  Abort Transaction
              1. 12.3.6.5.1.8.1 Asynchronous Abort
              2. 12.3.6.5.1.8.2 Synchronous Abort
            9. 12.3.6.5.1.9  Changing Bus Speed Mode
            10. 12.3.6.5.1.10 Error Recovery
              1. 12.3.6.5.1.10.1 Error Interrupt Recovery
              2. 12.3.6.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.5.1.11 Wakeup Control (Optional)
            12. 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.5.1.12.1 Suspend Sequence
              2. 12.3.6.5.1.12.2 Resume Sequence
              3. 12.3.6.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.5.2 Driver Flow Sequence
            1. 12.3.6.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.5.2.2 Boot Operation
              1. 12.3.6.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.5.2.3.1 Sampling Clock Tuning
              2. 12.3.6.5.2.3.2 Tuning Modes
              3. 12.3.6.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.5.2.4.2 Task Issuance Sequence
              3. 12.3.6.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.6.6 MMCSD Registers
          1. 12.3.6.6.1 MMCSD0 Subsystem Registers
          2. 12.3.6.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.6.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.6.6.4 MMCSD0 Host Controller Registers
          5. 12.3.6.6.5 MMCSD1 Subsystem Registers
          6. 12.3.6.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.6.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.6.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
        2. 12.4.1.2 ECAP Environment
          1. 12.4.1.2.1 ECAP I/O Interface
        3. 12.4.1.3 ECAP Integration
          1. 12.4.1.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.1.4 ECAP Functional Description
          1. 12.4.1.4.1 Capture and APWM Operating Modes
            1. 12.4.1.4.1.1 ECAP Capture Mode Description
              1. 12.4.1.4.1.1.1 ECAP Event Prescaler
              2. 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.4.1.1.6 ECAP Interrupt Control
              7. 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.4.1.2 ECAP APWM Mode Operation
          2. 12.4.1.4.2 Summary of ECAP Functional Registers
        5. 12.4.1.5 ECAP Use Cases
          1. 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.5.5 Application of the APWM Mode
            1. 12.4.1.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.1.6 ECAP Registers
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Not Supported Features
          3. 12.4.2.1.3 2951
        2. 12.4.2.2 EPWM Environment
          1. 12.4.2.2.1 EPWM I/O Interface
        3. 12.4.2.3 EPWM Integration
          1. 12.4.2.3.1 Device Specific EPWM Features
          2. 12.4.2.3.2 Daisy-Chain Connectivity between EPWM Modules
          3. 12.4.2.3.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
          4. 12.4.2.3.4 EPWM Modules Time Base Clock Gating
        4. 12.4.2.4 EPWM Functional Description
          1. 12.4.2.4.1  EPWM Submodule Features
            1. 12.4.2.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.4.2.1 Overview
            2. 12.4.2.4.2.2 2964
            3. 12.4.2.4.2.3 Controlling and Monitoring the EPWM Time-Base Submodule
            4. 12.4.2.4.2.4 Calculating PWM Period and Frequency
              1. 12.4.2.4.2.4.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.4.2.4.2 EPWM Time-Base Counter Synchronization
            5. 12.4.2.4.2.5 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            6. 12.4.2.4.2.6 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.4.3.1 Overview
            2. 12.4.2.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.4.4.1 Overview
            2. 12.4.2.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.4.5.1 Overview
            2. 12.4.2.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.4.6.1 Overview
            2. 12.4.2.4.6.2 2987
            3. 12.4.2.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.4.7.1 Overview
            2. 12.4.2.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.4.8.1 Overview
            2. 12.4.2.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.4.8.4 3002
          9. 12.4.2.4.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.4.9.1 Overview
            2. 12.4.2.4.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.4.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.4.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.4.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.4.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.4.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.4.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.2.5 EPWM Registers
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Not Supported Features
        2. 12.4.3.2 EQEP Environment
          1. 12.4.3.2.1 EQEP I/O Interface
        3. 12.4.3.3 EQEP Integration
          1. 12.4.3.3.1 Device Specific EQEP Features
        4. 12.4.3.4 EQEP Functional Description
          1. 12.4.3.4.1 EQEP Inputs
          2. 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.4.2.1.1 Quadrature Count Mode
              2. 12.4.3.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.4.2.2 EQEP Input Polarity Selection
            3. 12.4.3.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.4.3.2 EQEP Position Counter Latch
              1. 12.4.3.4.3.2.1 Index Event Latch
              2. 12.4.3.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.4.3.3 EQEP Position Counter Initialization
            4. 12.4.3.4.3.4 EQEP Position-Compare Unit
          4. 12.4.3.4.4 EQEP Edge Capture Unit
          5. 12.4.3.4.5 EQEP Watchdog
          6. 12.4.3.4.6 Unit Timer Base
          7. 12.4.3.4.7 EQEP Interrupt Structure
          8. 12.4.3.4.8 Summary of EQEP Functional Registers
        5. 12.4.3.5 EQEP Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Not Supported Features
        2. 12.4.4.2 MCAN Environment
          1. 12.4.4.2.1 CAN Network Basics
        3. 12.4.4.3 MCAN Integration
          1. 12.4.4.3.1 MCAN Integration in MCU Domain
          2. 12.4.4.3.2 MCAN Integration in MAIN Domain
        4. 12.4.4.4 MCAN Functional Description
          1. 12.4.4.4.1  Module Clocking Requirements
          2. 12.4.4.4.2  Interrupt and DMA Requests
            1. 12.4.4.4.2.1 Interrupt Requests
            2. 12.4.4.4.2.2 DMA Requests
            3. 12.4.4.4.2.3 3064
          3. 12.4.4.4.3  Operating Modes
            1. 12.4.4.4.3.1 Software Initialization
            2. 12.4.4.4.3.2 Normal Operation
            3. 12.4.4.4.3.3 CAN FD Operation
            4. 12.4.4.4.3.4 Transmitter Delay Compensation
              1. 12.4.4.4.3.4.1 Description
              2. 12.4.4.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.4.3.5 Restricted Operation Mode
            6. 12.4.4.4.3.6 Bus Monitoring Mode
            7. 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.4.3.8 Power Down (Sleep Mode)
              1. 12.4.4.4.3.8.1 External Clock Stop Mode
              2. 12.4.4.4.3.8.2 Suspend Mode
              3. 12.4.4.4.3.8.3 Wakeup request
            9. 12.4.4.4.3.9 Test Modes
              1. 12.4.4.4.3.9.1 Internal Loopback Mode
          4. 12.4.4.4.4  Timestamp Generation
            1. 12.4.4.4.4.1 External Timestamp Counter
          5. 12.4.4.4.5  Timeout Counter
          6. 12.4.4.4.6  ECC Support
            1. 12.4.4.4.6.1 ECC Wrapper
            2. 12.4.4.4.6.2 ECC Aggregator
          7. 12.4.4.4.7  Rx Handling
            1. 12.4.4.4.7.1 Acceptance Filtering
              1. 12.4.4.4.7.1.1 Range Filter
              2. 12.4.4.4.7.1.2 Filter for specific IDs
              3. 12.4.4.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.4.7.1.4 Standard Message ID Filtering
              5. 12.4.4.4.7.1.5 Extended Message ID Filtering
            2. 12.4.4.4.7.2 Rx FIFOs
              1. 12.4.4.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.4.7.3 Dedicated Rx Buffers
              1. 12.4.4.4.7.3.1 Rx Buffer Handling
            4. 12.4.4.4.7.4 Debug on CAN Support
          8. 12.4.4.4.8  Tx Handling
            1. 12.4.4.4.8.1 Transmit Pause
            2. 12.4.4.4.8.2 Dedicated Tx Buffers
            3. 12.4.4.4.8.3 Tx FIFO
            4. 12.4.4.4.8.4 Tx Queue
            5. 12.4.4.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.4.8.7 Transmit Cancellation
            8. 12.4.4.4.8.8 Tx Event Handling
          9. 12.4.4.4.9  FIFO Acknowledge Handling
          10. 12.4.4.4.10 Message RAM
            1. 12.4.4.4.10.1 Message RAM Configuration
            2. 12.4.4.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.4.10.3 Tx Buffer Element
            4. 12.4.4.4.10.4 Tx Event FIFO Element
            5. 12.4.4.4.10.5 Standard Message ID Filter Element
            6. 12.4.4.4.10.6 Extended Message ID Filter Element
        5. 12.4.4.5 MCAN Registers
          1. 12.4.4.5.1 MCAN Subsystem Registers
          2. 12.4.4.5.2 MCAN Core Registers
          3. 12.4.4.5.3 MCAN ECC Aggregator Registers
    5. 12.5 Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Not Supported Features
    6. 12.6 Timer Modules
      1. 12.6.1 Global Timebase Counter (GTC)
        1. 12.6.1.1 GTC Overview
          1. 12.6.1.1.1 GTC Features
          2. 12.6.1.1.2 GTC Not Supported Features
        2. 12.6.1.2 GTC Integration
        3. 12.6.1.3 GTC Functional Description
          1. 12.6.1.3.1 GTC Block Diagram
          2. 12.6.1.3.2 GTC Counter
          3. 12.6.1.3.3 GTC Gray Encoder
          4. 12.6.1.3.4 GTC Push Event Generation
          5. 12.6.1.3.5 GTC Register Partitioning
        4. 12.6.1.4 GTC Registers
          1. 12.6.1.4.1 GTC0_GTC_CFG0 Registers
          2. 12.6.1.4.2 GTC0_GTC_CFG1 Registers
          3. 12.6.1.4.3 GTC0_GTC_CFG2 Registers
          4. 12.6.1.4.4 GTC0_GTC_CFG3 Registers
      2. 12.6.2 Windowed Watchdog Timer (WWDT)
        1. 12.6.2.1 RTI Overview
          1. 12.6.2.1.1 RTI Features
          2. 12.6.2.1.2 RTI Not Supported Features
        2. 12.6.2.2 RTI Integration
          1. 12.6.2.2.1 RTI Integration in MCU Domain
          2. 12.6.2.2.2 RTI Integration in MAIN Domain
        3. 12.6.2.3 RTI Functional Description
          1. 12.6.2.3.1 RTI Counter Operation
          2. 12.6.2.3.2 RTI Digital Watchdog
          3. 12.6.2.3.3 RTI Digital Windowed Watchdog
          4. 12.6.2.3.4 RTI Low Power Mode Operation
          5. 12.6.2.3.5 RTI Debug Mode Behavior
        4. 12.6.2.4 RTI Registers
      3. 12.6.3 Timers
        1. 12.6.3.1 Timers Overview
          1. 12.6.3.1.1 Timers Features
          2. 12.6.3.1.2 Timers Not Supported Features
        2. 12.6.3.2 Timers Environment
          1. 12.6.3.2.1 Timer External System Interface
        3. 12.6.3.3 Timers Integration
          1. 12.6.3.3.1 Timers Integration in MCU Domain
          2. 12.6.3.3.2 Timers Integration in MAIN Domain
        4. 12.6.3.4 Timers Functional Description
          1. 12.6.3.4.1  Timer Block Diagram
          2. 12.6.3.4.2  Timer Power Management
            1. 12.6.3.4.2.1 Wake-Up Capability
          3. 12.6.3.4.3  Timer Software Reset
          4. 12.6.3.4.4  Timer Interrupts
          5. 12.6.3.4.5  Timer Mode Functionality
            1. 12.6.3.4.5.1 1-ms Tick Generation
          6. 12.6.3.4.6  Timer Capture Mode Functionality
          7. 12.6.3.4.7  Timer Compare Mode Functionality
          8. 12.6.3.4.8  Timer Prescaler Functionality
          9. 12.6.3.4.9  Timer Pulse-Width Modulation
          10. 12.6.3.4.10 Timer Counting Rate
          11. 12.6.3.4.11 Timer Under Emulation
          12. 12.6.3.4.12 Accessing Timer Registers
            1. 12.6.3.4.12.1 Writing to Timer Registers
              1. 12.6.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.6.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.6.3.4.12.2 Reading From Timer Counter Registers
              1. 12.6.3.4.12.2.1 Read Posted
              2. 12.6.3.4.12.2.2 Read Non-Posted
          13. 12.6.3.4.13 Timer Posted Mode Selection
        5. 12.6.3.5 Timers Low-Level Programming Models
          1. 12.6.3.5.1 Timer Global Initialization
            1. 12.6.3.5.1.1 Global Initialization of Surrounding Modules
            2. 12.6.3.5.1.2 Timer Module Global Initialization
              1. 12.6.3.5.1.2.1 Main Sequence – Timer Module Global Initialization
          2. 12.6.3.5.2 Timer Operational Mode Configuration
            1. 12.6.3.5.2.1 Timer Mode
              1. 12.6.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.6.3.5.2.2 Timer Compare Mode
              1. 12.6.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.6.3.5.2.3 Timer Capture Mode
              1. 12.6.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.6.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.6.3.5.2.3.3 Subsequence – Detect Event
            4. 12.6.3.5.2.4 Timer PWM Mode
              1. 12.6.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.6.3.6 Timers Registers
    7. 12.7 Internal Diagnostics Modules
      1. 12.7.1 Dual Clock Comparator (DCC)
        1. 12.7.1.1 DCC Overview
          1. 12.7.1.1.1 DCC Features
          2. 12.7.1.1.2 DCC Not Supported Features
        2. 12.7.1.2 DCC Integration
          1. 12.7.1.2.1 DCC Integration in MCU Domain
          2. 12.7.1.2.2 DCC Integration in MAIN Domain
        3. 12.7.1.3 DCC Functional Description
          1. 12.7.1.3.1 DCC Counter Operation
          2. 12.7.1.3.2 DCC Low Power Mode Operation
          3. 12.7.1.3.3 DCC Suspend Mode Behavior
          4. 12.7.1.3.4 DCC Single-Shot Mode
          5. 12.7.1.3.5 DCC Continuous mode
            1. 12.7.1.3.5.1 DCC Continue on Error
            2. 12.7.1.3.5.2 DCC Error Count
          6. 12.7.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.7.1.3.7 DCC Error Trajectory record
            1. 12.7.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.7.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.7.1.3.7.3 DCC FIFO Details
            4. 12.7.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.7.1.3.8 DCC Count read registers
        4. 12.7.1.4 DCC Registers
      2. 12.7.2 Error Signaling Module (ESM)
        1. 12.7.2.1 ESM Overview
          1. 12.7.2.1.1 ESM Features
        2. 12.7.2.2 ESM Environment
        3. 12.7.2.3 ESM Integration
          1. 12.7.2.3.1 ESM Integration in WKUP Domain
          2. 12.7.2.3.2 ESM Integration in MCU Domain
          3. 12.7.2.3.3 ESM Integration in MAIN Domain
        4. 12.7.2.4 ESM Functional Description
          1. 12.7.2.4.1 ESM Interrupt Requests
            1. 12.7.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.7.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.7.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.7.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.7.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.7.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.7.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.7.2.4.2 ESM Error Event Inputs
          3. 12.7.2.4.3 ESM Error Pin Output
          4. 12.7.2.4.4 ESM Minimum Time Interval
          5. 12.7.2.4.5 ESM Protection for Registers
          6. 12.7.2.4.6 ESM Clock Stop
        5. 12.7.2.5 ESM Registers
      3. 12.7.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.7.3.1 MCRC Overview
          1. 12.7.3.1.1 MCRC Features
          2. 12.7.3.1.2 MCRC Not Supported Features
        2. 12.7.3.2 MCRC Integration
        3. 12.7.3.3 MCRC Functional Description
          1. 12.7.3.3.1  MCRC Block Diagram
          2. 12.7.3.3.2  MCRC General Operation
          3. 12.7.3.3.3  MCRC Modes of Operation
            1. 12.7.3.3.3.1 AUTO Mode
            2. 12.7.3.3.3.2 Semi-CPU Mode
            3. 12.7.3.3.3.3 Full-CPU Mode
          4. 12.7.3.3.4  PSA Signature Register
          5. 12.7.3.3.5  PSA Sector Signature Register
          6. 12.7.3.3.6  CRC Value Register
          7. 12.7.3.3.7  Raw Data Register
          8. 12.7.3.3.8  Example DMA Controller Setup
            1. 12.7.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.7.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.7.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.7.3.3.9  Pattern Count Register
          10. 12.7.3.3.10 Sector Count Register/Current Sector Register
          11. 12.7.3.3.11 Interrupts
            1. 12.7.3.3.11.1 Compression Complete Interrupt
            2. 12.7.3.3.11.2 CRC Fail Interrupt
            3. 12.7.3.3.11.3 Overrun Interrupt
            4. 12.7.3.3.11.4 Underrun Interrupt
            5. 12.7.3.3.11.5 Timeout Interrupt
            6. 12.7.3.3.11.6 Interrupt Offset Register
            7. 12.7.3.3.11.7 Error Handling
          12. 12.7.3.3.12 Power Down Mode
          13. 12.7.3.3.13 Emulation
        4. 12.7.3.4 MCRC Programming Examples
          1. 12.7.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.7.3.4.1.1 DMA Setup
            2. 12.7.3.4.1.2 Timer Setup
            3. 12.7.3.4.1.3 CRC Setup
          2. 12.7.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.7.3.4.2.1 DMA Setup
            2. 12.7.3.4.2.2 CRC Setup
          3. 12.7.3.4.3 Example: Semi-CPU Mode
            1. 12.7.3.4.3.1 DMA Setup
            2. 12.7.3.4.3.2 Timer Setup
            3. 12.7.3.4.3.3 CRC Setup
          4. 12.7.3.4.4 Example: Full-CPU Mode
            1. 12.7.3.4.4.1 CRC Setup
        5. 12.7.3.5 MCRC Registers
      4. 12.7.4 ECC Aggregator
        1. 12.7.4.1 ECC Aggregator Overview
          1. 12.7.4.1.1 ECC Aggregator Features
        2. 12.7.4.2 ECC Aggregator Integration
        3. 12.7.4.3 ECC Aggregator Functional Description
          1. 12.7.4.3.1 ECC Aggregator Block Diagram
          2. 12.7.4.3.2 ECC Aggregator Register Groups
          3. 12.7.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.7.4.3.4 Serial Write Operation
          5. 12.7.4.3.5 Interrupts
          6. 12.7.4.3.6 Inject Only Mode
        4. 12.7.4.4 ECC Aggregator Registers
  15. 13On-Chip Debug
  16. 14Revision History

5.1.1.4 WKUP_CTRL_MMR0 Registers

Table 5-10 lists the memory-mapped registers for the WKUP_CTRL_MMR0. All register offset addresses not listed in Table 5-10 should be considered as reserved locations and the register contents should not be modified.

Table 5-9 WKUP_CTRL_MMR0 Instances
InstanceBase Address
WKUP_CTRL_MMR0_CFG04300 0000h
Table 5-10 WKUP_CTRL_MMR0 Registers
Offset Acronym Register Name WKUP_CTRL_MMR0_CFG0 Physical Address
0h CTRLMMR_WKUP_PID Peripheral Identification Register 4300 0000h
8h CTRLMMR_WKUP_MMR_CFG1 Configuration register 1 4300 0008h
14h CTRLMMR_WKUP_JTAGID JTAG / DEVICE ID Register 4300 0014h
18h Section 1.1.4.4 JTAG User Code ID Register 4300 0018h
20h CTRLMMR_WKUP_DIE_ID0 Die ID Register 0 4300 0020h
24h CTRLMMR_WKUP_DIE_ID1 Die ID Register 1 4300 0024h
28h CTRLMMR_WKUP_DIE_ID2 Die ID Register 2 4300 0028h
2Ch CTRLMMR_WKUP_DIE_ID3 Die ID Register 3 4300 002Ch
30h CTRLMMR_WKUP_DEVSTAT WKUP Domain Device Status Register 4300 0030h
34h CTRLMMR_WKUP_BOOTCFG WKUP Domain Boot Configuration Register 4300 0034h
38h CTRLMMR_WKUP_POST_SEL_STAT Power-on Self Test Selection Status Register 4300 0038h
3Ch CTRLMMR_WKUP_POST_OPT Power-on Self Test Options Register 4300 003Ch
50h CTRLMMR_WKUP_RESET_SRC_STAT Reset Status Register 4300 0050h
60h CTRLMMR_WKUP_DEVICE_FEATURE0 Device Feature Register 0 4300 0060h
64h CTRLMMR_WKUP_DEVICE_FEATURE1 Device Feature Register 1 4300 0064h
68h CTRLMMR_WKUP_DEVICE_FEATURE2 Device Feature Register 2 4300 0068h
6Ch CTRLMMR_WKUP_DEVICE_FEATURE3 Device Feature Register 3 4300 006Ch
74h CTRLMMR_WKUP_DEVICE_FEATURE5 Device Feature Register 5 4300 0074h
78h CTRLMMR_WKUP_DEVICE_FEATURE6 Device Feature Register 6 4300 0078h
200h CTRLMMR_WKUP_DBG_CBA_ERR_STAT Debug Bus Architecture Error Status 4300 0200h
204h CTRLMMR_WKUP_FW_CBA_ERR_STAT Firewall Bus Architecture Error Status 4300 0204h
208h CTRLMMR_WKUP_NONFW_CBA_ERR_STAT Non-Firewall Bus Architecture Error Status 4300 0208h
210h CTRLMMR_WKUP_MAIN_CBA_ERR_STAT Main Bus Architecture Error Status 4300 0210h
1008h CTRLMMR_WKUP_LOCK0_KICK0 Partition 0 Lock Key 0 Register 4300 1008h
100Ch CTRLMMR_WKUP_LOCK0_KICK1 Partition 0 Lock Key 1 Register 4300 100Ch
1010h CTRLMMR_WKUP_INTR_RAW_STAT Interrupt Raw Status Register 4300 1010h
1014h CTRLMMR_WKUP_INTR_STAT_CLR Interrupt Status and Clear Register 4300 1014h
1018h CTRLMMR_WKUP_INTR_EN_SET Interrupt Enable Set Register 4300 1018h
101Ch CTRLMMR_WKUP_INTR_EN_CLR Interrupt Enable Clear Register 4300 101Ch
1020h CTRLMMR_WKUP_EOI End of Interrupt Register 4300 1020h
1024h CTRLMMR_WKUP_FAULT_ADDR Fault Address Register 4300 1024h
1028h CTRLMMR_WKUP_FAULT_TYPE Fault Type Register 4300 1028h
102Ch CTRLMMR_WKUP_FAULT_ATTR Fault Attribute Register 4300 102Ch
1030h CTRLMMR_WKUP_FAULT_CLR Fault Clear Register 4300 1030h
4004h CTRLMMR_WKUP_MAIN_PWR_CTRL MAIN Voltage Domain Power Control Register 4300 4004h
4008h CTRLMMR_WKUP_MCU_PWR_CTRL MCU Voltage Domain Power Control Register 4300 4008h
4020h CTRLMMR_WKUP_GPIO_CTRL WKUP GPIO Control Register 4300 4020h
4030h CTRLMMR_WKUP_I2C0_CTRL WKUP I2C0 Control Register 4300 4030h
4084h CTRLMMR_WKUP_DBOUNCE_CFG1 Debounce Config Register 4300 4084h
4088h CTRLMMR_WKUP_DBOUNCE_CFG2 Debounce Config Register 4300 4088h
408Ch CTRLMMR_WKUP_DBOUNCE_CFG3 Debounce Config Register 4300 408Ch
4090h CTRLMMR_WKUP_DBOUNCE_CFG4 Debounce Config Register 4300 4090h
4094h CTRLMMR_WKUP_DBOUNCE_CFG5 Debounce Config Register 4300 4094h
4098h CTRLMMR_WKUP_DBOUNCE_CFG6 Debounce Config Register 4300 4098h
5008h CTRLMMR_WKUP_LOCK1_KICK0 Partition 1 Lock Key 0 Register 4300 5008h
500Ch CTRLMMR_WKUP_LOCK1_KICK1 Partition 1 Lock Key 1 Register 4300 500Ch
8000h CTRLMMR_WKUP_MCU_OBSCLK_CTRL Observe Clock Output Control Register 4300 8000h
8014h CTRLMMR_WKUP_HFOSC1_CTRL Oscillator1 Control Register 4300 8014h
8018h CTRLMMR_WKUP_HFOSC0_TRIM Oscillator0 Trim Register 4300 8018h
801Ch CTRLMMR_WKUP_HFOSC1_TRIM Oscillator1 Trim Register 4300 801Ch
8024h CTRLMMR_WKUP_RC12M_OSC_TRIM 12.5 MHz RC Oscillator Trim Register 4300 8024h
8050h CTRLMMR_WKUP_MCU_PLL_CLKSEL MCU PLL Source Clock Select Register 4300 8050h
8060h CTRLMMR_WKUP_PER_CLKSEL WKUP Peripheral Clock Select Register 4300 8060h
8064h CTRLMMR_WKUP_USART_CLKSEL WKUP USART Clock Select Register 4300 8064h
8070h CTRLMMR_WKUP_GPIO_CLKSEL WKUP GPIO Clock Select Register 4300 8070h
8080h CTRLMMR_WKUP_MAIN_PLL0_CLKSEL MAIN PLL0 Source Clock Select Register 4300 8080h
8084h CTRLMMR_WKUP_MAIN_PLL1_CLKSEL MAIN PLL1 Source Clock Select Register 4300 8084h
8088h CTRLMMR_WKUP_MAIN_PLL2_CLKSEL MAIN PLL2 Source Clock Select Register 4300 8088h
808Ch CTRLMMR_WKUP_MAIN_PLL3_CLKSEL MAIN PLL3 Source Clock Select Register 4300 808Ch
8090h CTRLMMR_WKUP_MAIN_PLL4_CLKSEL MAIN PLL4 Source Clock Select Register 4300 8090h
809Ch CTRLMMR_WKUP_MAIN_PLL7_CLKSEL MAIN PLL7 Source Clock Select Register 4300 809Ch
80A0h CTRLMMR_WKUP_MAIN_PLL8_CLKSEL MAIN PLL8 Source Clock Select Register 4300 80A0h
80B0h CTRLMMR_WKUP_MAIN_PLL12_CLKSEL MAIN PLL12 Source Clock Select Register 4300 80B0h
80B8h CTRLMMR_WKUP_MAIN_PLL14_CLKSEL MAIN PLL14 Source Clock Select Register 4300 80B8h
8100h CTRLMMR_WKUP_MAIN_SYSCLK_CTRL MAIN System Clock Control Register 4300 8100h
8110h CTRLMMR_WKUP_MCU_SPI0_CLKSEL MCU_SPI Clock Select Register 4300 8110h
8114h CTRLMMR_WKUP_MCU_SPI1_CLKSEL MCU_SPI Clock Select Register 4300 8114h
9008h CTRLMMR_WKUP_LOCK2_KICK0 Partition 2 Lock Key 0 Register 4300 9008h
900Ch CTRLMMR_WKUP_LOCK2_KICK1 Partition 2 Lock Key 1 Register 4300 900Ch
C280h CTRLMMR_WKUP_DMSC_LBIST_SIG DMSC Logic BIST MISR Signature Register 4300 C280h
C2C0h CTRLMMR_WKUP_POST_STAT WKUP Power-On Self Test Status Register 4300 C2C0h
C320h CTRLMMR_WKUP_FUSE_CRC_STAT WKUP eFuse CRC Status Register 4300 C320h
D008h CTRLMMR_WKUP_LOCK3_KICK0 Partition 3 Lock Key 0 Register 4300 D008h
D00Ch CTRLMMR_WKUP_LOCK3_KICK1 Partition 3 Lock Key 1 Register 4300 D00Ch
11008h CTRLMMR_WKUP_LOCK4_KICK0 Partition 4 Lock Key 0 Register 4301 1008h
1100Ch CTRLMMR_WKUP_LOCK4_KICK1 Partition 4 Lock Key 1 Register 4301 100Ch
18000h CTRLMMR_WKUP_POR_CTRL Power-On Reset Module Control Register 4301 8000h
18004h CTRLMMR_WKUP_POR_STAT Power-On Reset Module Status Register 4301 8004h
18010h CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL VDDA_PMIC_IN Power-OK Control Register 4301 8010h
18014h CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL 3P3_VDDA_MCU Undervoltage Power-OK Control Register 4301 8014h
18018h CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL VDDR_MCU Undervoltage Power-OK Control Register 4301 8018h
1801Ch CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_UV_CTRL VMON_CAP_MCU_GENERAL Undervoltage Power-OK Control Register 4301 801Ch
18020h CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL VDD_MCU Overvoltage Power-OK Control Register 4301 8020h
18024h CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL 3P3_VDDA_MCU Overvoltage Power-OK Control Register 4301 8024h
18028h CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL VDDR_MCU Overvoltage Power-OK Control Register 4301 8028h
1802Ch CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_OV_CTRL VMON_CAP_MCU_GENERAL Overvoltage Power-OK Control Register 4301 802Ch
18070h CTRLMMR_WKUP_MAIN_VDOM_CTRL MAIN Voltage Domain Control Register 4301 8070h
18080h CTRLMMR_WKUP_POR_POKHV_UV_CTRL 1.8V VDDA_MCU undervoltage POK Control Register 4301 8080h
18084h CTRLMMR_WKUP_POR_POKLVB_UV_CTRL VDD_MCU undervoltage POK Control Register 4301 8084h
18088h CTRLMMR_WKUP_POR_POKLVA_OV_CTRL 1.8V VDDA_MCU overvoltage POK Control Register 4301 8088h
1808Ch CTRLMMR_WKUP_POR_BANDGAP_CTRL Bandgap Control Register 4301 808Ch
180A0h CTRLMMR_WKUP_TEMP_DIODE_TRIM Temperature Diode Trim Register 4301 80A0h
180B0h CTRLMMR_WKUP_IO_VOLTAGE_STAT I/O Voltage Status Register 4301 80B0h
18104h CTRLMMR_WKUP_MAIN_POR_TO_CTRL MAIN PORz Reset Timeout Register 4301 8104h
18110h CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL VDD_CORE Undervoltage Power-OK Control Register 4301 8110h
18114h CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL VDD_CPU Undervoltage Power-OK Control Register 4301 8114h
18118h CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL 1P8_VDDA_SOC Undervoltage Power-OK Control Register 4301 8118h
1811Ch CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL VDDR_CORE Undervoltage Power-OK Control Register 4301 811Ch
18120h CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL VDD_CORE Overvoltage Power-OK Control Register 4301 8120h
18124h CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL VDD_CPU Overvoltage Power-OK Control Register 4301 8124h
18128h CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL 1P8_VDDA_SOC Overvoltage Power-OK Control Register 4301 8128h
1812Ch CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL VDDR_CORE Overvoltage Power-OK Control Register 4301 812Ch
18130h CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_UV_CTRL VMON_EXT_MAIN_1P8 Undervoltage Power-OK Control Register 4301 8130h
18134h CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_OV_CTRL VMON_EXT_MAIN_1P8 Overvoltage Power-OK Control Register 4301 8134h
18138h CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_UV_CTRL VMON_EXT_MAIN_3P3 Undervoltage Power-OK Control Register 4301 8138h
1813Ch CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_OV_CTRL VMON_EXT_MAIN_3P3 Overvoltage Power-OK Control Register 4301 813Ch
18160h CTRLMMR_WKUP_DEEPSLEEP_CTRL Deep Sleep Control Register 4301 8160h
18170h CTRLMMR_WKUP_POR_RST_CTRL PowerOn Reset Control Register 4301 8170h
18174h CTRLMMR_WKUP_MAIN_WARM_RST_CTRL MAIN Domain Warm Reset Control Register 4301 8174h
18178h CTRLMMR_WKUP_RST_STAT Reset Status Register 4301 8178h
1817Ch CTRLMMR_WKUP_MCU_WARM_RST_CTRL MCU Domain Warm Reset Control Register 4301 817Ch
18180h CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL CPU Voltage Glitch Detect Control Register 4301 8180h
18190h CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL Core Voltage Glitch Detect Control Register 4301 8190h
18194h CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL CPU SRAM Voltage Glitch Detect Control Register 4301 8194h
18198h CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL Core SRAM Voltage Glitch Detect Control Register 4301 8198h
181A0h CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT CPU Voltage Glitch Detect Status Register 4301 81A0h
181B0h CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT Core Voltage Core Glitch Detect Status Register 4301 81B0h
181B4h CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT CPU SRAM Voltage Glitch Detect Status Register 4301 81B4h
181B8h CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT Core SRAM Voltage Glitch Detect Status Register 4301 81B8h
181C0h CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL MCU Voltage Glitch Detect Control Register 4301 81C0h
181C4h CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL MCU SRAM Glitch Detect Control Register 4301 81C4h
181D0h CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT MCU Voltage Glitch Detect Status Register 4301 81D0h
181D4h CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT MCU SRAM Glitch Detect Status Register 4301 81D4h
18200h CTRLMMR_WKUP_PRG_PP_MCU_CTRL MCU PRG_PP Control Register 4301 8200h
18204h CTRLMMR_WKUP_PRG_PP_MCU_STAT MCU PRG_PP Status and Clear Register 4301 8204h
18208h CTRLMMR_WKUP_PRG_PP_POR_CTRL POR PRG_PP Control Register 4301 8208h
1820Ch CTRLMMR_WKUP_PRG_PP_POR_STAT POR PRG_PP Status and Clear Register 4301 820Ch
18210h CTRLMMR_WKUP_PRG_PP_MAIN_CTRL MAIN PRG_PP Control Register 4301 8210h
18214h CTRLMMR_WKUP_PRG_PP_MAIN_STAT MAIN PRG_PP Status and Clear Register 4301 8214h
18280h CTRLMMR_WKUP_CLKGATE_CTRL WKUP Automatic Clock Gating Control Register 4301 8280h
18284h CTRLMMR_WKUP_MCU_CLKGATE_CTRL MCU Automatic Clock Gating Control Register 4301 8284h
18288h CTRLMMR_WKUP_MAIN_CLKGATE_CTRL0 MAIN Automatic Clock Gating Control Register 4301 8288h
1828Ch CTRLMMR_WKUP_MAIN_CLKGATE_CTRL1 MAIN Automatic Clock Gating Control Register 4301 828Ch
18300h CTRLMMR_WKUP_CANUART_WAKE_CTRL CANUART IO Domain Daisy-Chain Wakeup Control Register 4301 8300h
18308h CTRLMMR_WKUP_CANUART_WAKE_STAT0 CANUART IO Domain Daisy-Chain Wakeup Status Register 0 4301 8308h
1830Ch CTRLMMR_WKUP_CANUART_WAKE_STAT1 CANUART IO Domain Daisy-Chain Wakeup Status Register 1 4301 830Ch
18310h CTRLMMR_WKUP_MCU_GEN_WAKE_CTRL MCU_GENERAL IO Domain Daisy-Chain Wakeup Control Register 4301 8310h
18318h CTRLMMR_WKUP_MCU_GEN_WAKE_STAT0 MCU_GENERAL IO Domain Daisy-Chain Wakeup Status Register 0 4301 8318h
1831Ch CTRLMMR_WKUP_MCU_GEN_WAKE_STAT1 MCU_GENERAL IO Domain Daisy-Chain Wakeup Status Register 1 4301 831Ch
19008h CTRLMMR_WKUP_LOCK6_KICK0 Partition 6 Lock Key 0 Register 4301 9008h
1900Ch CTRLMMR_WKUP_LOCK6_KICK1 Partition 6 Lock Key 1 Register 4301 900Ch
1C000h CTRLMMR_WKUP_PADCONFIG0 PAD Configuration Register 0 4301 C000h
1C004h CTRLMMR_WKUP_PADCONFIG1 PAD Configuration Register 1 4301 C004h
1C008h CTRLMMR_WKUP_PADCONFIG2 PAD Configuration Register 2 4301 C008h
1C00Ch CTRLMMR_WKUP_PADCONFIG3 PAD Configuration Register 3 4301 C00Ch
1C010h CTRLMMR_WKUP_PADCONFIG4 PAD Configuration Register 4 4301 C010h
1C014h CTRLMMR_WKUP_PADCONFIG5 PAD Configuration Register 5 4301 C014h
1C018h CTRLMMR_WKUP_PADCONFIG6 PAD Configuration Register 6 4301 C018h
1C01Ch CTRLMMR_WKUP_PADCONFIG7 PAD Configuration Register 7 4301 C01Ch
1C020h CTRLMMR_WKUP_PADCONFIG8 PAD Configuration Register 8 4301 C020h
1C024h CTRLMMR_WKUP_PADCONFIG9 PAD Configuration Register 9 4301 C024h
1C028h CTRLMMR_WKUP_PADCONFIG10 PAD Configuration Register 10 4301 C028h
1C02Ch CTRLMMR_WKUP_PADCONFIG11 PAD Configuration Register 11 4301 C02Ch
1C030h CTRLMMR_WKUP_PADCONFIG12 PAD Configuration Register 12 4301 C030h
1C038h CTRLMMR_WKUP_PADCONFIG14 PAD Configuration Register 14 4301 C038h
1C03Ch CTRLMMR_WKUP_PADCONFIG15 PAD Configuration Register 15 4301 C03Ch
1C068h CTRLMMR_WKUP_PADCONFIG26 PAD Configuration Register 26 4301 C068h
1C06Ch CTRLMMR_WKUP_PADCONFIG27 PAD Configuration Register 27 4301 C06Ch
1C070h CTRLMMR_WKUP_PADCONFIG28 PAD Configuration Register 28 4301 C070h
1C074h CTRLMMR_WKUP_PADCONFIG29 PAD Configuration Register 29 4301 C074h
1C078h CTRLMMR_WKUP_PADCONFIG30 PAD Configuration Register 30 4301 C078h
1C07Ch CTRLMMR_WKUP_PADCONFIG31 PAD Configuration Register 31 4301 C07Ch
1C080h CTRLMMR_WKUP_PADCONFIG32 PAD Configuration Register 32 4301 C080h
1C084h CTRLMMR_WKUP_PADCONFIG33 PAD Configuration Register 33 4301 C084h
1C088h CTRLMMR_WKUP_PADCONFIG34 PAD Configuration Register 34 4301 C088h
1C08Ch CTRLMMR_WKUP_PADCONFIG35 PAD Configuration Register 35 4301 C08Ch
1C090h CTRLMMR_WKUP_PADCONFIG36 PAD Configuration Register 36 4301 C090h
1C094h CTRLMMR_WKUP_PADCONFIG37 PAD Configuration Register 37 4301 C094h
1C098h CTRLMMR_WKUP_PADCONFIG38 PAD Configuration Register 38 4301 C098h
1C09Ch CTRLMMR_WKUP_PADCONFIG39 PAD Configuration Register 39 4301 C09Ch
1C0A0h CTRLMMR_WKUP_PADCONFIG40 PAD Configuration Register 40 4301 C0A0h
1C0A4h CTRLMMR_WKUP_PADCONFIG41 PAD Configuration Register 41 4301 C0A4h
1C0A8h CTRLMMR_WKUP_PADCONFIG42 PAD Configuration Register 42 4301 C0A8h
1C0ACh CTRLMMR_WKUP_PADCONFIG43 PAD Configuration Register 43 4301 C0ACh
1C0B0h CTRLMMR_WKUP_PADCONFIG44 PAD Configuration Register 44 4301 C0B0h
1C0B4h CTRLMMR_WKUP_PADCONFIG45 PAD Configuration Register 45 4301 C0B4h
1C0B8h CTRLMMR_WKUP_PADCONFIG46 PAD Configuration Register 46 4301 C0B8h
1C0BCh CTRLMMR_WKUP_PADCONFIG47 PAD Configuration Register 47 4301 C0BCh
1C0C0h CTRLMMR_WKUP_PADCONFIG48 PAD Configuration Register 48 4301 C0C0h
1C0C4h CTRLMMR_WKUP_PADCONFIG49 PAD Configuration Register 49 4301 C0C4h
1C0C8h CTRLMMR_WKUP_PADCONFIG50 PAD Configuration Register 50 4301 C0C8h
1C0CCh CTRLMMR_WKUP_PADCONFIG51 PAD Configuration Register 51 4301 C0CCh
1C0D0h CTRLMMR_WKUP_PADCONFIG52 PAD Configuration Register 52 4301 C0D0h
1C0D4h CTRLMMR_WKUP_PADCONFIG53 PAD Configuration Register 53 4301 C0D4h
1C0D8h CTRLMMR_WKUP_PADCONFIG54 PAD Configuration Register 54 4301 C0D8h
1C0DCh CTRLMMR_WKUP_PADCONFIG55 PAD Configuration Register 55 4301 C0DCh
1C0E0h CTRLMMR_WKUP_PADCONFIG56 PAD Configuration Register 56 4301 C0E0h
1C0E4h CTRLMMR_WKUP_PADCONFIG57 PAD Configuration Register 57 4301 C0E4h
1C0E8h CTRLMMR_WKUP_PADCONFIG58 PAD Configuration Register 58 4301 C0E8h
1C0ECh CTRLMMR_WKUP_PADCONFIG59 PAD Configuration Register 59 4301 C0ECh
1C0F0h CTRLMMR_WKUP_PADCONFIG60 PAD Configuration Register 60 4301 C0F0h
1C0F4h CTRLMMR_WKUP_PADCONFIG61 PAD Configuration Register 61 4301 C0F4h
1C0F8h CTRLMMR_WKUP_PADCONFIG62 PAD Configuration Register 62 4301 C0F8h
1C0FCh CTRLMMR_WKUP_PADCONFIG63 PAD Configuration Register 63 4301 C0FCh
1C100h CTRLMMR_WKUP_PADCONFIG64 PAD Configuration Register 64 4301 C100h
1C104h CTRLMMR_WKUP_PADCONFIG65 PAD Configuration Register 65 4301 C104h
1C108h CTRLMMR_WKUP_PADCONFIG66 PAD Configuration Register 66 4301 C108h
1C10Ch CTRLMMR_WKUP_PADCONFIG67 PAD Configuration Register 67 4301 C10Ch
1C110h CTRLMMR_WKUP_PADCONFIG68 PAD Configuration Register 68 4301 C110h
1C114h CTRLMMR_WKUP_PADCONFIG69 PAD Configuration Register 69 4301 C114h
1C118h CTRLMMR_WKUP_PADCONFIG70 PAD Configuration Register 70 4301 C118h
1C11Ch CTRLMMR_WKUP_PADCONFIG71 PAD Configuration Register 71 4301 C11Ch
1C120h CTRLMMR_WKUP_PADCONFIG72 PAD Configuration Register 72 4301 C120h
1C124h CTRLMMR_WKUP_PADCONFIG73 PAD Configuration Register 73 4301 C124h
1C128h CTRLMMR_WKUP_PADCONFIG74 PAD Configuration Register 74 4301 C128h
1C12Ch CTRLMMR_WKUP_PADCONFIG75 PAD Configuration Register 75 4301 C12Ch
1C130h CTRLMMR_WKUP_PADCONFIG76 PAD Configuration Register 76 4301 C130h
1C134h CTRLMMR_WKUP_PADCONFIG77 PAD Configuration Register 77 4301 C134h
1C138h CTRLMMR_WKUP_PADCONFIG78 PAD Configuration Register 78 4301 C138h
1C13Ch CTRLMMR_WKUP_PADCONFIG79 PAD Configuration Register 79 4301 C13Ch
1C140h CTRLMMR_WKUP_PADCONFIG80 PAD Configuration Register 80 4301 C140h
1C144h CTRLMMR_WKUP_PADCONFIG81 PAD Configuration Register 81 4301 C144h
1C148h CTRLMMR_WKUP_PADCONFIG82 PAD Configuration Register 82 4301 C148h
1C14Ch CTRLMMR_WKUP_PADCONFIG83 PAD Configuration Register 83 4301 C14Ch
1C150h CTRLMMR_WKUP_PADCONFIG84 PAD Configuration Register 84 4301 C150h
1C174h CTRLMMR_WKUP_PADCONFIG93 PAD Configuration Register 93 4301 C174h
1C178h CTRLMMR_WKUP_PADCONFIG94 PAD Configuration Register 94 4301 C178h
1C17Ch CTRLMMR_WKUP_PADCONFIG95 PAD Configuration Register 95 4301 C17Ch
1C180h CTRLMMR_WKUP_PADCONFIG96 PAD Configuration Register 96 4301 C180h
1C184h CTRLMMR_WKUP_PADCONFIG97 PAD Configuration Register 97 4301 C184h
1C188h CTRLMMR_WKUP_PADCONFIG98 PAD Configuration Register 98 4301 C188h
1C18Ch CTRLMMR_WKUP_PADCONFIG99 PAD Configuration Register 99 4301 C18Ch
1C190h CTRLMMR_WKUP_PADCONFIG100 PAD Configuration Register 100 4301 C190h
1D008h CTRLMMR_WKUP_LOCK7_KICK0 Partition 7 Lock Key 0 Register 4301 D008h
1D00Ch CTRLMMR_WKUP_LOCK7_KICK1 Partition 7 Lock Key 1 Register 4301 D00Ch

1.1.4.1 CTRLMMR_WKUP_PID Register ( Offset = 0h) [reset = 61800800h]

CTRLMMR_WKUP_PID is shown in Figure 5-2 and described in Table 5-12.

Return to Summary Table.

Peripheral release details.

Table 5-11 CTRLMMR_WKUP_PID Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0000h
Figure 5-2 CTRLMMR_WKUP_PID Register
3130292827262524
SCHEMEBUFUNC
R-1hR-2hR-180h
2322212019181716
FUNC
R-180h
15141312111098
R_RTLX_MAJOR
R-1hR-0h
76543210
CUSTOMY_MINOR
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-12 CTRLMMR_WKUP_PID Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMER1h

CTRLMMR_WKUP_PID follows new scheme

29-28BUR2h

Business unit - Processors

27-16FUNCR180h

Module functional identifier - CTRL MMR

15-11R_RTLR1h

RTL revision number - actual value determined by RTL

10-8X_MAJORR0h

Major revision number - actual value determined by RTL

7-6CUSTOMR0h

Custom revision number - actual value determined by RTL

5-0Y_MINORR0h

Minor revision number - actual value determined by RTL

1.1.4.2 CTRLMMR_WKUP_MMR_CFG1 Register ( Offset = 8h) [reset = 800000DFh]

CTRLMMR_WKUP_MMR_CFG1 is shown in Figure 5-3 and described in Table 5-14.

Return to Summary Table.

Indicates the MMR configuration.

Table 5-13 CTRLMMR_WKUP_MMR_CFG1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0008h
Figure 5-3 CTRLMMR_WKUP_MMR_CFG1 Register
3130292827262524
RESERVEDRESERVED
R-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
PARTITIONS
R-DFh
LEGEND: R = Read Only; -n = value after reset
Table 5-14 CTRLMMR_WKUP_MMR_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR1h

Reserved

30-8RESERVEDR0h

Reserved

7-0PARTITIONSRDFh

Indicates present partitions

1.1.4.3 CTRLMMR_WKUP_JTAGID Register ( Offset = 14h) [reset = BB6D02Fh]

CTRLMMR_WKUP_JTAGID is shown in Figure 5-4 and described in Table 5-16.

Return to Summary Table.

The CTRLMMR_WKUP_JTAGID register must be readable by the configuration bus so that this can be accessed via the JTAG and CPU. In Boundary Scan mode, this ID should also be readable with only TCLK present. This means without a valid CPU clock running and also implies that Fusefarm scan is not necessary. The partno and variant field inputs should be set in the top metal mask so that this may be changed if a future PG is necessary. All other fields may be hard coded.

Table 5-15 CTRLMMR_WKUP_JTAGID Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0014h
Figure 5-4 CTRLMMR_WKUP_JTAGID Register
3130292827262524
VARIANTPARTNO
R-0hR-BB6Dh
2322212019181716
PARTNO
R-BB6Dh
15141312111098
PARTNOMFG
R-BB6DhR-17h
76543210
MFGLSB
R-17hR-1h
LEGEND: R = Read Only; -n = value after reset
Table 5-16 CTRLMMR_WKUP_JTAGID Register Field Descriptions
BitFieldTypeResetDescription
31-28VARIANTR0h

Silicon Revision identifier

27-12PARTNORBB6Dh

Part number for boundary scan

11-1MFGR17h

Indicates manufacturer

0LSBR1h

Always 1

1.1.4.4 CTRLMMR_WKUP_JTAG_USER_ID Register ( Offset = 18h) [reset = BB6402Fh]

Return to Summary Table.

This register must be readable by the configuration bus so that this can be accessed via the JTAG and CPU. In Boundary Scan mode, this ID should also be readable with only TCLK present. This means without a valid CPU clock running and also implies that Fusefarm scan is not necessary. The Variant field should be set in the top metal mask so that this may be changed if a future PG is necessary. All other fields may be hard coded.

Table 5-17 CTRLMMR_WKUP_JTAG_USER_ID Instances
Instance Physical Address
WKUP_CTRL_MMR0 4300 0018h
Figure 5-5 CTRLMMR_WKUP_JTAG_USER_ID Register
31 30 29 28 27 26 25 24
DEVICE_ID
R-0h
23 22 21 20 19 18 17 16
DEVICE_ID
R-0h
15 14 13 12 11 10 9 8
RESERVED REV RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-18 CTRLMMR_WKUP_JTAG_USER_ID Register Field Descriptions
Bit Field Type Reset Description
31-16 DEVICE_ID R 0h

Base part number

See device comparison table in the device-specific data sheet for details.
15-0 Reserved

1.1.4.5 CTRLMMR_WKUP_DIE_ID0 Register ( Offset = 20h) [reset = X]

CTRLMMR_WKUP_DIE_ID0 is shown in Figure 5-6 and described in Table 5-20.

Return to Summary Table.

Contains information to identify this particular die.

Table 5-19 CTRLMMR_WKUP_DIE_ID0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0020h
Figure 5-6 CTRLMMR_WKUP_DIE_ID0 Register
313029282726252423222120191817161514131211109876543210
DIEID
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-20 CTRLMMR_WKUP_DIE_ID0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DIEIDRX

Contains individual die information

1.1.4.6 CTRLMMR_WKUP_DIE_ID1 Register ( Offset = 24h) [reset = X]

CTRLMMR_WKUP_DIE_ID1 is shown in Figure 5-7 and described in Table 5-22.

Return to Summary Table.

Contains information to identify this particular die.

Table 5-21 CTRLMMR_WKUP_DIE_ID1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0024h
Figure 5-7 CTRLMMR_WKUP_DIE_ID1 Register
313029282726252423222120191817161514131211109876543210
DIEID
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-22 CTRLMMR_WKUP_DIE_ID1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DIEIDRX

Contains individual die information

1.1.4.7 CTRLMMR_WKUP_DIE_ID2 Register ( Offset = 28h) [reset = X]

CTRLMMR_WKUP_DIE_ID2 is shown in Figure 5-8 and described in Table 5-24.

Return to Summary Table.

Contains information to identify this particular die.

Table 5-23 CTRLMMR_WKUP_DIE_ID2 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0028h
Figure 5-8 CTRLMMR_WKUP_DIE_ID2 Register
313029282726252423222120191817161514131211109876543210
DIEID
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-24 CTRLMMR_WKUP_DIE_ID2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DIEIDRX

Contains individual die information

1.1.4.8 CTRLMMR_WKUP_DIE_ID3 Register ( Offset = 2Ch) [reset = X]

CTRLMMR_WKUP_DIE_ID3 is shown in Figure 5-9 and described in Table 5-26.

Return to Summary Table.

Contains information to identify this particular die.

Table 5-25 CTRLMMR_WKUP_DIE_ID3 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 002Ch
Figure 5-9 CTRLMMR_WKUP_DIE_ID3 Register
313029282726252423222120191817161514131211109876543210
DIEID
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-26 CTRLMMR_WKUP_DIE_ID3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DIEIDRX

Contains individual die information

1.1.4.9 CTRLMMR_WKUP_DEVSTAT Register ( Offset = 30h) [reset = X]

CTRLMMR_WKUP_DEVSTAT is shown in Figure 5-10 and described in Table 5-28.

Return to Summary Table.

Indicates Device bootstrap selection. The default value of this register is determined by the bootstrap pins when the por_boot_cfg_srst_n input is de-asserted.

Table 5-27 CTRLMMR_WKUP_DEVSTAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0030h
Figure 5-10 CTRLMMR_WKUP_DEVSTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
MAIN_BOOTMODE
R/W-X
15141312111098
RESERVEDMCU_BOOTMODE
R-0hR/W-X
76543210
MCU_BOOTMODE
R/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-28 CTRLMMR_WKUP_DEVSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23-16MAIN_BOOTMODER/WX

Specifies the device Primary and Backup boot media.
Bit assignments defined by ROM

15-10RESERVEDR0h

Reserved

9-0MCU_BOOTMODER/WX

Indicates MCU boot mode.
Bits 9:8 - Power-on Self Test mode (if CTRLMMR_WKUP_POST_SEL_STAT = 0x0)
0h - POST mode 1 (See POST_OPT_opt1_xxx bitfields)
1h - POST mode 2 (See POST_OPT_opt2_xxx bitfields)
2h - POST mode 3 (See POST_OPT_opt3_xxx bitfields)
3h - Bypass POST
Bits 7:3 - MCU primary and secondary boot source
Bits 2:0 - HFOSC0 frequency selection
0h - 19.2 MHz
1h - 20.0 MHz
2h - 24.0 MHz
3h - 25.0 MHz
4h - 26.0 MHz
5h - 27.0 MHz
6h - Reserved for device test
7h - No PLL configuration

1.1.4.10 CTRLMMR_WKUP_BOOTCFG Register ( Offset = 34h) [reset = X]

CTRLMMR_WKUP_BOOTCFG is shown in Figure 5-11 and described in Table 5-30.

Return to Summary Table.

Indicates Device bootstrap selection latched at power-on reset by MCU_PORz. The default value of this register is determined by the bootstrap pins when the por_boot_cfg_srst_n input is de-asserted and will remain until the bootstrap pins are re-latched on a subsequent por_boot_cfg_srst_n rising edge.

Table 5-29 CTRLMMR_WKUP_BOOTCFG Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0034h
Figure 5-11 CTRLMMR_WKUP_BOOTCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
MAIN_BOOTMODE
R-X
15141312111098
RESERVEDMCU_BOOTMODE
R-0hR-X
76543210
MCU_BOOTMODE
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-30 CTRLMMR_WKUP_BOOTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23-16MAIN_BOOTMODERX

Specifies the device Primary and Backup boot media as latched at PORz
Bit assignments assigned by ROM

15-10RESERVEDR0h

Reserved

9-0MCU_BOOTMODERX

Indicates MCU boot mode as latched at power-on reset. These bits always contain the values latched.

Bits 9:8 - Power-on Self Test mode (if CTRLMMR_WKUP_POST_SEL_STAT = 0x0)
0h - POST mode 1 (See POST_OPT_opt1_xxx bitfields)
1h - POST mode 2 (See POST_OPT_opt2_xxx bitfields)
2h - POST mode 3 (See POST_OPT_opt3_xxx bitfields)
3h - Bypass POST
Bits 7:3 - MCU primary and secondary boot source
Bits 2:0 - HFOSC0 frequency selection
0h - 19.2 MHz
1h - 20.0 MHz
2h - 24.0 MHz
3h - 25.0 MHz
4h - 26.0 MHz
5h - 27.0 MHz
6h - Reserved for device test
7h - No PLL configuration

1.1.4.11 CTRLMMR_WKUP_POST_SEL_STAT Register ( Offset = 38h) [reset = X]

CTRLMMR_WKUP_POST_SEL_STAT is shown in Figure 5-12 and described in Table 5-32.

Return to Summary Table.

Indicates which power-on self test option was performed.

Table 5-31 CTRLMMR_WKUP_POST_SEL_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0038h
Figure 5-12 CTRLMMR_WKUP_POST_SEL_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPOST_SEL_STAT
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-32 CTRLMMR_WKUP_POST_SEL_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0POST_SEL_STATRX

Indicates which POST option was selected at power-up

1.1.4.12 CTRLMMR_WKUP_POST_OPT Register ( Offset = 3Ch) [reset = X]

CTRLMMR_WKUP_POST_OPT is shown in Figure 5-13 and described in Table 5-34.

Return to Summary Table.

Indicates the 3 available power-on self test (POST) options Bits 3:0 - POST Option 1 Bits 11:8 - POST Option 2 Bits 19:16 - POST Option 3.

Table 5-33 CTRLMMR_WKUP_POST_OPT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 003Ch
Figure 5-13 CTRLMMR_WKUP_POST_OPT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDOPT3_MCU_PBIST_ENOPT3_MCU_LBIST_ENOPT3_DMSC_LBIST_ENOPT3_PARALLEL_EN
R-0hR-XR-XR-XR-X
15141312111098
RESERVEDOPT2_MCU_PBIST_ENOPT2_MCU_LBIST_ENOPT2_DMSC_LBIST_ENOPT2_PARALLEL_EN
R-0hR-XR-XR-XR-X
76543210
RESERVEDOPT1_MCU_PBIST_ENOPT1_MCU_LBIST_ENOPT1_DMSC_LBIST_ENOPT1_PARALLEL_EN
R-0hR-XR-XR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-34 CTRLMMR_WKUP_POST_OPT Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h

Reserved

19OPT3_MCU_PBIST_ENRX

MCU R5 PBIST enabled

18OPT3_MCU_LBIST_ENRX

MCU R5 LBIST enabled

17OPT3_DMSC_LBIST_ENRX

DMSC LBIST enabled

16OPT3_PARALLEL_ENRX

Selects DMSC/MCU R5 LBIST sequencing
0h - Serial (DMSC LBIST performed first)
1h - Parallel

15-12RESERVEDR0h

Reserved

11OPT2_MCU_PBIST_ENRX

MCU R5 PBIST enabled

10OPT2_MCU_LBIST_ENRX

MCU R5 LBIST enabled

9OPT2_DMSC_LBIST_ENRX

DMSC LBIST enabled

8OPT2_PARALLEL_ENRX

Selects DMSC/MCU R5 LBIST sequencing
0h - Serial (DMSC LBIST performed first)
1h - Parallel

7-4RESERVEDR0h

Reserved

3OPT1_MCU_PBIST_ENRX

MCU R5 PBIST enabled

2OPT1_MCU_LBIST_ENRX

MCU R5 LBIST enabled

1OPT1_DMSC_LBIST_ENRX

DMSC LBIST enabled

0OPT1_PARALLEL_ENRX

Selects DMSC/MCU R5 LBIST sequencing
0h - Serial (DMSC LBIST performed first)
1h - Parallel

1.1.4.13 CTRLMMR_WKUP_RESET_SRC_STAT Register ( Offset = 50h) [reset = 0h]

CTRLMMR_WKUP_RESET_SRC_STAT is shown in Figure 5-14 and described in Table 5-36.

Return to Summary Table.

Indicates source of last device reset.

Table 5-35 CTRLMMR_WKUP_RESET_SRC_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0050h
Figure 5-14 CTRLMMR_WKUP_RESET_SRC_STAT Register
3130292827262524
RESERVEDTHERMAL_RST
R-0hREC-0h
2322212019181716
RESERVEDDBUGSS_RSTCOLD_OUT_RSTRESERVEDWARM_OUT_RST
R-0hFEC-0hFEC-0hR-0hFEC-0h
15141312111098
RESERVEDPORZ_PINRESERVEDRESET_REQZ_PINMCU_RSTZ_PIN
R-0hFEC-0hR-0hFEC-0hFEC-0h
76543210
RESERVEDSW_MAIN_PORRESERVEDSW_MAIN_WARMRSTSW_MCU_WARMRST
R-0hFEC-0hR-0hFEC-0hFEC-0h
LEGEND: FEC = Falling Edge Capture; R = Read Only; REC = Rising Edge Capture-n = value after reset
Table 5-36 CTRLMMR_WKUP_RESET_SRC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h

Reserved

24THERMAL_RSTREC0h

When set, indicates that a VTM Max Temp Thermal reset occurred.
Write 1 to clear this bit.

23-21RESERVEDR0h

Reserved

20DBUGSS_RSTFEC0h

When set, indicates that a Debug reset occurred.
Write 1 to clear this bit.

19COLD_OUT_RSTFEC0h

When set, indicates that a DMSC Cold reset occurred.
Write 1 to clear this bit.

18-17RESERVEDR0h

Reserved

16WARM_OUT_RSTFEC0h

When set, indicates that a DSMC Warm reset occurred.
Write 1 to clear this bit.

15-12RESERVEDR0h

Reserved

11PORZ_PINFEC0h

When set indicates that a PORz pin reset occurred.
Write 1 to clear this bit.

10RESERVEDR0h

Reserved

9RESET_REQZ_PINFEC0h

When set indicates that a RESET_REQz pin reset occurred.
Write 1 to clear this bit.

8MCU_RSTZ_PINFEC0h

When set indicates that a MCU_RESETz pin reset occurred.
Write 1 to clear this bit.

7-4RESERVEDR0h

Reserved

3SW_MAIN_PORFEC0h

When set, indicates that a Software MAIN Power-on reset occurred.
Write 1 to clear this bit.

2RESERVEDR0h

Reserved

1SW_MAIN_WARMRSTFEC0h

When set indicates that a Software MAIN Warm reset occurred.
Write 1 to clear this bit.

0SW_MCU_WARMRSTFEC0h

When set indicates that a Software MCU Warm reset occurred.
Write 1 to clear this bit.

1.1.4.14 CTRLMMR_WKUP_DEVICE_FEATURE0 Register ( Offset = 60h) [reset = X]

CTRLMMR_WKUP_DEVICE_FEATURE0 is shown in Figure 5-15 and described in Table 5-38.

Return to Summary Table.

Indicates enabled MPU processing elements on the device.

Table 5-37 CTRLMMR_WKUP_DEVICE_FEATURE0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0060h
Figure 5-15 CTRLMMR_WKUP_DEVICE_FEATURE0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMPU_CLUSTER0_CORE1MPU_CLUSTER0_CORE0
R-0hR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-38 CTRLMMR_WKUP_DEVICE_FEATURE0 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1MPU_CLUSTER0_CORE1RX

MPU Cluster0 Core 1 is enabled when set

0MPU_CLUSTER0_CORE0RX

MPU Cluster0 Core 0 is enabled when set

1.1.4.15 CTRLMMR_WKUP_DEVICE_FEATURE1 Register ( Offset = 64h) [reset = X]

CTRLMMR_WKUP_DEVICE_FEATURE1 is shown in Figure 5-16 and described in Table 5-40.

Return to Summary Table.

Indicates enabled non-MPU processing elements on the device.

Table 5-39 CTRLMMR_WKUP_DEVICE_FEATURE1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0064h
Figure 5-16 CTRLMMR_WKUP_DEVICE_FEATURE1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMCU_CLUSTER0_CORE1MCU_CLUSTER0_CORE0
R-0hR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-40 CTRLMMR_WKUP_DEVICE_FEATURE1 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1MCU_CLUSTER0_CORE1RX

MAIN MCU Cluster0 Core1 is enabled when set

0MCU_CLUSTER0_CORE0RX

MAIN MCU Cluster0 Core0 is enabled when set

1.1.4.16 CTRLMMR_WKUP_DEVICE_FEATURE2 Register ( Offset = 68h) [reset = X]

CTRLMMR_WKUP_DEVICE_FEATURE2 is shown in Figure 5-17 and described in Table 5-42.

Return to Summary Table.

Indicates enabled MCU domain interface elements on the device.

Table 5-41 CTRLMMR_WKUP_DEVICE_FEATURE2 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0068h
Figure 5-17 CTRLMMR_WKUP_DEVICE_FEATURE2 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCRYPTO_PKA_ENCRYPTO_ENCR_ENCRYPTO_SHA_EN
R-0hR-XR-XR-X
76543210
AES_AUTH_ENHYPERBUSRESERVEDOSPI0MCU_MCAN1RESERVEDMCU_MCAN0MCU_MCAN_FD_MODE
R-XR-XR-XR-XR-XR-0hR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-42 CTRLMMR_WKUP_DEVICE_FEATURE2 Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0h

Reserved

10CRYPTO_PKA_ENRX

MCU SA2_UL Crypto Module PKA enabled

9CRYPTO_ENCR_ENRX

MCU SA2_UL Crypto Module AES/3DES/DBRG enabled

8CRYPTO_SHA_ENRX

MCU SA2_UL Crypto Module SHA/MD5 enabled

7AES_AUTH_ENRX

AES authentication is enabled in MCU_FlashSS and DMSC when set

6HYPERBUSRX

MCU_Hyperbus is enabled when set

5RESERVEDRX

Reserved

4OSPI0RX

MCU_OSPI0 is enabled when set

3MCU_MCAN1RX

MCU_MCAN1 is enabled when set

2RESERVEDR0h

Reserved

1MCU_MCAN0RX

MCU_MCAN0 is enabled when set

0MCU_MCAN_FD_MODERX

FD mode is supported on MCU_MCAN[1:0] when set

1.1.4.17 CTRLMMR_WKUP_DEVICE_FEATURE3 Register ( Offset = 6Ch) [reset = X]

CTRLMMR_WKUP_DEVICE_FEATURE3 is shown in Figure 5-18 and described in Table 5-44.

Return to Summary Table.

Indicates enabled MAIN domain interface elements on the device.

Table 5-43 CTRLMMR_WKUP_DEVICE_FEATURE3 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 006Ch
Figure 5-18 CTRLMMR_WKUP_DEVICE_FEATURE3 Register
3130292827262524
RESERVEDEMIF0RESERVED
R-0hR-XR-0h
2322212019181716
RESERVEDMMC_4B0MMC_8BRESERVED
R-0hR-XR-XR-0h
15141312111098
RESERVEDSERDES0
R-0hR-X
76543210
RESERVEDPCIE1RESERVEDUSB0
R-0hR-XR-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-44 CTRLMMR_WKUP_DEVICE_FEATURE3 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h

Reserved

28EMIF0RX

EMIF0 is enabled when set

27-22RESERVEDR0h

Reserved

21MMC_4B0RX

4-bit MMC/SD1 is enabled when set

20MMC_8BRX

8-bit MMC/SD0 is enabled when set

19-9RESERVEDR0h

Reserved

8SERDES0RX

10G SERDES0 is enabled when set

7-6RESERVEDR0h

Reserved

5PCIE1RX

PCIe1 is enabled when set

4-1RESERVEDR0h

Reserved

0USB0RX

USB0 is enabled when set

1.1.4.18 CTRLMMR_WKUP_DEVICE_FEATURE5 Register ( Offset = 74h) [reset = X]

CTRLMMR_WKUP_DEVICE_FEATURE5 is shown in Figure 5-19 and described in Table 5-46.

Return to Summary Table.

Indicates enabled MAIN domain interface elements on the device.

Table 5-45 CTRLMMR_WKUP_DEVICE_FEATURE5 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0074h
Figure 5-19 CTRLMMR_WKUP_DEVICE_FEATURE5 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMCAN17MCAN16
R-0hR-XR-X
15141312111098
MCAN15MCAN14MCAN13MCAN12MCAN11MCAN10MCAN9MCAN8
R-XR-XR-XR-XR-XR-XR-XR-X
76543210
MCAN7MCAN6MCAN5MCAN4MCAN3MCAN2MCAN1MCAN0
R-XR-XR-XR-XR-XR-XR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-46 CTRLMMR_WKUP_DEVICE_FEATURE5 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h

Reserved

17MCAN17RX

MCAN17 is enabled when set

16MCAN16RX

MCAN16 is enabled when set

15MCAN15RX

MCAN15 is enabled when set

14MCAN14RX

MCAN14 is enabled when set

13MCAN13RX

MCAN13 is enabled when set

12MCAN12RX

MCAN12 is enabled when set

11MCAN11RX

MCAN11 is enabled when set

10MCAN10RX

MCAN10 is enabled when set

9MCAN9RX

MCAN9 is enabled when set

8MCAN8RX

MCAN8 is enabled when set

7MCAN7RX

MCAN7 is enabled when set

6MCAN6RX

MCAN6 is enabled when set

5MCAN5RX

MCAN5 is enabled when set

4MCAN4RX

MCAN4 is enabled when set

3MCAN3RX

MCAN3 is enabled when set

2MCAN2RX

MCAN2 is enabled when set

1MCAN1RX

MCAN1 is enabled when set

0MCAN0RX

MCAN0 is enabled when set

1.1.4.19 CTRLMMR_WKUP_DEVICE_FEATURE6 Register ( Offset = 78h) [reset = X]

CTRLMMR_WKUP_DEVICE_FEATURE6 is shown in Figure 5-20 and described in Table 5-48.

Return to Summary Table.

Indicates enabled MAIN domain interface elements on the device.

Table 5-47 CTRLMMR_WKUP_DEVICE_FEATURE6 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0078h
Figure 5-20 CTRLMMR_WKUP_DEVICE_FEATURE6 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-XR-XR-XR-0h
15141312111098
RESERVEDI3CMOTOR_PER
R-0hR-XR-X
76543210
ATLRESERVEDCPSW5GRESERVED
R-XR-0hR-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-48 CTRLMMR_WKUP_DEVICE_FEATURE6 Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h

Reserved

22RESERVEDRX

Reserved

21RESERVEDRX

Reserved

20RESERVEDRX

Reserved

19-10RESERVEDR0h

Reserved

9I3CRX

MAIN domain I3C is enabled when set

8MOTOR_PERRX

Motor control peripherals (eCAP, eQEP, eHRPWM) are enabled when set

7ATLRX

Audio tracking logic is enabled when set

6-5RESERVEDR0h

Reserved

4CPSW5GRX

4 Channel Q/SGMII Ethernet switch enabled when set

3-0RESERVEDR0h

Reserved

1.1.4.20 CTRLMMR_WKUP_DBG_CBA_ERR_STAT Register ( Offset = 200h) [reset = X]

CTRLMMR_WKUP_DBG_CBA_ERR_STAT is shown in Figure 5-21 and described in Table 5-50.

Return to Summary Table.

Indicates addressing errors on the Debug CBA bus segments.

Table 5-49 CTRLMMR_WKUP_DBG_CBA_ERR_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0200h
Figure 5-21 CTRLMMR_WKUP_DBG_CBA_ERR_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMAIN_DBG_ERRRESERVED
R-0hR-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-50 CTRLMMR_WKUP_DBG_CBA_ERR_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1MAIN_DBG_ERRRX

Main Debug bus segment error

0RESERVEDR0h

Reserved

1.1.4.21 CTRLMMR_WKUP_FW_CBA_ERR_STAT Register ( Offset = 204h) [reset = X]

CTRLMMR_WKUP_FW_CBA_ERR_STAT is shown in Figure 5-22 and described in Table 5-52.

Return to Summary Table.

Indicates addressing errors on the Firewall CBA bus segments.

Table 5-51 CTRLMMR_WKUP_FW_CBA_ERR_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0204h
Figure 5-22 CTRLMMR_WKUP_FW_CBA_ERR_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMAIN_FW_ERRMCU_FW_ERRWKUP_FW_ERR
R-0hR-XR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-52 CTRLMMR_WKUP_FW_CBA_ERR_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2MAIN_FW_ERRRX

MAIN Firewall bus segment error

1MCU_FW_ERRRX

MCU Firewall bus segment error

0WKUP_FW_ERRRX

WKUP Firewall bus segment error

1.1.4.22 CTRLMMR_WKUP_NONFW_CBA_ERR_STAT Register ( Offset = 208h) [reset = X]

CTRLMMR_WKUP_NONFW_CBA_ERR_STAT is shown in Figure 5-23 and described in Table 5-54.

Return to Summary Table.

Indicates addressing errors on Non-Firewall CBA bus segments.

Table 5-53 CTRLMMR_WKUP_NONFW_CBA_ERR_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0208h
Figure 5-23 CTRLMMR_WKUP_NONFW_CBA_ERR_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMAIN_INFRA_NONSAFE_CBA_ERRDBG_CBA_ERRWKUP_CBA_ERRMCU_CBA_ERRMAIN_INFRA_CBA_ERRMAIN_CBA_ERR
R-0hR-XR-XR-XR-XR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-54 CTRLMMR_WKUP_NONFW_CBA_ERR_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5MAIN_INFRA_NONSAFE_CBA_ERRRX

MAIN Infrastructure non-safe bus segment error

4DBG_CBA_ERRRX

Debug bus aggregated error. See CTRLMMR_WKUP_DBG_CBA_ERR_STAT for specific segment information.

3WKUP_CBA_ERRRX

WKUP Data bus segment error

2MCU_CBA_ERRRX

MCU Data bus segment error

1MAIN_INFRA_CBA_ERRRX

MAIN Infrastructure safe bus segment error

0MAIN_CBA_ERRRX

MAIN Data bus aggregated error. See CTRLMMR_WKUP_MAIN_CBA_ERR_STAT for specific segment information

1.1.4.23 CTRLMMR_WKUP_MAIN_CBA_ERR_STAT Register ( Offset = 210h) [reset = X]

CTRLMMR_WKUP_MAIN_CBA_ERR_STAT is shown in Figure 5-24 and described in Table 5-56.

Return to Summary Table.

Indicates addressing errors on the MAIN CBA bus segments.

Table 5-55 CTRLMMR_WKUP_MAIN_CBA_ERR_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 0210h
Figure 5-24 CTRLMMR_WKUP_MAIN_CBA_ERR_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDPULSAR0_SLV_CBA_ERRPULSAR0_MEM_CBA_ERR
R-0hR-XR-X
15141312111098
RESERVEDIPPHY_SAFE_CBA_ERRRESERVEDMCASP_G0_CBA_ERRIPPHY_CBA_ERRRESERVED
R-0hR-XR-0hR-XR-XR-0h
76543210
DEBUG_CBA_ERRHC2_CBA_ERRHC_CFG_CBA_ERRRESERVEDRC_CFG_CBA_ERRRC_CBA_ERRRESERVED
R-XR-XR-XR-0hR-XR-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-56 CTRLMMR_WKUP_MAIN_CBA_ERR_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h

Reserved

17PULSAR0_SLV_CBA_ERRRX

MAIN R5 Slave Data bus segment error

16PULSAR0_MEM_CBA_ERRRX

MAIN R5 Memory Data bus segment error

15-14RESERVEDR0h

Reserved

13IPPHY_SAFE_CBA_ERRRX

MAIN Phy safe Data bus segment error

12RESERVEDR0h

Reserved

11MCASP_G0_CBA_ERRRX

MAIN McASP Group0 Data bus segment error

10IPPHY_CBA_ERRRX

MAIN Phy non-safe Data bus segment error

9-8RESERVEDR0h

Reserved

7DEBUG_CBA_ERRRX

MAIN Debug Data bus segment error

6HC2_CBA_ERRRX

MAIN HC2 Data bus segment error

5HC_CFG_CBA_ERRRX

MAIN HC CFG Data bus segment error

4RESERVEDR0h

Reserved

3RC_CFG_CBA_ERRRX

MAIN RC CFG Data bus segment error

2RC_CBA_ERRRX

MAIN RC Data bus segment error

1-0RESERVEDR0h

Reserved

1.1.4.24 CTRLMMR_WKUP_LOCK0_KICK0 Register ( Offset = 1008h) [reset = 0h]

CTRLMMR_WKUP_LOCK0_KICK0 is shown in Figure 5-25 and described in Table 5-58.

Return to Summary Table.

Lower 32-bits of Partition0 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_WKUP_LOCK0_KICK1 with its key value before write-protected Partition 0 registers can be written.

Table 5-57 CTRLMMR_WKUP_LOCK0_KICK0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 1008h
Figure 5-25 CTRLMMR_WKUP_LOCK0_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-58 CTRLMMR_WKUP_LOCK0_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers

0UNLOCKEDR0h

Unlock status.
When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.4.25 CTRLMMR_WKUP_LOCK0_KICK1 Register ( Offset = 100Ch) [reset = 0h]

CTRLMMR_WKUP_LOCK0_KICK1 is shown in Figure 5-26 and described in Table 5-60.

Return to Summary Table.

Upper 32-bits of Partition 0 write lock key. This register must be written with the designated key value after a write to CTRLMMR_WKUP_LOCK0_KICK0 with its key value before write-protected Partition 0 registers can be written.

Table 5-59 CTRLMMR_WKUP_LOCK0_KICK1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 100Ch
Figure 5-26 CTRLMMR_WKUP_LOCK0_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-60 CTRLMMR_WKUP_LOCK0_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers

1.1.4.26 CTRLMMR_WKUP_INTR_RAW_STAT Register ( Offset = 1010h) [reset = 0h]

CTRLMMR_WKUP_INTR_RAW_STAT is shown in Figure 5-27 and described in Table 5-62.

Return to Summary Table.

Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test).

Table 5-61 CTRLMMR_WKUP_INTR_RAW_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 1010h
Figure 5-27 CTRLMMR_WKUP_INTR_RAW_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDLOCK_ERRADDR_ERRPROT_ERR
R-0hW1TS-0hW1TS-0hW1TS-0hW1TS-0h
LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset
Table 5-62 CTRLMMR_WKUP_INTR_RAW_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3RESERVEDW1TS0h

Reserved

2LOCK_ERRW1TS0h

Lock violation occurred (attempt to write a write-locked register with partition locked)
Write 1 to set the status bit (for test)
Writing 0 has no effect.

1ADDR_ERRW1TS0h

Address violation occurred (attempt to read or write an invalid register address)
Write 1 to set the status bit (for test)
Writing 0 has no effect.

0PROT_ERRW1TS0h

Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)
Write 1 to set the status bit (for test)
Writing 0 has no effect.

1.1.4.27 CTRLMMR_WKUP_INTR_STAT_CLR Register ( Offset = 1014h) [reset = 0h]

CTRLMMR_WKUP_INTR_STAT_CLR is shown in Figure 5-28 and described in Table 5-64.

Return to Summary Table.

Shows the enabled interrupt status and allows the interrupt to be cleared.

Table 5-63 CTRLMMR_WKUP_INTR_STAT_CLR Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 1014h
Figure 5-28 CTRLMMR_WKUP_INTR_STAT_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDEN_LOCK_ERREN_ADDR_ERREN_PROT_ERR
R-0hW1TC-0hW1TC-0hW1TC-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-64 CTRLMMR_WKUP_INTR_STAT_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3RESERVEDW1TC0h

Reserved

2EN_LOCK_ERRW1TC0h

Enabled lock interrupt event status
Write 1 to clear the interrupt event
Writing 0 has no effect.

1EN_ADDR_ERRW1TC0h

Enabled address interrupt event status
Write 1 to clear the interrupt event
Writing 0 has no effect.

0EN_PROT_ERRW1TC0h

Enabled protection interrupt event status
Write 1 to clear the interrupt event
Writing 0 has no effect.

1.1.4.28 CTRLMMR_WKUP_INTR_EN_SET Register ( Offset = 1018h) [reset = 0h]

CTRLMMR_WKUP_INTR_EN_SET is shown in Figure 5-29 and described in Table 5-66.

Return to Summary Table.

Allows interrupt enables to be set.

Table 5-65 CTRLMMR_WKUP_INTR_EN_SET Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 1018h
Figure 5-29 CTRLMMR_WKUP_INTR_EN_SET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDLOCK_ERR_EN_SETADDR_ERR_EN_SETPROT_ERR_EN_SET
R-0hW1TS-0hW1TS-0hW1TS-0hW1TS-0h
LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset
Table 5-66 CTRLMMR_WKUP_INTR_EN_SET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3RESERVEDW1TS0h

Reserved

2LOCK_ERR_EN_SETW1TS0h

Lock interrupt enable
Write 1 to enable lock interrupt events
Writing 0 has no effect.

1ADDR_ERR_EN_SETW1TS0h

Address interrupt enable
Write 1 to enable address interrupt events
Writing 0 has no effect.

0PROT_ERR_EN_SETW1TS0h

Protection interrupt enable
Write 1 to enable protection interrupt events
Writing 0 has no effect.

1.1.4.29 CTRLMMR_WKUP_INTR_EN_CLR Register ( Offset = 101Ch) [reset = 0h]

CTRLMMR_WKUP_INTR_EN_CLR is shown in Figure 5-30 and described in Table 5-68.

Return to Summary Table.

Allows interrupt enables to be cleared.

Table 5-67 CTRLMMR_WKUP_INTR_EN_CLR Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 101Ch
Figure 5-30 CTRLMMR_WKUP_INTR_EN_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDLOCK_ERR_EN_CLRADDR_ERR_EN_CLRPROT_ERR_EN_CLR
R-0hW1TC-0hW1TC-0hW1TC-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-68 CTRLMMR_WKUP_INTR_EN_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3RESERVEDW1TC0h

Reserved

2LOCK_ERR_EN_CLRW1TC0h

Lock interrupt disable
Write 1 to disable lock interrupt events
Writing 0 has no effect.

1ADDR_ERR_EN_CLRW1TC0h

Address interrupt disable
Write 1 to disable address interrupt events
Writing 0 has no effect.

0PROT_ERR_EN_CLRW1TC0h

Protection interrupt disable
Write 1 to disable protection interrupt events
Writing 0 has no effect.

1.1.4.30 CTRLMMR_WKUP_EOI Register ( Offset = 1020h) [reset = 0h]

CTRLMMR_WKUP_EOI is shown in Figure 5-31 and described in Table 5-70.

Return to Summary Table.

CTRLMMR_WKUP_EOI Vector value This register should be written with interrupt distribution value required by the device architecture to indicate service completion of the MMR interrupt.

Table 5-69 CTRLMMR_WKUP_EOI Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 1020h
Figure 5-31 CTRLMMR_WKUP_EOI Register
313029282726252423222120191817161514131211109876543210
RESERVEDVECTOR
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-70 CTRLMMR_WKUP_EOI Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7-0VECTORR/W0h

CTRLMMR_WKUP_EOI vector value

1.1.4.31 CTRLMMR_WKUP_FAULT_ADDR Register ( Offset = 1024h) [reset = 0h]

CTRLMMR_WKUP_FAULT_ADDR is shown in Figure 5-32 and described in Table 5-72.

Return to Summary Table.

Indicates the address of the first transfer that caused a fault to occur.

Table 5-71 CTRLMMR_WKUP_FAULT_ADDR Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 1024h
Figure 5-32 CTRLMMR_WKUP_FAULT_ADDR Register
313029282726252423222120191817161514131211109876543210
ADDRESS
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-72 CTRLMMR_WKUP_FAULT_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR0h

Address of the faulted access

1.1.4.32 CTRLMMR_WKUP_FAULT_TYPE Register ( Offset = 1028h) [reset = 0h]

CTRLMMR_WKUP_FAULT_TYPE is shown in Figure 5-33 and described in Table 5-74.

Return to Summary Table.

Indicates the access type of the first transfer that caused a fault to occur.

Table 5-73 CTRLMMR_WKUP_FAULT_TYPE Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 1028h
Figure 5-33 CTRLMMR_WKUP_FAULT_TYPE Register
313029282726252423222120191817161514131211109876543210
RESERVEDTYPE
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-74 CTRLMMR_WKUP_FAULT_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0TYPER0h

Type of access which faulted

0h - No fault

1h - User execute access

2h - User write access

4h - User read access

8h - Supervisor execute access

10h - Supervisor write access

20h - Supervisor read access

1.1.4.33 CTRLMMR_WKUP_FAULT_ATTR Register ( Offset = 102Ch) [reset = 0h]

CTRLMMR_WKUP_FAULT_ATTR is shown in Figure 5-34 and described in Table 5-76.

Return to Summary Table.

Indicates the attributes of the first transfer that caused a fault to occur.

Table 5-75 CTRLMMR_WKUP_FAULT_ATTR Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 102Ch
Figure 5-34 CTRLMMR_WKUP_FAULT_ATTR Register
3130292827262524
XID
R-0h
2322212019181716
XIDROUTEID
R-0hR-0h
15141312111098
ROUTEID
R-0h
76543210
PRIVID
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-76 CTRLMMR_WKUP_FAULT_ATTR Register Field Descriptions
BitFieldTypeResetDescription
31-20XIDR0h

Transaction ID

19-8ROUTEIDR0h

Route ID

7-0PRIVIDR0h

Privilege ID

1.1.4.34 CTRLMMR_WKUP_FAULT_CLR Register ( Offset = 1030h) [reset = 0h]

CTRLMMR_WKUP_FAULT_CLR is shown in Figure 5-35 and described in Table 5-78.

Return to Summary Table.

Allows software to clear the current fault Clearing the current fault allows the CTRLMMR_WKUP_FAULT_ADDR, CTRLMMR_WKUP_FAULT_TYPE, and CTRLMMR_WKUP_FAULT_ATTR registers to latch the attributes of the next fault that occurs. This does not affect the fault interrupt event itself. The interrupt must be cleared using the appropriate INTR_STATUS_CLR register bits.

Table 5-77 CTRLMMR_WKUP_FAULT_CLR Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 1030h
Figure 5-35 CTRLMMR_WKUP_FAULT_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLEAR
R-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-78 CTRLMMR_WKUP_FAULT_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0CLEARW1TC0h

Fault clear
Write 1 to clear the current fault
Writing 0 has no effect

1.1.4.35 CTRLMMR_WKUP_MAIN_PWR_CTRL Register ( Offset = 4004h) [reset = 1h]

CTRLMMR_WKUP_MAIN_PWR_CTRL is shown in Figure 5-36 and described in Table 5-80.

Return to Summary Table.

Controls power options for the MAIN voltage domain.

Table 5-79 CTRLMMR_WKUP_MAIN_PWR_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4004h
Figure 5-36 CTRLMMR_WKUP_MAIN_PWR_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDWAKE_EN
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPWR_EN
R-0hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-80 CTRLMMR_WKUP_MAIN_PWR_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16WAKE_ENR/W0h

When set, drives the PMIC_WAKE0 (CANUART IOs domain) output low.
This bit should be set to 1h only for diagnostic purposes.
0h - PMIC_WAKE0 output is tri-stated (controlled by IO daisy-chain wakeup)
1h - Force PMIC_WAKE0 output enable (PMIC_WAKE0 driven low)

15-1RESERVEDR0h

Reserved

0PWR_ENR/W1h

When set, drives the PMIC_PWR_EN1 output to turn on the MAIN voltage domain

1.1.4.36 CTRLMMR_WKUP_MCU_PWR_CTRL Register ( Offset = 4008h) [reset = 0h]

CTRLMMR_WKUP_MCU_PWR_CTRL is shown in Figure 5-37 and described in Table 5-82.

Return to Summary Table.

Controls power options for the MAIN voltage domain.

Table 5-81 CTRLMMR_WKUP_MCU_PWR_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4008h
Figure 5-37 CTRLMMR_WKUP_MCU_PWR_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDWAKE_EN
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-82 CTRLMMR_WKUP_MCU_PWR_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16WAKE_ENR/W0h

When set, drives the PMIC_WAKE1 (MCU_GENERAL IOs domain) output low.
This bit should be set to 1h only for diagnostic purposes.
0h - PMIC_WAKE1 output is tri-stated (controlled by IO daisy-chain wakeup)
1h - Force PMIC_WAKE1 output enable (PMIC_WAKE1 driven low)

15-0RESERVEDR0h

Reserved

1.1.4.37 CTRLMMR_WKUP_GPIO_CTRL Register ( Offset = 4020h) [reset = 0h]

CTRLMMR_WKUP_GPIO_CTRL is shown in Figure 5-38 and described in Table 5-84.

Return to Summary Table.

Controls operation of the WKUP_GPIO module.

Table 5-83 CTRLMMR_WKUP_GPIO_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4020h
Figure 5-38 CTRLMMR_WKUP_GPIO_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWAKEN
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-84 CTRLMMR_WKUP_GPIO_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0WAKENR/W0h

Enables WKUP_GPIO wakeup event operation by controlling the WKUP_GPIO LPSC clockstop_ack behavior.

0h - No WKUP_GPIO wakeup support. WKUP_GPIO vbus clock is gated on clkstop_ack from WKUP_GPIO to LPSC

1h - WKUP_GPIO wakeup enabled. WKUP_GPIO vbus clock is NOT gated on LPSC clockstop_req. WKUP_GPIO LPSC clkstop_ack input is driven by clkstop_req output.

1.1.4.38 CTRLMMR_WKUP_I2C0_CTRL Register ( Offset = 4030h) [reset = 0h]

CTRLMMR_WKUP_I2C0_CTRL is shown in Figure 5-39 and described in Table 5-86.

Return to Summary Table.

Controls WKUP_I2C0 operation.

Table 5-85 CTRLMMR_WKUP_I2C0_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4030h
Figure 5-39 CTRLMMR_WKUP_I2C0_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDHS_MCS_EN
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-86 CTRLMMR_WKUP_I2C0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0HS_MCS_ENR/W0h

HS Mode master current source enable.
When set, enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing.

1.1.4.39 CTRLMMR_WKUP_DBOUNCE_CFG1 Register ( Offset = 4084h) [reset = 0h]

CTRLMMR_WKUP_DBOUNCE_CFG1 is shown in Figure 5-40 and described in Table 5-88.

Return to Summary Table.

Configures IO debounce selections.

Table 5-87 CTRLMMR_WKUP_DBOUNCE_CFG1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4084h
Figure 5-40 CTRLMMR_WKUP_DBOUNCE_CFG1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDDB_CFG
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-88 CTRLMMR_WKUP_DBOUNCE_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0DB_CFGR/W0h

Configures the debounce period used for I/Os with DEBOUNCE_SEL1 enabled.

1.1.4.40 CTRLMMR_WKUP_DBOUNCE_CFG2 Register ( Offset = 4088h) [reset = 0h]

CTRLMMR_WKUP_DBOUNCE_CFG2 is shown in Figure 5-41 and described in Table 5-90.

Return to Summary Table.

Configures IO debounce selections.

Table 5-89 CTRLMMR_WKUP_DBOUNCE_CFG2 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4088h
Figure 5-41 CTRLMMR_WKUP_DBOUNCE_CFG2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDDB_CFG
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-90 CTRLMMR_WKUP_DBOUNCE_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0DB_CFGR/W0h

Configures the debounce period used for I/Os with DEBOUNCE_SEL2 enabled.

1.1.4.41 CTRLMMR_WKUP_DBOUNCE_CFG3 Register ( Offset = 408Ch) [reset = 0h]

CTRLMMR_WKUP_DBOUNCE_CFG3 is shown in Figure 5-42 and described in Table 5-92.

Return to Summary Table.

Configures IO debounce selections.

Table 5-91 CTRLMMR_WKUP_DBOUNCE_CFG3 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 408Ch
Figure 5-42 CTRLMMR_WKUP_DBOUNCE_CFG3 Register
313029282726252423222120191817161514131211109876543210
RESERVEDDB_CFG
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-92 CTRLMMR_WKUP_DBOUNCE_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0DB_CFGR/W0h

Configures the debounce period used for I/Os with DEBOUNCE_SEL3 enabled.

1.1.4.42 CTRLMMR_WKUP_DBOUNCE_CFG4 Register ( Offset = 4090h) [reset = 0h]

CTRLMMR_WKUP_DBOUNCE_CFG4 is shown in Figure 5-43 and described in Table 5-94.

Return to Summary Table.

Configures IO debounce selections.

Table 5-93 CTRLMMR_WKUP_DBOUNCE_CFG4 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4090h
Figure 5-43 CTRLMMR_WKUP_DBOUNCE_CFG4 Register
313029282726252423222120191817161514131211109876543210
RESERVEDDB_CFG
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-94 CTRLMMR_WKUP_DBOUNCE_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0DB_CFGR/W0h

Configures the debounce period used for I/Os with DEBOUNCE_SEL4 enabled.

1.1.4.43 CTRLMMR_WKUP_DBOUNCE_CFG5 Register ( Offset = 4094h) [reset = 0h]

CTRLMMR_WKUP_DBOUNCE_CFG5 is shown in Figure 5-44 and described in Table 5-96.

Return to Summary Table.

Configures IO debounce selections.

Table 5-95 CTRLMMR_WKUP_DBOUNCE_CFG5 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4094h
Figure 5-44 CTRLMMR_WKUP_DBOUNCE_CFG5 Register
313029282726252423222120191817161514131211109876543210
RESERVEDDB_CFG
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-96 CTRLMMR_WKUP_DBOUNCE_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0DB_CFGR/W0h

Configures the debounce period used for I/Os with DEBOUNCE_SEL5 enabled.

1.1.4.44 CTRLMMR_WKUP_DBOUNCE_CFG6 Register ( Offset = 4098h) [reset = 0h]

CTRLMMR_WKUP_DBOUNCE_CFG6 is shown in Figure 5-45 and described in Table 5-98.

Return to Summary Table.

Configures IO debounce selections.

Table 5-97 CTRLMMR_WKUP_DBOUNCE_CFG6 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 4098h
Figure 5-45 CTRLMMR_WKUP_DBOUNCE_CFG6 Register
313029282726252423222120191817161514131211109876543210
RESERVEDDB_CFG
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-98 CTRLMMR_WKUP_DBOUNCE_CFG6 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0DB_CFGR/W0h

Configures the debounce period used for I/Os with DEBOUNCE_SEL6 enabled.

1.1.4.45 CTRLMMR_WKUP_LOCK1_KICK0 Register ( Offset = 5008h) [reset = 0h]

CTRLMMR_WKUP_LOCK1_KICK0 is shown in Figure 5-46 and described in Table 5-100.

Return to Summary Table.

Lower 32-bits of Partition1 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_WKUP_LOCK1_KICK1 with its key value before write-protected Partition 1 registers can be written.

Table 5-99 CTRLMMR_WKUP_LOCK1_KICK0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 5008h
Figure 5-46 CTRLMMR_WKUP_LOCK1_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-100 CTRLMMR_WKUP_LOCK1_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers

0UNLOCKEDR0h

Unlock status.
When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.4.46 CTRLMMR_WKUP_LOCK1_KICK1 Register ( Offset = 500Ch) [reset = 0h]

CTRLMMR_WKUP_LOCK1_KICK1 is shown in Figure 5-47 and described in Table 5-102.

Return to Summary Table.

Upper 32-bits of Partition 1 write lock key. This register must be written with the designated key value after a write to CTRLMMR_WKUP_LOCK1_KICK0 with its key value before write-protected Partition 1 registers can be written.

Table 5-101 CTRLMMR_WKUP_LOCK1_KICK1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 500Ch
Figure 5-47 CTRLMMR_WKUP_LOCK1_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-102 CTRLMMR_WKUP_LOCK1_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers

1.1.4.47 CTRLMMR_WKUP_MCU_OBSCLK_CTRL Register ( Offset = 8000h) [reset = 3h]

CTRLMMR_WKUP_MCU_OBSCLK_CTRL is shown in Figure 5-48 and described in Table 5-104.

Return to Summary Table.

Controls which internal clock is made observable on the MCU_OBSCLK output pin.

Table 5-103 CTRLMMR_WKUP_MCU_OBSCLK_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8000h
Figure 5-48 CTRLMMR_WKUP_MCU_OBSCLK_CTRL Register
3130292827262524
RESERVEDOUT_MUX_SEL
R-0hR/W-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVEDCLK_DIV
R-0hR/W-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-104 CTRLMMR_WKUP_MCU_OBSCLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h

Reserved

24OUT_MUX_SELR/W0h

MCU_OBSCLK pin output mux selection.
Note, when HFOSC0_CLK is selected (1h) the MCU_OBSCLK_CTRL_clk_sel field must be programmed to 1h.
0h - The output of the MCU_OBSCLK output divider is output on the pin
1h - HFOSC0_CLK is output on the pin

23-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the OBSCLK divider value. This bit can be cleared but must not be set in the same write cycle in which the CLK_DIV value is changed.

15-12RESERVEDR0h

Reserved

11-8CLK_DIVR/W0h

MCU_OBSCLK pin clock selection output divider
Output clock is divided by CLK_DIV+1

7-4RESERVEDR0h

Reserved

3-0CLK_SELR/W3h

MCU_OBSCLK pin clock selection

0h - CLK_12M_RC

1h - "0"

2h - MCU_PLL0_HSDIV0_CLKOUT

3h - MCU_PLLCTL_OBSCLK

4h - MCU_PLL1_HSDIV1_CLKOUT

5h - MCU_PLL1_HSDIV2_CLKOUT

6h - MCU_PLL1_HSDIV3_CLKOUT

7h - MCU_PLL1_HSDIV4_CLKOUT

8h - MCU_PLL2_HSDIV0_CLKOUT

9h - CLK_32K

Ah - MCU_PLL2_HSDIV1_CLKOUT

Bh - MCU_PLL2_HSDIV2_CLKOUT

Ch - MCU_PLL2_HSDIV3_CLKOUT

Dh - MCU_PLL2_HSDIV4_CLKOUT

Eh - HFOSC0_CLKOUT

Fh - WKUP_LFOSC0_CLKOUT

1.1.4.48 CTRLMMR_WKUP_HFOSC1_CTRL Register ( Offset = 8014h) [reset = 80h]

CTRLMMR_WKUP_HFOSC1_CTRL is shown in Figure 5-49 and described in Table 5-106.

Return to Summary Table.

Controls the operation of oscillator 1.

Table 5-105 CTRLMMR_WKUP_HFOSC1_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8014h
Figure 5-49 CTRLMMR_WKUP_HFOSC1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
PD_CRESERVEDBP_CRESERVED
R/W-1hR-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-106 CTRLMMR_WKUP_HFOSC1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7PD_CR/W1h

Oscillator powerdown control. When set, oscillator is disabled. Oscillator output is tristated if bp_c=0

6-5RESERVEDR0h

Reserved

4BP_CR/W0h

Oscillator bypass control. When set oscillator is in bypass mode

3-0RESERVEDR0h

Reserved

1.1.4.49 CTRLMMR_WKUP_HFOSC0_TRIM Register ( Offset = 8018h) [reset = X]

CTRLMMR_WKUP_HFOSC0_TRIM is shown in Figure 5-50 and described in Table 5-108.

Return to Summary Table.

Provides frequency trimming for oscillator 0.

Table 5-107 CTRLMMR_WKUP_HFOSC0_TRIM Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8018h
Figure 5-50 CTRLMMR_WKUP_HFOSC0_TRIM Register
3130292827262524
TRIM_ENRESERVEDFREQ_RNG
R/W-XR-0hR/W-X
2322212019181716
RESERVEDHYSTRESERVEDI_MULT
R-0hR/W-XR-0hR/W-X
15141312111098
RESERVEDR_REF
R-0hR/W-X
76543210
I_IBIAS_COMPR_IBIAS_REF
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-108 CTRLMMR_WKUP_HFOSC0_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31TRIM_ENR/WX

Apply MMR values to OSC trim inputs instead of tie-offs

30-26RESERVEDR0h

Reserved

25-24FREQ_RNGR/WX

Sets the frequency range of operation based on:
I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block, I(AGC) : Current from AGC Loop and mirrored)

0h - I(AMP) - 3x I(MIRRBIAS)

1h - I(AMP)

2h - I(AMP)

3h - I(AMP) + 3x I(MIRRBIAS)

23-22RESERVEDR0h

Reserved

21-20HYSTR/WX

Sets comparator hysteresis

19RESERVEDR0h

Reserved

18-16I_MULTR/WX

AGC AMP current multiplication gain
I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block, I(AGC) : Current from AGC Loop and mirrored)

0h - 3x I(MIRRBIAS)

1h - 4x I(MIRRBIAS)

2h - 5x I(MIRRBIAS)

3h - 6x I(MIRRBIAS)

4h - 7x I(MIRRBIAS)

5h - 8x I(MIRRBIAS)

6h - 9x I(MIRRBIAS)

7h - 10x I(MIRRBIAS)

15-14RESERVEDR0h

Reserved

13-8R_REFR/WX

Sets the AMP AGC bias current
r_ref(5:3) are not used.

0h - 0.00 K-Ohm

1h - 3.1548 K-Ohm

2h - 6.3048 K-Ohm

3h - 9.4548 K-Ohm

4h - 12.6048 K-Ohm

5h - 15.7548 K-Ohm

6h - 18.9048 K-Ohm

7h - 22.0548 K-Ohm

7-4I_IBIAS_COMPR/WX

Sets the COMP bias current
x = 1 uA

0h - 40x

1h - 48x

2h - 56x

3h - 64x

4h - 72x

5h - 80x

6h - 88x

7h - 96x

8h - 104x

9h - 112x

Ah - 120x

Bh - 128x

Ch - 136x

Dh - 144x

Eh - 152x

Fh - 160x

3-0R_IBIAS_REFR/WX

Sets the base IBIAS reference

0h - 64 K-Ohm

1h - 72 K-Ohm

2h - 80 K-Ohm

3h - 88 K-Ohm

4h - 96 K-Ohm

5h - 104 K-Ohm

6h - 112 K-Ohm

7h - 120 K-Ohm

8h - 128 K-Ohm

9h - 136 K-Ohm

Ah - 144 K-Ohm

Bh - 152 K-Ohm

Ch - 160 K-Ohm

Dh - 168 K-Ohm

Eh - 176 K-Ohm

Fh - 184 K-Ohm

1.1.4.50 CTRLMMR_WKUP_HFOSC1_TRIM Register ( Offset = 801Ch) [reset = X]

CTRLMMR_WKUP_HFOSC1_TRIM is shown in Figure 5-51 and described in Table 5-110.

Return to Summary Table.

Provides frequency trimming for oscillator 1.

Table 5-109 CTRLMMR_WKUP_HFOSC1_TRIM Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 801Ch
Figure 5-51 CTRLMMR_WKUP_HFOSC1_TRIM Register
3130292827262524
TRIM_ENRESERVEDFREQ_RNG
R/W-XR-0hR/W-X
2322212019181716
RESERVEDHYSTRESERVEDI_MULT
R-0hR/W-XR-0hR/W-X
15141312111098
RESERVEDR_REF
R-0hR/W-X
76543210
I_IBIAS_COMPR_IBIAS_REF
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-110 CTRLMMR_WKUP_HFOSC1_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31TRIM_ENR/WX

Apply MMR values to OSC trim inputs instead of tie-offs

30-26RESERVEDR0h

Reserved

25-24FREQ_RNGR/WX

Sets the frequency range of operation based on:
I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block, I(AGC) : Current from AGC Loop and mirrored)

0h - I(AMP) - 3x I(MIRRBIAS)

1h - I(AMP)

2h - I(AMP)

3h - I(AMP) + 3x I(MIRRBIAS)

23-22RESERVEDR0h

Reserved

21-20HYSTR/WX

Sets comparator hysteresis

19RESERVEDR0h

Reserved

18-16I_MULTR/WX

AGC AMP current multiplication gain
I(MIRRBIAS) = I(AGC) + 4x I(BIAS) (I(BIAS) : Bias current to AMP_AGC Block, I(AGC) : Current from AGC Loop and mirrored)

0h - 3x I(MIRRBIAS)

1h - 4x I(MIRRBIAS)

2h - 5x I(MIRRBIAS)

3h - 6x I(MIRRBIAS)

4h - 7x I(MIRRBIAS)

5h - 8x I(MIRRBIAS)

6h - 9x I(MIRRBIAS)

7h - 10x I(MIRRBIAS)

15-14RESERVEDR0h

Reserved

13-8R_REFR/WX

Sets the AMP AGC bias current
r_ref(5:3) are not used.

0h - 0.00 K-Ohm

1h - 3.1548 K-Ohm

2h - 6.3048 K-Ohm

3h - 9.4548 K-Ohm

4h - 12.6048 K-Ohm

5h - 15.7548 K-Ohm

6h - 18.9048 K-Ohm

7h - 22.0548 K-Ohm

7-4I_IBIAS_COMPR/WX

Sets the COMP bias current
x = 1 uA

0h - 40x

1h - 48x

2h - 56x

3h - 64x

4h - 72x

5h - 80x

6h - 88x

7h - 96x

8h - 104x

9h - 112x

Ah - 120x

Bh - 128x

Ch - 136x

Dh - 144x

Eh - 152x

Fh - 160x

3-0R_IBIAS_REFR/WX

Sets the base IBIAS reference

0h - 64 K-Ohm

1h - 72 K-Ohm

2h - 80 K-Ohm

3h - 88 K-Ohm

4h - 96 K-Ohm

5h - 104 K-Ohm

6h - 112 K-Ohm

7h - 120 K-Ohm

8h - 128 K-Ohm

9h - 136 K-Ohm

Ah - 144 K-Ohm

Bh - 152 K-Ohm

Ch - 160 K-Ohm

Dh - 168 K-Ohm

Eh - 176 K-Ohm

Fh - 184 K-Ohm

1.1.4.51 CTRLMMR_WKUP_RC12M_OSC_TRIM Register ( Offset = 8024h) [reset = X]

CTRLMMR_WKUP_RC12M_OSC_TRIM is shown in Figure 5-52 and described in Table 5-112.

Return to Summary Table.

Provides frequency trimming for the 12.5 MHz RC oscillator module.

Table 5-111 CTRLMMR_WKUP_RC12M_OSC_TRIM Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8024h
Figure 5-52 CTRLMMR_WKUP_RC12M_OSC_TRIM Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIMOSC_COARSE_DIRTRIMOSC_COARSETRIMOSC_FINE
R-0hR/W-XR/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-112 CTRLMMR_WKUP_RC12M_OSC_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0h

Reserved

6TRIMOSC_COARSE_DIRR/WX

Coarse adjustment direction. If output is greater than 12.5
0h - Coarse adjustment decreases frequency
1h - Coarse adjustment increases frequency

5-3TRIMOSC_COARSER/WX

Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value.

2-0TRIMOSC_FINER/WX

Fine adjustment. Decreases the frequency by 250 KHz per value.

1.1.4.52 CTRLMMR_WKUP_MCU_PLL_CLKSEL Register ( Offset = 8050h) [reset = 800000h]

CTRLMMR_WKUP_MCU_PLL_CLKSEL is shown in Figure 5-53 and described in Table 5-114.

Return to Summary Table.

Controls the clock source for MCU voltage domain PLL[2:0].

Table 5-113 CTRLMMR_WKUP_MCU_PLL_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8050h
Figure 5-53 CTRLMMR_WKUP_MCU_PLL_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-1hR-0h
15141312111098
RESERVEDCLKLOSS_SWTCH_EN
R-0hR/W-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-114 CTRLMMR_WKUP_MCU_PLL_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
When set, enables software control of exit from bypass mode on a mcu_reset_z for MCU PLL[2:0]. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W1h

PLL bypass mode after warm reset.
This bit is only valid when bypass_sw_ovrd is set to 1h to enable bypass software override.
This bit is set (1h) when an MCU warm reset occurs and will keep MCU PLL[2:0] in bypass mode after reset exit until cleared by software.
0h - Exit bypass mode (based on MCU PLL[2:0]_CTRL_bypass_en bit value)
1h = Maintain bypass mode.

22-9RESERVEDR0h

Reserved

8CLKLOSS_SWTCH_ENR/W0h

When set, enables automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected

7-0RESERVEDR0h

Reserved

1.1.4.53 CTRLMMR_WKUP_PER_CLKSEL Register ( Offset = 8060h) [reset = 0h]

CTRLMMR_WKUP_PER_CLKSEL is shown in Figure 5-54 and described in Table 5-116.

Return to Summary Table.

Controls the wakeup peripheral functional clock source. Allows the main oscillator to be used as the functional clock source for the WKUP_USART and WKUP_I2C when PLLs are powered down.

Table 5-115 CTRLMMR_WKUP_PER_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8060h
Figure 5-54 CTRLMMR_WKUP_PER_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMCUPLL_BYPASS
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-116 CTRLMMR_WKUP_PER_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0MCUPLL_BYPASSR/W0h

Select the main oscillator clock rather than the PLL generated clock as the functional clock (PLL BYPASS mode).

0h - WKUP_I2C functional clock is MCU_PLL1_HSDIV3_CLKOUT
WKUP_USART functional clock is MCU_PLL1_HSDIV3_CLKOUT or MAIN_PLL_HSDIV5_CLKOUT as selected by CTRLMMR_WKUP_USART_CLKSEL.clk_sel

1h:
WKUP_I2C functional clock is HFOSC0_CLKOUT
WKUP_USART functional clock is HFOSC0_CLKOUT

1.1.4.54 CTRLMMR_WKUP_USART_CLKSEL Register ( Offset = 8064h) [reset = 0h]

CTRLMMR_WKUP_USART_CLKSEL is shown in Figure 5-55 and described in Table 5-118.

Return to Summary Table.

Controls the functional clock source for WKUP_USART0.

Table 5-117 CTRLMMR_WKUP_USART_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8064h
Figure 5-55 CTRLMMR_WKUP_USART_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-118 CTRLMMR_WKUP_USART_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

WKUP_USART0 FCLK selection
0h - MCU_PLL1_HSDIV3_CLKOUT
1h - MAIN_PLL_HSDIV5_CLKOUT

1.1.4.55 CTRLMMR_WKUP_GPIO_CLKSEL Register ( Offset = 8070h) [reset = 0h]

CTRLMMR_WKUP_GPIO_CLKSEL is shown in Figure 5-56 and described in Table 5-120.

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Controls the functional clock source for WKUP_GPIO.

Table 5-119 CTRLMMR_WKUP_GPIO_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8070h
Figure 5-56 CTRLMMR_WKUP_GPIO_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWAKE_CLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-120 CTRLMMR_WKUP_GPIO_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0WAKE_CLK_SELR/W0h

WKUP_GPIO clock selection. Must be set to MCU_SYSCLK0/6 whenever WKUP_GPIO VBUS interface is enabled. Other clock source may be selected as a wake up clock for DeepSleep modes after WKUP_GPIO is gated off through LPSC.

0h - MCU_SYSCLK0 / 6

1h - MCU_SYSCLK0 / 6

2h - CLK_32K

3h - CLK_12M_RC

1.1.4.56 CTRLMMR_WKUP_MAIN_PLL0_CLKSEL Register ( Offset = 8080h) [reset = 800000h]

CTRLMMR_WKUP_MAIN_PLL0_CLKSEL is shown in Figure 5-57 and described in Table 5-122.

Return to Summary Table.

Controls the clock source for MAIN voltage domain PLL0.

Table 5-121 CTRLMMR_WKUP_MAIN_PLL0_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8080h
Figure 5-57 CTRLMMR_WKUP_MAIN_PLL0_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-1hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-122 CTRLMMR_WKUP_MAIN_PLL0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL0. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W1h

PLL bypass mode after warm reset.
This bit is only valid when bypass_sw_ovrd is set to 1h to enable bypass software override.
This bit is set (1h) when a MAIN warm reset occurs and will keep MAIN PLL0 in bypass mode after reset exit until cleared by software.
0h - Exit bypass mode (based on MAIN PLL0_CTRL_bypass_en bit value)
1h = Maintain bypass mode.

22-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL0
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.57 CTRLMMR_WKUP_MAIN_PLL1_CLKSEL Register ( Offset = 8084h) [reset = 0h]

CTRLMMR_WKUP_MAIN_PLL1_CLKSEL is shown in Figure 5-58 and described in Table 5-124.

Return to Summary Table.

Controls the clock source for MAIN voltage domain PLL1.

Table 5-123 CTRLMMR_WKUP_MAIN_PLL1_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8084h
Figure 5-58 CTRLMMR_WKUP_MAIN_PLL1_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-124 CTRLMMR_WKUP_MAIN_PLL1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W0h

PLL bypass mode after warm reset.
This bit is cleared to 0h when a MAIN warm reset occurs which will cause MAIN PLL1 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because MAIN PLL1 is warm reset insensitive, bypass mode will only be entered (and exited) in the case of a Thermal reset event.

22-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL1
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.58 CTRLMMR_WKUP_MAIN_PLL2_CLKSEL Register ( Offset = 8088h) [reset = 0h]

CTRLMMR_WKUP_MAIN_PLL2_CLKSEL is shown in Figure 5-59 and described in Table 5-126.

Return to Summary Table.

Controls the clock source for MAIN voltage domain PLL2.

Table 5-125 CTRLMMR_WKUP_MAIN_PLL2_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8088h
Figure 5-59 CTRLMMR_WKUP_MAIN_PLL2_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-126 CTRLMMR_WKUP_MAIN_PLL2_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W0h

PLL bypass mode after warm reset.
This bit is cleared to 0h when a MAIN warm reset occurs which will cause MAIN PLL2 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because MAIN PLL2 is warm reset insensitive, bypass mode will only be entered (and exited) in the case of a Thermal reset event.

22-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL2
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.59 CTRLMMR_WKUP_MAIN_PLL3_CLKSEL Register ( Offset = 808Ch) [reset = 0h]

CTRLMMR_WKUP_MAIN_PLL3_CLKSEL is shown in Figure 5-60 and described in Table 5-128.

Return to Summary Table.

Controls the clock source for MAIN voltage domain PLL3.

Table 5-127 CTRLMMR_WKUP_MAIN_PLL3_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 808Ch
Figure 5-60 CTRLMMR_WKUP_MAIN_PLL3_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-128 CTRLMMR_WKUP_MAIN_PLL3_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
This bit has no effect on PLL operation as MAIN PLL3 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W0h

PLL bypass mode after warm reset.
This bit is cleared to 0h when a MAIN warm reset occurs which will cause MAIN PLL3 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behavior. Because MAIN PLL3 is warm reset insensitive, bypass mode will only be entered (and exited) in the case of a Thermal reset event.

22-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL3
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.60 CTRLMMR_WKUP_MAIN_PLL4_CLKSEL Register ( Offset = 8090h) [reset = 800000h]

CTRLMMR_WKUP_MAIN_PLL4_CLKSEL is shown in Figure 5-61 and described in Table 5-130.

Return to Summary Table.

Controls the clock source for MAIN voltage domain PLL4.

Table 5-129 CTRLMMR_WKUP_MAIN_PLL4_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8090h
Figure 5-61 CTRLMMR_WKUP_MAIN_PLL4_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-1hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDXREF_SELRESERVEDCLK_SEL
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-130 CTRLMMR_WKUP_MAIN_PLL4_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL4. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W1h

PLL bypass mode after warm reset.
This bit is only valid when bypass_sw_ovrd is set to 1h to enable bypass software override.
This bit is set (1h) when a MAIN warm reset occurs and will keep MAIN PLL4 in bypass mode after reset exit until cleared by software.
0h - Exit bypass mode (based on MAIN PLL4_CTRL_bypass_en bit value)
1h = Maintain bypass mode.

22-5RESERVEDR0h

Reserved

4XREF_SELR/W0h

Selects the alternate clock source for MAIN PLL4
0h - Use HFOSC0_CLKOUT or HFOSC1 CLKOUT as selected by clk_sel bit
1h - Use EXT_REFCLK1

3-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL4
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.61 CTRLMMR_WKUP_MAIN_PLL7_CLKSEL Register ( Offset = 809Ch) [reset = 800000h]

CTRLMMR_WKUP_MAIN_PLL7_CLKSEL is shown in Figure 5-62 and described in Table 5-132.

Return to Summary Table.

Controls the clock source for MAIN voltage domain PLL7.

Table 5-131 CTRLMMR_WKUP_MAIN_PLL7_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 809Ch
Figure 5-62 CTRLMMR_WKUP_MAIN_PLL7_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-1hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-132 CTRLMMR_WKUP_MAIN_PLL7_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL7. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W1h

PLL bypass mode after warm reset.
This bit is only valid when bypass_sw_ovrd is set to 1h to enable bypass software override.
This bit is set (1h) when a MAIN warm reset occurs and will keep MAIN PLL7 in bypass mode after reset exit until cleared by software.
0h - Exit bypass mode (based on MAIN PLL7_CTRL_bypass_en bit value)
1h = Maintain bypass mode.

22-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL7
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.62 CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register ( Offset = 80A0h) [reset = 800000h]

CTRLMMR_WKUP_MAIN_PLL8_CLKSEL is shown in Figure 5-63 and described in Table 5-134.

Return to Summary Table.

Controls the clock source for MAIN voltage domain PLL8.

Table 5-133 CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 80A0h
Figure 5-63 CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-1hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-134 CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL8. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W1h

PLL bypass mode after warm reset.
This bit is only valid when bypass_sw_ovrd is set to 1h to enable bypass software override.
This bit is set (1h) when a MAIN warm reset occurs and will keep MAIN PLL8 in bypass mode after reset exit until cleared by software.
0h - Exit bypass mode (based on MAIN PLL8_CTRL_bypass_en bit value)
1h = Maintain bypass mode.

22-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL8
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.63 CTRLMMR_WKUP_MAIN_PLL12_CLKSEL Register ( Offset = 80B0h) [reset = 800000h]

CTRLMMR_WKUP_MAIN_PLL12_CLKSEL is shown in Figure 5-64 and described in Table 5-136.

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Controls the clock source for MAIN voltage domain PLL12.

Table 5-135 CTRLMMR_WKUP_MAIN_PLL12_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 80B0h
Figure 5-64 CTRLMMR_WKUP_MAIN_PLL12_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-1hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-136 CTRLMMR_WKUP_MAIN_PLL12_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL12. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W1h

PLL bypass mode after warm reset.
This bit is only valid when bypass_sw_ovrd is set to 1h to enable bypass software override.
This bit is set (1h) when a MAIN warm reset occurs and will keep MAIN PLL12 in bypass mode after reset exit until cleared by software.
0h - Exit bypass mode (based on MAIN PLL12_CTRL_bypass_en bit value)
1h = Maintain bypass mode.

22-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL12
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.64 CTRLMMR_WKUP_MAIN_PLL14_CLKSEL Register ( Offset = 80B8h) [reset = 800000h]

CTRLMMR_WKUP_MAIN_PLL14_CLKSEL is shown in Figure 5-65 and described in Table 5-138.

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Controls the clock source for MAIN voltage domain PLL14.

Table 5-137 CTRLMMR_WKUP_MAIN_PLL14_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 80B8h
Figure 5-65 CTRLMMR_WKUP_MAIN_PLL14_CLKSEL Register
3130292827262524
BYPASS_SW_OVRDRESERVED
R/W-0hR-0h
2322212019181716
BYP_WARM_RSTRESERVED
R/W-1hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-138 CTRLMMR_WKUP_MAIN_PLL14_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31BYPASS_SW_OVRDR/W0h

PLL Bypass warm reset software override
When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL14. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.

30-24RESERVEDR0h

Reserved

23BYP_WARM_RSTR/W1h

PLL bypass mode after warm reset.
This bit is only valid when bypass_sw_ovrd is set to 1h to enable bypass software override.
This bit is set (1h) when a MAIN warm reset occurs and will keep MAIN PLL14 in bypass mode after reset exit until cleared by software.
0h - Exit bypass mode (based on MAIN PLL14_CTRL_bypass_en bit value)
1h = Maintain bypass mode.

22-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source for MAIN PLL14
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.1.4.65 CTRLMMR_WKUP_MAIN_SYSCLK_CTRL Register ( Offset = 8100h) [reset = 0h]

CTRLMMR_WKUP_MAIN_SYSCLK_CTRL is shown in Figure 5-66 and described in Table 5-140.

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Controls clock gating of the MAIN PLL Controller SYSCLK outputs.

Table 5-139 CTRLMMR_WKUP_MAIN_SYSCLK_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8100h
Figure 5-66 CTRLMMR_WKUP_MAIN_SYSCLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSYSCLK1_GATE
R-0hR/W-0h
76543210
RESERVEDSYSCLK0_GATE
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-140 CTRLMMR_WKUP_MAIN_SYSCLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8SYSCLK1_GATER/W0h

When set, gates off SYSCLK1 output of the MAIN PLL Controller

7-1RESERVEDR0h

Reserved

0SYSCLK0_GATER/W0h

When set, gates off SYSCLK0 (MCLK1) output of the MAIN PLL Controller

1.1.4.66 CTRLMMR_WKUP_MCU_SPI0_CLKSEL Register ( Offset = 8110h) [reset = 0h]

CTRLMMR_WKUP_MCU_SPI0_CLKSEL is shown in Figure 5-67 and described in Table 5-142.

Return to Summary Table.

MCU_SPI0 clock control.

Table 5-141 CTRLMMR_WKUP_MCU_SPI0_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8110h
Figure 5-67 CTRLMMR_WKUP_MCU_SPI0_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-142 CTRLMMR_WKUP_MCU_SPI0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.1.4.67 CTRLMMR_WKUP_MCU_SPI1_CLKSEL Register ( Offset = 8114h) [reset = 0h]

CTRLMMR_WKUP_MCU_SPI1_CLKSEL is shown in Figure 5-68 and described in Table 5-144.

Return to Summary Table.

MCU_SPI1 clock control.

Table 5-143 CTRLMMR_WKUP_MCU_SPI1_CLKSEL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 8114h
Figure 5-68 CTRLMMR_WKUP_MCU_SPI1_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-144 CTRLMMR_WKUP_MCU_SPI1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.1.4.68 CTRLMMR_WKUP_LOCK2_KICK0 Register ( Offset = 9008h) [reset = 0h]

CTRLMMR_WKUP_LOCK2_KICK0 is shown in Figure 5-69 and described in Table 5-146.

Return to Summary Table.

Lower 32-bits of Partition2 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_WKUP_LOCK2_KICK1 with its key value before write-protected Partition 2 registers can be written.

Table 5-145 CTRLMMR_WKUP_LOCK2_KICK0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 9008h
Figure 5-69 CTRLMMR_WKUP_LOCK2_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-146 CTRLMMR_WKUP_LOCK2_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers

0UNLOCKEDR0h

Unlock status.
When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.4.69 CTRLMMR_WKUP_LOCK2_KICK1 Register ( Offset = 900Ch) [reset = 0h]

CTRLMMR_WKUP_LOCK2_KICK1 is shown in Figure 5-70 and described in Table 5-148.

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Upper 32-bits of Partition 2 write lock key. This register must be written with the designated key value after a write to CTRLMMR_WKUP_LOCK2_KICK0 with its key value before write-protected Partition 2 registers can be written.

Table 5-147 CTRLMMR_WKUP_LOCK2_KICK1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 900Ch
Figure 5-70 CTRLMMR_WKUP_LOCK2_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-148 CTRLMMR_WKUP_LOCK2_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers

1.1.4.70 CTRLMMR_WKUP_DMSC_LBIST_SIG Register ( Offset = C280h) [reset = X]

CTRLMMR_WKUP_DMSC_LBIST_SIG is shown in Figure 5-71 and described in Table 5-150.

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Contains expected MISR output value.

Table 5-149 CTRLMMR_WKUP_DMSC_LBIST_SIG Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 C280h
Figure 5-71 CTRLMMR_WKUP_DMSC_LBIST_SIG Register
313029282726252423222120191817161514131211109876543210
MISR_SIG
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-150 CTRLMMR_WKUP_DMSC_LBIST_SIG Register Field Descriptions
BitFieldTypeResetDescription
31-0MISR_SIGRX

MISR signature

1.1.4.71 CTRLMMR_WKUP_POST_STAT Register ( Offset = C2C0h) [reset = X]

CTRLMMR_WKUP_POST_STAT is shown in Figure 5-72 and described in Table 5-152.

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Contains the result of power-on self tests.

Table 5-151 CTRLMMR_WKUP_POST_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 C2C0h
Figure 5-72 CTRLMMR_WKUP_POST_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDFPOST_PLL_LOCK_TIMEOUTFPOST_PLL_LOCKLOSS
R-0hR-XR-X
15141312111098
POST_MCU_PBIST_FAILRESERVEDPOST_MCU_PBIST_TIMEOUTPOST_MCU_PBIST_DONE
R-XR-0hR-XR-X
76543210
RESERVEDPOST_MCU_LBIST_TIMEOUTPOST_DMSC_LBIST_TIMEOUTRESERVEDPOST_MCU_LBIST_DONEPOST_DMSC_LBIST_DONE
R-0hR-XR-XR-0hR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-152 CTRLMMR_WKUP_POST_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h

Reserved

17FPOST_PLL_LOCK_TIMEOUTRX

Indicates PLL lock timeout for Fast POST mode operation.
0h - PLLs locked, Fast POST mode was entered
1h - PLLs lock timeout occurred. Slow speed POST was performed

16FPOST_PLL_LOCKLOSSRX

Indicates if PLL lock was lost during POST
0h - No PLL lock loss. Fast POST was executed
1h - PLL lock was lost. POST was terminated

15POST_MCU_PBIST_FAILRX

MCU PBIST failed

14-10RESERVEDR0h

Reserved

9POST_MCU_PBIST_TIMEOUTRX

MCU PBIST timed out

8POST_MCU_PBIST_DONERX

MCU PBIST done

7-6RESERVEDR0h

Reserved

5POST_MCU_LBIST_TIMEOUTRX

MCU LBIST timed out

4POST_DMSC_LBIST_TIMEOUTRX

DMSC LBIST timed out

3-2RESERVEDR0h

Reserved

1POST_MCU_LBIST_DONERX

MCU LBIST done

0POST_DMSC_LBIST_DONERX

DMSC LBIST done

1.1.4.72 CTRLMMR_WKUP_FUSE_CRC_STAT Register ( Offset = C320h) [reset = X]

CTRLMMR_WKUP_FUSE_CRC_STAT is shown in Figure 5-73 and described in Table 5-154.

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Indicates status of fuse chain CRC.

Table 5-153 CTRLMMR_WKUP_FUSE_CRC_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 C320h
Figure 5-73 CTRLMMR_WKUP_FUSE_CRC_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCRC_ERR_2CRC_ERR_1RESERVED
R-0hR-XR-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-154 CTRLMMR_WKUP_FUSE_CRC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2CRC_ERR_2RX

Indicates eFuse CRC error on chain 2

1CRC_ERR_1RX

Indicates eFuse CRC error on chain 1

0RESERVEDR0h

Reserved

1.1.4.73 CTRLMMR_WKUP_LOCK3_KICK0 Register ( Offset = D008h) [reset = 0h]

CTRLMMR_WKUP_LOCK3_KICK0 is shown in Figure 5-74 and described in Table 5-156.

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Lower 32-bits of Partition3 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_WKUP_LOCK3_KICK1 with its key value before write-protected Partition 3 registers can be written.

Table 5-155 CTRLMMR_WKUP_LOCK3_KICK0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 D008h
Figure 5-74 CTRLMMR_WKUP_LOCK3_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-156 CTRLMMR_WKUP_LOCK3_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers

0UNLOCKEDR0h

Unlock status.
When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.4.74 CTRLMMR_WKUP_LOCK3_KICK1 Register ( Offset = D00Ch) [reset = 0h]

CTRLMMR_WKUP_LOCK3_KICK1 is shown in Figure 5-75 and described in Table 5-158.

Return to Summary Table.

Upper 32-bits of Partition 3 write lock key. This register must be written with the designated key value after a write to CTRLMMR_WKUP_LOCK3_KICK0 with its key value before write-protected Partition 3 registers can be written.

Table 5-157 CTRLMMR_WKUP_LOCK3_KICK1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04300 D00Ch
Figure 5-75 CTRLMMR_WKUP_LOCK3_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-158 CTRLMMR_WKUP_LOCK3_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers

1.1.4.75 CTRLMMR_WKUP_LOCK4_KICK0 Register ( Offset = 11008h) [reset = 0h]

CTRLMMR_WKUP_LOCK4_KICK0 is shown in Figure 5-76 and described in Table 5-160.

Return to Summary Table.

Lower 32-bits of Partition4 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_WKUP_LOCK4_KICK1 with its key value before write-protected Partition 4 registers can be written.

Table 5-159 CTRLMMR_WKUP_LOCK4_KICK0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 1008h
Figure 5-76 CTRLMMR_WKUP_LOCK4_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-160 CTRLMMR_WKUP_LOCK4_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers

0UNLOCKEDR0h

Unlock status.
When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.4.76 CTRLMMR_WKUP_LOCK4_KICK1 Register ( Offset = 1100Ch) [reset = 0h]

CTRLMMR_WKUP_LOCK4_KICK1 is shown in Figure 5-77 and described in Table 5-162.

Return to Summary Table.

Upper 32-bits of Partition 4 write lock key. This register must be written with the designated key value after a write to CTRLMMR_WKUP_LOCK4_KICK0 with its key value before write-protected Partition 4 registers can be written.

Table 5-161 CTRLMMR_WKUP_LOCK4_KICK1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 100Ch
Figure 5-77 CTRLMMR_WKUP_LOCK4_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-162 CTRLMMR_WKUP_LOCK4_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition4 registers

1.1.4.77 CTRLMMR_WKUP_POR_CTRL Register ( Offset = 18000h) [reset = 10h]

CTRLMMR_WKUP_POR_CTRL is shown in Figure 5-78 and described in Table 5-164.

Return to Summary Table.

Configures POR module reset behavior.

Table 5-163 CTRLMMR_WKUP_POR_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8000h
Figure 5-78 CTRLMMR_WKUP_POR_CTRL Register
3130292827262524
RESERVEDOVRD_SET5OVRD_SET4OVRD_SET3OVRD_SET2OVRD_SET1OVRD_SET0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDOVRD5OVRD4OVRD3OVRD2OVRD1OVRD0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
TRIM_SELRESERVEDMASK_HHVRESERVED
R/W-0hR-0hR/W-1hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-164 CTRLMMR_WKUP_POR_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h

Reserved

29OVRD_SET5R/W0h

Reserved override set

28OVRD_SET4R/W0h

POKLVB override set

27OVRD_SET3R/W0h

POKLVA override set

26OVRD_SET2R/W0h

POKHV override set

25OVRD_SET1R/W0h

BGOK override set

24OVRD_SET0R/W0h

PORHV override set

23-22RESERVEDR0h

Reserved

21OVRD5R/W0h

Reserved override enable

20OVRD4R/W0h

POKLVB override enable

19OVRD3R/W0h

POKLVA override enable

18OVRD2R/W0h

POKHV override enable

17OVRD1R/W0h

BGOK override enable

16OVRD0R/W0h

PORHV override enable

15-8RESERVEDR0h

Reserved

7TRIM_SELR/W0h

POR Trim Select
0h - Trim selections for Bandgap and POKs come from HHV defaults
1h - Trim selections for Bandgap and POKs come from
CTRLMMR_WKUP_POR_BANDGAP_CTRL and POR_POKxxx_CTRL registers

6-5RESERVEDR0h

Reserved

4MASK_HHVR/W1h

Mask HHV/SOC_PORz outputs when applying new trim values

3-0RESERVEDR0h

Reserved

1.1.4.78 CTRLMMR_WKUP_POR_STAT Register ( Offset = 18004h) [reset = X]

CTRLMMR_WKUP_POR_STAT is shown in Figure 5-79 and described in Table 5-166.

Return to Summary Table.

Shows POR module status.

Table 5-165 CTRLMMR_WKUP_POR_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8004h
Figure 5-79 CTRLMMR_WKUP_POR_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDBGOK
R-0hR-X
76543210
RESERVEDSOC_PORRESERVED
R-0hR-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-166 CTRLMMR_WKUP_POR_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8BGOKRX

Bandgap OK status

7-5RESERVEDR0h

Reserved

4SOC_PORRX

POR module status
0h - Module is in functional mode
1h - Module is in reset mode

3-0RESERVEDR0h

Reserved

1.1.4.79 CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL Register ( Offset = 18010h) [reset = 80000000h]

CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL is shown in Figure 5-80 and described in Table 5-168.

Return to Summary Table.

Controls operation of the VDDA_PMIC_IN POK module.

Table 5-167 CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8010h
Figure 5-80 CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDOVER_VOLT_DET
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-168 CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-1RESERVEDR0h

Reserved

0OVER_VOLT_DETR/W0h

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

1.1.4.80 CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL Register ( Offset = 18014h) [reset = X]

CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL is shown in Figure 5-81 and described in Table 5-170.

Return to Summary Table.

Controls operation of the VDDSHV_WKUP_GENERAL POK undervoltage detection.

Table 5-169 CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8014h
Figure 5-81 CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-170 CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.81 CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL Register ( Offset = 18018h) [reset = X]

CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL is shown in Figure 5-82 and described in Table 5-172.

Return to Summary Table.

Controls operation of the VDDR_MCU POK undervoltage detection.

Table 5-171 CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8018h
Figure 5-82 CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-172 CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.82 CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_UV_CTRL Register ( Offset = 1801Ch) [reset = X]

CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_UV_CTRL is shown in Figure 5-83 and described in Table 5-174.

Return to Summary Table.

Controls operation of the VMON_CAP_MCU_GENERAL POK undervoltage detection.

Table 5-173 CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 801Ch
Figure 5-83 CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-174 CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.83 CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL Register ( Offset = 18020h) [reset = X]

CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL is shown in Figure 5-84 and described in Table 5-176.

Return to Summary Table.

Controls operation of the VDD_MCU overvoltage POK module.

Table 5-175 CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8020h
Figure 5-84 CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-176 CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.84 CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL Register ( Offset = 18024h) [reset = X]

CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL is shown in Figure 5-85 and described in Table 5-178.

Return to Summary Table.

Controls operation of the VDDSHV_WKUP_GENERAL POK overvoltage detection.

Table 5-177 CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8024h
Figure 5-85 CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-178 CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.85 CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL Register ( Offset = 18028h) [reset = X]

CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL is shown in Figure 5-86 and described in Table 5-180.

Return to Summary Table.

Controls operation of the VDDR_MCU POK overvoltage detection.

Table 5-179 CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8028h
Figure 5-86 CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-180 CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.86 CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_OV_CTRL Register ( Offset = 1802Ch) [reset = X]

CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_OV_CTRL is shown in Figure 5-87 and described in Table 5-182.

Return to Summary Table.

Controls operation of the VMON_CAP_MCU_GENERAL POK overvoltage detection.

Table 5-181 CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 802Ch
Figure 5-87 CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-182 CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.87 CTRLMMR_WKUP_MAIN_VDOM_CTRL Register ( Offset = 18070h) [reset = 0h]

CTRLMMR_WKUP_MAIN_VDOM_CTRL is shown in Figure 5-88 and described in Table 5-184.

Return to Summary Table.

Provides MAIN voltage domain isolation for deep sleep operation.

Table 5-183 CTRLMMR_WKUP_MAIN_VDOM_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8070h
Figure 5-88 CTRLMMR_WKUP_MAIN_VDOM_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMAIN_VD_OFF
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-184 CTRLMMR_WKUP_MAIN_VDOM_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0MAIN_VD_OFFR/W0h

MAIN deep sleep isolation enable. This bit should be set prior to powering off the MAIN voltage domain to ensure proper signal isolation.

1.1.4.88 CTRLMMR_WKUP_POR_POKHV_UV_CTRL Register ( Offset = 18080h) [reset = X]

CTRLMMR_WKUP_POR_POKHV_UV_CTRL is shown in Figure 5-89 and described in Table 5-186.

Return to Summary Table.

Controls operation of the 1.8V VDDA_MCU undervoltage POK within the POR.

Table 5-185 CTRLMMR_WKUP_POR_POKHV_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8080h
Figure 5-89 CTRLMMR_WKUP_POR_POKHV_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-186 CTRLMMR_WKUP_POR_POKHV_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.89 CTRLMMR_WKUP_POR_POKLVB_UV_CTRL Register ( Offset = 18084h) [reset = X]

CTRLMMR_WKUP_POR_POKLVB_UV_CTRL is shown in Figure 5-90 and described in Table 5-188.

Return to Summary Table.

Controls operation of the VDD_MCU undervoltage POK within the POR.

Table 5-187 CTRLMMR_WKUP_POR_POKLVB_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8084h
Figure 5-90 CTRLMMR_WKUP_POR_POKLVB_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-188 CTRLMMR_WKUP_POR_POKLVB_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.90 CTRLMMR_WKUP_POR_POKLVA_OV_CTRL Register ( Offset = 18088h) [reset = X]

CTRLMMR_WKUP_POR_POKLVA_OV_CTRL is shown in Figure 5-91 and described in Table 5-190.

Return to Summary Table.

Controls operation of the 1.8V VDDA_MCU overvoltage POK within the POR.

Table 5-189 CTRLMMR_WKUP_POR_POKLVA_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8088h
Figure 5-91 CTRLMMR_WKUP_POR_POKLVA_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-190 CTRLMMR_WKUP_POR_POKLVA_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.91 CTRLMMR_WKUP_POR_BANDGAP_CTRL Register ( Offset = 1808Ch) [reset = X]

CTRLMMR_WKUP_POR_BANDGAP_CTRL is shown in Figure 5-92 and described in Table 5-192.

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Controls the operation of the bandgap module within the POR.

Table 5-191 CTRLMMR_WKUP_POR_BANDGAP_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 808Ch
Figure 5-92 CTRLMMR_WKUP_POR_BANDGAP_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDBGAPI
R-0hR/W-X
15141312111098
BGAPV
R/W-X
76543210
BGAPC
R/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-192 CTRLMMR_WKUP_POR_BANDGAP_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h

Reserved

19-16BGAPIR/WX

Bandgap output current trim bits

15-8BGAPVR/WX

Bandgap output voltage magnitude trim bits

7-0BGAPCR/WX

Bandgap slope trim bits. Bit7 is used to calculate the offset

1.1.4.92 CTRLMMR_WKUP_TEMP_DIODE_TRIM Register ( Offset = 180A0h) [reset = X]

CTRLMMR_WKUP_TEMP_DIODE_TRIM is shown in Figure 5-93 and described in Table 5-194.

Return to Summary Table.

Trims the silicon junction temperature diode calculation.

Table 5-193 CTRLMMR_WKUP_TEMP_DIODE_TRIM Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 80A0h
Figure 5-93 CTRLMMR_WKUP_TEMP_DIODE_TRIM Register
313029282726252423222120191817161514131211109876543210
RESERVEDTRIM
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-194 CTRLMMR_WKUP_TEMP_DIODE_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0h

Reserved

13-0TRIMR/WX

Sets the diode non-ideality factor (n), starting from 100th place decimal and going down

1.1.4.93 CTRLMMR_WKUP_IO_VOLTAGE_STAT Register ( Offset = 180B0h) [reset = X]

CTRLMMR_WKUP_IO_VOLTAGE_STAT is shown in Figure 5-94 and described in Table 5-196.

Return to Summary Table.

Indicates the I/O voltage of each LVCMOS dual I/O group.

Table 5-195 CTRLMMR_WKUP_IO_VOLTAGE_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 80B0h
Figure 5-94 CTRLMMR_WKUP_IO_VOLTAGE_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMAIN_CANUART
R-0hR-X
15141312111098
RESERVEDMAIN_MMC1MAIN_MMC0MAIN_GEN
R-0hR-XR-XR-X
76543210
RESERVEDMCU_RGMIIMCU_FLASHMCU_GEN
R-0hR-XR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-196 CTRLMMR_WKUP_IO_VOLTAGE_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MAIN_CANUARTRX

Indicates the voltage for the CANUART I/O group
0h - I/O group is set for 1.8V
1h - I/O group is set for 3.3V

15-11RESERVEDR0h

Reserved

10MAIN_MMC1RX

Indicates the voltage for the MMC1 I/O group
0h - I/O group is set for 1.8V
1h - I/O group is set for 3.3V

9MAIN_MMC0RX

Indicates the voltage for the MMC0 I/O group
0h - I/O group is set for 1.8V
1h - I/O group is set for 3.3V

8MAIN_GENRX

Indicates the voltage for the General I/O group
0h - I/O group is set for 1.8V
1h - I/O group is set for 3.3V

7-3RESERVEDR0h

Reserved

2MCU_RGMIIRX

Indicates the voltage for the MCU CPSW2G RGMII I/O group
0h - I/O group is set for 1.8V
1h - I/O group is set for 3.3V

1MCU_FLASHRX

Indicates the voltage for the MCU Flash I/O group
0h - I/O group is set for 1.8V
1h - I/O group is set for 3.3V

0MCU_GENRX

Indicates the voltage for the MCU General I/O group
0h - I/O group is set for 1.8V
1h - I/O group is set for 3.3V

1.1.4.94 CTRLMMR_WKUP_MAIN_POR_TO_CTRL Register ( Offset = 18104h) [reset = X]

CTRLMMR_WKUP_MAIN_POR_TO_CTRL is shown in Figure 5-95 and described in Table 5-198.

Return to Summary Table.

Indicates the MAIN PORz timeout period.

Table 5-197 CTRLMMR_WKUP_MAIN_POR_TO_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8104h
Figure 5-95 CTRLMMR_WKUP_MAIN_POR_TO_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTIMEOUT_PER
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-198 CTRLMMR_WKUP_MAIN_POR_TO_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0TIMEOUT_PERR/WX

MAIN PORz hardware timeout period.
During normal operation, the assertion of a MAIN Domain PORz generates a reset request interrupt to the DMSC. The DMSC then performs steps to properly isolate the MAIN Domain before the actual reset is performed. A hardware timeout mechanism is provided to ensure that the PORz gets propagated to the MAIN Domain in the event that a error prevents the DMSC from completing the reset isolation.

0h - Immediate

1h - 100 microsec

2h - 200 microsec

3h - 300 microsec

4h - 400 microsec

5h - 500 microsec

1.1.4.95 CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL Register ( Offset = 18110h) [reset = X]

CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL is shown in Figure 5-96 and described in Table 5-200.

Return to Summary Table.

Controls operation of the VDD_CORE POK undervoltage detection.

Table 5-199 CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8110h
Figure 5-96 CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-200 CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.96 CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL Register ( Offset = 18114h) [reset = X]

CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL is shown in Figure 5-97 and described in Table 5-202.

Return to Summary Table.

Controls operation of the VDD_CPU POK undervoltage detection.

Table 5-201 CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8114h
Figure 5-97 CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-202 CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.97 CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL Register ( Offset = 18118h) [reset = X]

CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL is shown in Figure 5-98 and described in Table 5-204.

Return to Summary Table.

Controls operation of the VMON_EXTC POK undervoltage detection.

Table 5-203 CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8118h
Figure 5-98 CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-204 CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.98 CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL Register ( Offset = 1811Ch) [reset = X]

CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL is shown in Figure 5-99 and described in Table 5-206.

Return to Summary Table.

Controls operation of the VDDR_CORE POK undervoltage detection.

Table 5-205 CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 811Ch
Figure 5-99 CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-206 CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.99 CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL Register ( Offset = 18120h) [reset = X]

CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL is shown in Figure 5-100 and described in Table 5-208.

Return to Summary Table.

Controls operation of the VDD_CORE POK overvoltage detection.

Table 5-207 CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8120h
Figure 5-100 CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-208 CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.100 CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL Register ( Offset = 18124h) [reset = X]

CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL is shown in Figure 5-101 and described in Table 5-210.

Return to Summary Table.

Controls operation of the VDD_CPU POK overvoltage detection.

Table 5-209 CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8124h
Figure 5-101 CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-210 CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.101 CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL Register ( Offset = 18128h) [reset = X]

CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL is shown in Figure 5-102 and described in Table 5-212.

Return to Summary Table.

Controls operation of the VMON_EXT POK overvoltage detection.

Table 5-211 CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8128h
Figure 5-102 CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-212 CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.102 CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL Register ( Offset = 1812Ch) [reset = X]

CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL is shown in Figure 5-103 and described in Table 5-214.

Return to Summary Table.

Controls operation of the VDDR_CORE POK overvoltage detection.

Table 5-213 CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 812Ch
Figure 5-103 CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-214 CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.103 CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_UV_CTRL Register ( Offset = 18130h) [reset = X]

CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_UV_CTRL is shown in Figure 5-104 and described in Table 5-216.

Return to Summary Table.

Controls operation of the VMON_EXT_MAIN1P8 POK undervoltage detection.

Table 5-215 CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8130h
Figure 5-104 CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-216 CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.104 CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_OV_CTRL Register ( Offset = 18134h) [reset = X]

CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_OV_CTRL is shown in Figure 5-105 and described in Table 5-218.

Return to Summary Table.

Controls operation of the VMON_EXT_MAIN1P8 POK overvoltage detection.

Table 5-217 CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8134h
Figure 5-105 CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-218 CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.105 CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_UV_CTRL Register ( Offset = 18138h) [reset = X]

CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_UV_CTRL is shown in Figure 5-106 and described in Table 5-220.

Return to Summary Table.

Controls operation of the VMON_EXT_MAIN3P3 POK undervoltage detection.

Table 5-219 CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_UV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8138h
Figure 5-106 CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_UV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-220 CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_UV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.106 CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_OV_CTRL Register ( Offset = 1813Ch) [reset = X]

CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_OV_CTRL is shown in Figure 5-107 and described in Table 5-222.

Return to Summary Table.

Controls operation of the VMON_EXT_MAIN3P3 POK overvoltage detection.

Table 5-221 CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_OV_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 813Ch
Figure 5-107 CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_OV_CTRL Register
3130292827262524
HYST_ENRESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OVER_VOLT_DETPOK_TRIM
R/W-XR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-222 CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_OV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31HYST_ENR/W1h

Enable POK hysteresis

30-8RESERVEDR0h

Reserved

7OVER_VOLT_DETR/WX

Over / under voltage detection mode
0h - Under voltage detection
1h - Over voltage detection

6-0POK_TRIMR/WX

POK trim bits. These bits are used to trim the comparator threshold voltage.

1.1.4.107 CTRLMMR_WKUP_DEEPSLEEP_CTRL Register ( Offset = 18160h) [reset = 0h]

CTRLMMR_WKUP_DEEPSLEEP_CTRL is shown in Figure 5-108 and described in Table 5-224.

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Used to control IO deepsleep operation.

Table 5-223 CTRLMMR_WKUP_DEEPSLEEP_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8160h
Figure 5-108 CTRLMMR_WKUP_DEEPSLEEP_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDFORCE_DS_MAIN
R-0hR/W-0h
76543210
RESERVEDFORCE_DS_WKUP
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-224 CTRLMMR_WKUP_DEEPSLEEP_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8FORCE_DS_MAINR/W0h

Force all MAIN IOs into deepsleep mode when set

7-1RESERVEDR0h

Reserved

0FORCE_DS_WKUPR/W0h

Force all WKUP IOs into deepsleep mode when set

1.1.4.108 CTRLMMR_WKUP_POR_RST_CTRL Register ( Offset = 18170h) [reset = F0000h]

CTRLMMR_WKUP_POR_RST_CTRL is shown in Figure 5-109 and described in Table 5-226.

Return to Summary Table.

Controls MAIN domain power-on reset behavior.

Table 5-225 CTRLMMR_WKUP_POR_RST_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8170h
Figure 5-109 CTRLMMR_WKUP_POR_RST_CTRL Register
3130292827262524
RESERVEDMAIN_PORZ_DAISYCHAIN_EN
R-0hR/W-0h
2322212019181716
RESERVEDSW_MAIN_POR
R-0hR/W-Fh
15141312111098
RESERVEDMAIN_PORZ_DS_STRETCHRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDPOR_RST_ISO_DONE_Z
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-226 CTRLMMR_WKUP_POR_RST_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h

Reserved

24MAIN_PORZ_DAISYCHAIN_ENR/W0h

Reserved. Always keep at default value.

23-20RESERVEDR0h

Reserved

19-16SW_MAIN_PORR/WFh

Main Domain software power-on reset. When set to 6h, a power-on is issued to the MAIN voltage domain. (Bits will reset to Fh on reset of the Main Domain)

15-13RESERVEDR0h

Reserved

12MAIN_PORZ_DS_STRETCHR/W0h

Reserved. Always keep at default value.

11-1RESERVEDR0h

Reserved

0POR_RST_ISO_DONE_ZR/W0h

Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete.
0h - POR reset propagates to MAIN domain
1h - POR reset blocked from MAIN domain

1.1.4.109 CTRLMMR_WKUP_MAIN_WARM_RST_CTRL Register ( Offset = 18174h) [reset = F0000h]

CTRLMMR_WKUP_MAIN_WARM_RST_CTRL is shown in Figure 5-110 and described in Table 5-228.

Return to Summary Table.

Controls warm reset propagation to the MAIN domain. This allows the DMSC to ensure that the MCU domain is properly isolated before the MAIN domain is reset.

Table 5-227 CTRLMMR_WKUP_MAIN_WARM_RST_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8174h
Figure 5-110 CTRLMMR_WKUP_MAIN_WARM_RST_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSW_WARMRST
R-0hR/W-Fh
15141312111098
RESERVED
R-0h
76543210
RESERVEDSOC_WARMRST_ISO_DONE_Z
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-228 CTRLMMR_WKUP_MAIN_WARM_RST_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h

Reserved

19-16SW_WARMRSTR/WFh

Main Domain software warm reset. When set to 6h, a warm reset is issued to the MAIN voltage domain. (Bits will reset to Fh on reset of the Main Domain)

15-1RESERVEDR0h

Reserved

0SOC_WARMRST_ISO_DONE_ZR/W0h

Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete.
0h - Warm reset propagates to MAIN domain
1h - Warm reset blocked from MAIN domain

1.1.4.110 CTRLMMR_WKUP_RST_STAT Register ( Offset = 18178h) [reset = X]

CTRLMMR_WKUP_RST_STAT is shown in Figure 5-111 and described in Table 5-230.

Return to Summary Table.

Shows the reset status.

Table 5-229 CTRLMMR_WKUP_RST_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8178h
Figure 5-111 CTRLMMR_WKUP_RST_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMCU_RST_DONE
R-0hR-X
15141312111098
RESERVED
R-0h
76543210
RESERVEDMAIN_RST_DONE
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-230 CTRLMMR_WKUP_RST_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MCU_RST_DONERX

Indicates MCU domain reset status.
0h - MCU domain is in reset
1h - MCU domain reset is complete

15-1RESERVEDR0h

Reserved

0MAIN_RST_DONERX

Indicates MAIN domain Warm reset status.
0h - MAIN domain is in Warm reset
1h - MAIN domain Warm reset is complete

1.1.4.111 CTRLMMR_WKUP_MCU_WARM_RST_CTRL Register ( Offset = 1817Ch) [reset = F0000h]

CTRLMMR_WKUP_MCU_WARM_RST_CTRL is shown in Figure 5-112 and described in Table 5-232.

Return to Summary Table.

Controls warm reset propagation to the MCU domain. This allows the DMSC to ensure that the WKUP domain is properly isolated before the MCU domain is reset.

Table 5-231 CTRLMMR_WKUP_MCU_WARM_RST_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 817Ch
Figure 5-112 CTRLMMR_WKUP_MCU_WARM_RST_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDSW_WARMRST
R-0hR/W-Fh
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-232 CTRLMMR_WKUP_MCU_WARM_RST_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h

Reserved

19-16SW_WARMRSTR/WFh

Chip software warm reset. When set to 6h, a warm reset is issued to the device (all voltage domains). (Bits will reset to Fh on reset completion.)

15-0RESERVEDR0h

Reserved

1.1.4.112 CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL Register ( Offset = 18180h) [reset = X]

CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL is shown in Figure 5-113 and described in Table 5-234.

Return to Summary Table.

Controls the voltage glitch detector circuit monitoring the VDD_CPU voltage domain.

Table 5-233 CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8180h
Figure 5-113 CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL Register
3130292827262524
PWDBRSTBRESERVED
R/W-0hR/W-0hR-0h
2322212019181716
RESERVEDLP_FILTER_SEL
R-0hR/W-X
15141312111098
RESERVEDTHRESH_HI_SEL
R-0hR/W-X
76543210
RESERVEDTHRESH_LO_SEL
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-234 CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31PWDBR/W0h

Power down - active low.
0h - Disable all functions
1h - Enable glitch detectors

30RSTBR/W0h

Reset - active low. To ensure proper operation, rstb must not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally, rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings to prevent abnormal trigger events.
0h - Reset glitch detector flags
1h - Glitch detection flags are enabled

29-19RESERVEDR0h

Reserved

18-16LP_FILTER_SELR/WX

Selects the glitch detect low-pass filter bandwidth

0h - 150 kHz

1h - 125 kHz

2h - 100 kHz

3h - 80 kHz

4h - 60 kHz

5h - 45 kHz

6h - 30 kHz

7h - 15 kHz

15-14RESERVEDR0h

Reserved

13-8THRESH_HI_SELR/WX

Selects the high voltage glitch threshold as a percentage of the monitored voltage

0h - 93.5% of VDD

1h - 94.0% of VDD

2h - 94.5% of VDD

3h - 95.0% of VDD

4h - 95.5% of VDD

5h - 96.0% of VDD

6h - 96.5% of VDD

7h - 97.0% of VDD

8h - 97.5% of VDD

9h - 98.0% of VDD

Ah - 98.5% of VDD

Bh - 99.0% of VDD

Ch - 99.5% of VDD

Dh - 100.0% of VDD

Eh - 100.5% of VDD

Fh - 101.0% of VDD

10h - 101.5% of VDD

11h - 102.0% of VDD

12h - 102.5% of VDD

13h - 103.0% of VDD

14h - 103.5% of VDD

15h - 104.0% of VDD

16h - 104.5% of VDD

17h - 105.0% of VDD

18h - 105.5% of VDD

19h - 106.0% of VDD

1Ah - 106.5% of VDD

1Bh - 107.0% of VDD

1Ch - 107.5% of VDD

1Dh - 108.0% of VDD

1Eh - 108.5% of VDD

1Fh - 109.0% of VDD

20h - 109.5% of VDD

21h - 110.0% of VDD

22h - 111.0% of VDD

23h - 112.0% of VDD

24h - 113.0% of VDD

25h - 114.0% of VDD

26h - 115.0% of VDD

27h - 116.0% of VDD

28h - 117.0% of VDD

29h - 118.0% of VDD

2Ah - 119.0% of VDD

2Bh - 120.0% of VDD

2Ch - 121.0% of VDD

2Dh - 122.0% of VDD

2Eh - 123.0% of VDD

2Fh - 124.0% of VDD

30h - 125.0% of VDD

31h - 126.0% of VDD

32h - 127.0% of VDD

33h - 128.0% of VDD

34h - 129.0% of VDD

35h - 130.0% of VDD

36h - 131.0% of VDD

37h - 132.0% of VDD

38h - 133.0% of VDD

39h - 134.0% of VDD

3Ah - 135.0% of VDD

3Bh - 136.0% of VDD

3Ch - 137.0% of VDD

3Dh - 138.0% of VDD

3Eh - 139.0% of VDD

3Fh - 140.0% of VDD

7-6RESERVEDR0h

Reserved

5-0THRESH_LO_SELR/WX

Selects the low voltage glitch threshold as a percentage of the monitored voltage

0h - 106.5% of VDD

1h - 106.0% of VDD

2h - 105.5% of VDD

3h - 105.0% of VDD

4h - 104.5% of VDD

5h - 104.0% of VDD

6h - 103.5% of VDD

7h - 103.0% of VDD

8h - 102.5% of VDD

9h - 102.0% of VDD

Ah - 101.5% of VDD

Bh - 101.0% of VDD

Ch - 100.5% of VDD

Dh - 100.0% of VDD

Eh - 99.5% of VDD

Fh - 99.0% of VDD

10h - 98.5% of VDD

11h - 98.0% of VDD

12h - 97.5% of VDD

13h - 97.0% of VDD

14h - 96.5% of VDD

15h - 96.0% of VDD

16h - 95.5% of VDD

17h - 95.0% of VDD

18h - 94.5% of VDD

19h - 94.0% of VDD

1Ah - 93.5% of VDD

1Bh - 93.0% of VDD

1Ch - 92.5% of VDD

1Dh - 92.0% of VDD

1Eh - 91.5% of VDD

1Fh - 91.0% of VDD

20h - 90.5% of VDD

21h - 90.0% of VDD

22h - 89.0% of VDD

23h - 88.0% of VDD

24h - 87.0% of VDD

25h - 86.0% of VDD

26h - 85.0% of VDD

27h - 84.0% of VDD

28h - 83.0% of VDD

29h - 82.0% of VDD

2Ah - 81.0% of VDD

2Bh - 80.0% of VDD

2Ch - 79.0% of VDD

2Dh - 78.0% of VDD

2Eh - 77.0% of VDD

2Fh - 76.0% of VDD

30h - 75.0% of VDD

31h - 74.0% of VDD

32h - 73.0% of VDD

33h - 72.0% of VDD

34h - 71.0% of VDD

35h - 70.0% of VDD

36h - 69.0% of VDD

37h - 68.0% of VDD

38h - 67.0% of VDD

39h - 66.0% of VDD

3Ah - 65.0% of VDD

3Bh - 64.0% of VDD

3Ch - 63.0% of VDD

3Dh - 62.0% of VDD

3Eh - 61.0% of VDD

3Fh - 60.0% of VDD

1.1.4.113 CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL Register ( Offset = 18190h) [reset = X]

CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL is shown in Figure 5-114 and described in Table 5-236.

Return to Summary Table.

Controls the voltage glitch detector circuit monitoring the VDD_CORE voltage domain.

Table 5-235 CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8190h
Figure 5-114 CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL Register
3130292827262524
PWDBRSTBRESERVED
R/W-0hR/W-0hR-0h
2322212019181716
RESERVEDLP_FILTER_SEL
R-0hR/W-X
15141312111098
RESERVEDTHRESH_HI_SEL
R-0hR/W-X
76543210
RESERVEDTHRESH_LO_SEL
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-236 CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31PWDBR/W0h

Power down - active low.
0h - Disable all functions
1h - Enable glitch detectors

30RSTBR/W0h

Reset - active low. To ensure proper operation, rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally, rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings to prevent abnormal trigger events.
0h - Reset glitch detector flags
1h - Glitch detection flags are enabled

29-19RESERVEDR0h

Reserved

18-16LP_FILTER_SELR/WX

Selects the glitch detect low-pass filter bandwidth

0h - 150 kHz

1h - 125 kHz

2h - 100 kHz

3h - 80 kHz

4h - 60 kHz

5h - 45 kHz

6h - 30 kHz

7h - 15 kHz

15-14RESERVEDR0h

Reserved

13-8THRESH_HI_SELR/WX

Selects the high voltage glitch threshold as a percentage of the monitored voltage

0h - 93.5% of VDD

1h - 94.0% of VDD

2h - 94.5% of VDD

3h - 95.0% of VDD

4h - 95.5% of VDD

5h - 96.0% of VDD

6h - 96.5% of VDD

7h - 97.0% of VDD

8h - 97.5% of VDD

9h - 98.0% of VDD

Ah - 98.5% of VDD

Bh - 99.0% of VDD

Ch - 99.5% of VDD

Dh - 100.0% of VDD

Eh - 100.5% of VDD

Fh - 101.0% of VDD

10h - 101.5% of VDD

11h - 102.0% of VDD

12h - 102.5% of VDD

13h - 103.0% of VDD

14h - 103.5% of VDD

15h - 104.0% of VDD

16h - 104.5% of VDD

17h - 105.0% of VDD

18h - 105.5% of VDD

19h - 106.0% of VDD

1Ah - 106.5% of VDD

1Bh - 107.0% of VDD

1Ch - 107.5% of VDD

1Dh - 108.0% of VDD

1Eh - 108.5% of VDD

1Fh - 109.0% of VDD

20h - 109.5% of VDD

21h - 110.0% of VDD

22h - 111.0% of VDD

23h - 112.0% of VDD

24h - 113.0% of VDD

25h - 114.0% of VDD

26h - 115.0% of VDD

27h - 116.0% of VDD

28h - 117.0% of VDD

29h - 118.0% of VDD

2Ah - 119.0% of VDD

2Bh - 120.0% of VDD

2Ch - 121.0% of VDD

2Dh - 122.0% of VDD

2Eh - 123.0% of VDD

2Fh - 124.0% of VDD

30h - 125.0% of VDD

31h - 126.0% of VDD

32h - 127.0% of VDD

33h - 128.0% of VDD

34h - 129.0% of VDD

35h - 130.0% of VDD

36h - 131.0% of VDD

37h - 132.0% of VDD

38h - 133.0% of VDD

39h - 134.0% of VDD

3Ah - 135.0% of VDD

3Bh - 136.0% of VDD

3Ch - 137.0% of VDD

3Dh - 138.0% of VDD

3Eh - 139.0% of VDD

3Fh - 140.0% of VDD

7-6RESERVEDR0h

Reserved

5-0THRESH_LO_SELR/WX

Selects the low voltage glitch threshold as a percentage of the monitored voltage

0h - 106.5% of VDD

1h - 106.0% of VDD

2h - 105.5% of VDD

3h - 105.0% of VDD

4h - 104.5% of VDD

5h - 104.0% of VDD

6h - 103.5% of VDD

7h - 103.0% of VDD

8h - 102.5% of VDD

9h - 102.0% of VDD

Ah - 101.5% of VDD

Bh - 101.0% of VDD

Ch - 100.5% of VDD

Dh - 100.0% of VDD

Eh - 99.5% of VDD

Fh - 99.0% of VDD

10h - 98.5% of VDD

11h - 98.0% of VDD

12h - 97.5% of VDD

13h - 97.0% of VDD

14h - 96.5% of VDD

15h - 96.0% of VDD

16h - 95.5% of VDD

17h - 95.0% of VDD

18h - 94.5% of VDD

19h - 94.0% of VDD

1Ah - 93.5% of VDD

1Bh - 93.0% of VDD

1Ch - 92.5% of VDD

1Dh - 92.0% of VDD

1Eh - 91.5% of VDD

1Fh - 91.0% of VDD

20h - 90.5% of VDD

21h - 90.0% of VDD

22h - 89.0% of VDD

23h - 88.0% of VDD

24h - 87.0% of VDD

25h - 86.0% of VDD

26h - 85.0% of VDD

27h - 84.0% of VDD

28h - 83.0% of VDD

29h - 82.0% of VDD

2Ah - 81.0% of VDD

2Bh - 80.0% of VDD

2Ch - 79.0% of VDD

2Dh - 78.0% of VDD

2Eh - 77.0% of VDD

2Fh - 76.0% of VDD

30h - 75.0% of VDD

31h - 74.0% of VDD

32h - 73.0% of VDD

33h - 72.0% of VDD

34h - 71.0% of VDD

35h - 70.0% of VDD

36h - 69.0% of VDD

37h - 68.0% of VDD

38h - 67.0% of VDD

39h - 66.0% of VDD

3Ah - 65.0% of VDD

3Bh - 64.0% of VDD

3Ch - 63.0% of VDD

3Dh - 62.0% of VDD

3Eh - 61.0% of VDD

3Fh - 60.0% of VDD

1.1.4.114 CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL Register ( Offset = 18194h) [reset = X]

CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL is shown in Figure 5-115 and described in Table 5-238.

Return to Summary Table.

Controls the voltage glitch detector circuit monitoring the VDDR_CPU voltage domain.

Table 5-237 CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8194h
Figure 5-115 CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL Register
3130292827262524
PWDBRSTBRESERVED
R/W-0hR/W-0hR-0h
2322212019181716
RESERVEDLP_FILTER_SEL
R-0hR/W-X
15141312111098
RESERVEDTHRESH_HI_SEL
R-0hR/W-X
76543210
RESERVEDTHRESH_LO_SEL
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-238 CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31PWDBR/W0h

Power down - active low.
0h - Disable all functions
1h - Enable glitch detectors

30RSTBR/W0h

Reset - active low. To ensure proper operation, rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally, rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings to prevent abnormal trigger events.
0h - Reset glitch detector flags
1h - Glitch detection flags are enabled

29-19RESERVEDR0h

Reserved

18-16LP_FILTER_SELR/WX

Selects the glitch detect low-pass filter bandwidth

0h - 150 kHz

1h - 125 kHz

2h - 100 kHz

3h - 80 kHz

4h - 60 kHz

5h - 45 kHz

6h - 30 kHz

7h - 15 kHz

15-14RESERVEDR0h

Reserved

13-8THRESH_HI_SELR/WX

Selects the high voltage glitch threshold as a percentage of the monitored voltage

0h - 93.5% of VDD

1h - 94.0% of VDD

2h - 94.5% of VDD

3h - 95.0% of VDD

4h - 95.5% of VDD

5h - 96.0% of VDD

6h - 96.5% of VDD

7h - 97.0% of VDD

8h - 97.5% of VDD

9h - 98.0% of VDD

Ah - 98.5% of VDD

Bh - 99.0% of VDD

Ch - 99.5% of VDD

Dh - 100.0% of VDD

Eh - 100.5% of VDD

Fh - 101.0% of VDD

10h - 101.5% of VDD

11h - 102.0% of VDD

12h - 102.5% of VDD

13h - 103.0% of VDD

14h - 103.5% of VDD

15h - 104.0% of VDD

16h - 104.5% of VDD

17h - 105.0% of VDD

18h - 105.5% of VDD

19h - 106.0% of VDD

1Ah - 106.5% of VDD

1Bh - 107.0% of VDD

1Ch - 107.5% of VDD

1Dh - 108.0% of VDD

1Eh - 108.5% of VDD

1Fh - 109.0% of VDD

20h - 109.5% of VDD

21h - 110.0% of VDD

22h - 111.0% of VDD

23h - 112.0% of VDD

24h - 113.0% of VDD

25h - 114.0% of VDD

26h - 115.0% of VDD

27h - 116.0% of VDD

28h - 117.0% of VDD

29h - 118.0% of VDD

2Ah - 119.0% of VDD

2Bh - 120.0% of VDD

2Ch - 121.0% of VDD

2Dh - 122.0% of VDD

2Eh - 123.0% of VDD

2Fh - 124.0% of VDD

30h - 125.0% of VDD

31h - 126.0% of VDD

32h - 127.0% of VDD

33h - 128.0% of VDD

34h - 129.0% of VDD

35h - 130.0% of VDD

36h - 131.0% of VDD

37h - 132.0% of VDD

38h - 133.0% of VDD

39h - 134.0% of VDD

3Ah - 135.0% of VDD

3Bh - 136.0% of VDD

3Ch - 137.0% of VDD

3Dh - 138.0% of VDD

3Eh - 139.0% of VDD

3Fh - 140.0% of VDD

7-6RESERVEDR0h

Reserved

5-0THRESH_LO_SELR/WX

Selects the low voltage glitch threshold as a percentage of the monitored voltage

0h - 106.5% of VDD

1h - 106.0% of VDD

2h - 105.5% of VDD

3h - 105.0% of VDD

4h - 104.5% of VDD

5h - 104.0% of VDD

6h - 103.5% of VDD

7h - 103.0% of VDD

8h - 102.5% of VDD

9h - 102.0% of VDD

Ah - 101.5% of VDD

Bh - 101.0% of VDD

Ch - 100.5% of VDD

Dh - 100.0% of VDD

Eh - 99.5% of VDD

Fh - 99.0% of VDD

10h - 98.5% of VDD

11h - 98.0% of VDD

12h - 97.5% of VDD

13h - 97.0% of VDD

14h - 96.5% of VDD

15h - 96.0% of VDD

16h - 95.5% of VDD

17h - 95.0% of VDD

18h - 94.5% of VDD

19h - 94.0% of VDD

1Ah - 93.5% of VDD

1Bh - 93.0% of VDD

1Ch - 92.5% of VDD

1Dh - 92.0% of VDD

1Eh - 91.5% of VDD

1Fh - 91.0% of VDD

20h - 90.5% of VDD

21h - 90.0% of VDD

22h - 89.0% of VDD

23h - 88.0% of VDD

24h - 87.0% of VDD

25h - 86.0% of VDD

26h - 85.0% of VDD

27h - 84.0% of VDD

28h - 83.0% of VDD

29h - 82.0% of VDD

2Ah - 81.0% of VDD

2Bh - 80.0% of VDD

2Ch - 79.0% of VDD

2Dh - 78.0% of VDD

2Eh - 77.0% of VDD

2Fh - 76.0% of VDD

30h - 75.0% of VDD

31h - 74.0% of VDD

32h - 73.0% of VDD

33h - 72.0% of VDD

34h - 71.0% of VDD

35h - 70.0% of VDD

36h - 69.0% of VDD

37h - 68.0% of VDD

38h - 67.0% of VDD

39h - 66.0% of VDD

3Ah - 65.0% of VDD

3Bh - 64.0% of VDD

3Ch - 63.0% of VDD

3Dh - 62.0% of VDD

3Eh - 61.0% of VDD

3Fh - 60.0% of VDD

1.1.4.115 CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL Register ( Offset = 18198h) [reset = X]

CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL is shown in Figure 5-116 and described in Table 5-240.

Return to Summary Table.

Controls the voltage glitch detector circuit monitoring the VDDR_CORE voltage domain.

Table 5-239 CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8198h
Figure 5-116 CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL Register
3130292827262524
PWDBRSTBRESERVED
R/W-0hR/W-0hR-0h
2322212019181716
RESERVEDLP_FILTER_SEL
R-0hR/W-X
15141312111098
RESERVEDTHRESH_HI_SEL
R-0hR/W-X
76543210
RESERVEDTHRESH_LO_SEL
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-240 CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31PWDBR/W0h

Power down - active low.
0h - Disable all functions
1h - Enable glitch detectors

30RSTBR/W0h

Reset - active low. To ensure proper operation, rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally, rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings to prevent abnormal trigger events.
0h - Reset glitch detector flags
1h - Glitch detection flags are enabled

29-19RESERVEDR0h

Reserved

18-16LP_FILTER_SELR/WX

Selects the glitch detect low-pass filter bandwidth

0h - 150 kHz

1h - 125 kHz

2h - 100 kHz

3h - 80 kHz

4h - 60 kHz

5h - 45 kHz

6h - 30 kHz

7h - 15 kHz

15-14RESERVEDR0h

Reserved

13-8THRESH_HI_SELR/WX

Selects the high voltage glitch threshold as a percentage of the monitored voltage

0h - 93.5% of VDD

1h - 94.0% of VDD

2h - 94.5% of VDD

3h - 95.0% of VDD

4h - 95.5% of VDD

5h - 96.0% of VDD

6h - 96.5% of VDD

7h - 97.0% of VDD

8h - 97.5% of VDD

9h - 98.0% of VDD

Ah - 98.5% of VDD

Bh - 99.0% of VDD

Ch - 99.5% of VDD

Dh - 100.0% of VDD

Eh - 100.5% of VDD

Fh - 101.0% of VDD

10h - 101.5% of VDD

11h - 102.0% of VDD

12h - 102.5% of VDD

13h - 103.0% of VDD

14h - 103.5% of VDD

15h - 104.0% of VDD

16h - 104.5% of VDD

17h - 105.0% of VDD

18h - 105.5% of VDD

19h - 106.0% of VDD

1Ah - 106.5% of VDD

1Bh - 107.0% of VDD

1Ch - 107.5% of VDD

1Dh - 108.0% of VDD

1Eh - 108.5% of VDD

1Fh - 109.0% of VDD

20h - 109.5% of VDD

21h - 110.0% of VDD

22h - 111.0% of VDD

23h - 112.0% of VDD

24h - 113.0% of VDD

25h - 114.0% of VDD

26h - 115.0% of VDD

27h - 116.0% of VDD

28h - 117.0% of VDD

29h - 118.0% of VDD

2Ah - 119.0% of VDD

2Bh - 120.0% of VDD

2Ch - 121.0% of VDD

2Dh - 122.0% of VDD

2Eh - 123.0% of VDD

2Fh - 124.0% of VDD

30h - 125.0% of VDD

31h - 126.0% of VDD

32h - 127.0% of VDD

33h - 128.0% of VDD

34h - 129.0% of VDD

35h - 130.0% of VDD

36h - 131.0% of VDD

37h - 132.0% of VDD

38h - 133.0% of VDD

39h - 134.0% of VDD

3Ah - 135.0% of VDD

3Bh - 136.0% of VDD

3Ch - 137.0% of VDD

3Dh - 138.0% of VDD

3Eh - 139.0% of VDD

3Fh - 140.0% of VDD

7-6RESERVEDR0h

Reserved

5-0THRESH_LO_SELR/WX

Selects the low voltage glitch threshold as a percentage of the monitored voltage

0h - 106.5% of VDD

1h - 106.0% of VDD

2h - 105.5% of VDD

3h - 105.0% of VDD

4h - 104.5% of VDD

5h - 104.0% of VDD

6h - 103.5% of VDD

7h - 103.0% of VDD

8h - 102.5% of VDD

9h - 102.0% of VDD

Ah - 101.5% of VDD

Bh - 101.0% of VDD

Ch - 100.5% of VDD

Dh - 100.0% of VDD

Eh - 99.5% of VDD

Fh - 99.0% of VDD

10h - 98.5% of VDD

11h - 98.0% of VDD

12h - 97.5% of VDD

13h - 97.0% of VDD

14h - 96.5% of VDD

15h - 96.0% of VDD

16h - 95.5% of VDD

17h - 95.0% of VDD

18h - 94.5% of VDD

19h - 94.0% of VDD

1Ah - 93.5% of VDD

1Bh - 93.0% of VDD

1Ch - 92.5% of VDD

1Dh - 92.0% of VDD

1Eh - 91.5% of VDD

1Fh - 91.0% of VDD

20h - 90.5% of VDD

21h - 90.0% of VDD

22h - 89.0% of VDD

23h - 88.0% of VDD

24h - 87.0% of VDD

25h - 86.0% of VDD

26h - 85.0% of VDD

27h - 84.0% of VDD

28h - 83.0% of VDD

29h - 82.0% of VDD

2Ah - 81.0% of VDD

2Bh - 80.0% of VDD

2Ch - 79.0% of VDD

2Dh - 78.0% of VDD

2Eh - 77.0% of VDD

2Fh - 76.0% of VDD

30h - 75.0% of VDD

31h - 74.0% of VDD

32h - 73.0% of VDD

33h - 72.0% of VDD

34h - 71.0% of VDD

35h - 70.0% of VDD

36h - 69.0% of VDD

37h - 68.0% of VDD

38h - 67.0% of VDD

39h - 66.0% of VDD

3Ah - 65.0% of VDD

3Bh - 64.0% of VDD

3Ch - 63.0% of VDD

3Dh - 62.0% of VDD

3Eh - 61.0% of VDD

3Fh - 60.0% of VDD

1.1.4.116 CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT Register ( Offset = 181A0h) [reset = X]

CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT is shown in Figure 5-117 and described in Table 5-242.

Return to Summary Table.

Shows the status of the voltage glitch detector circuit monitoring the VDD_CPU voltage domain.

Table 5-241 CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 81A0h
Figure 5-117 CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTHRESH_HI_FLAG
R-0hR-X
76543210
RESERVEDTHRESH_LOW_FLAG
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-242 CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8THRESH_HI_FLAGRX

High voltage flag. This flag is cleared by clearing the VDD_CPU_GLDTC_CTRL_rstb bit.
0h - No high voltage detected
1h - Voltage above the high voltage threshold was detected.

7-1RESERVEDR0h

Reserved

0THRESH_LOW_FLAGRX

Low voltage flag. This flag is cleared by clearing the VDD_CPU_GLDTC_CTRL_rstb bit.
0h - No low voltage detected
1h - Voltage below the low voltage threshold was detected.

1.1.4.117 CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT Register ( Offset = 181B0h) [reset = X]

CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT is shown in Figure 5-118 and described in Table 5-244.

Return to Summary Table.

Shows the status of the voltage glitch detector circuit monitoring the VDD_CORE voltage domain.

Table 5-243 CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 81B0h
Figure 5-118 CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTHRESH_HI_FLAG
R-0hR-X
76543210
RESERVEDTHRESH_LOW_FLAG
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-244 CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8THRESH_HI_FLAGRX

High voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit.
0h - No high voltage detected
1h - Voltage above the high voltage threshold was detected.

7-1RESERVEDR0h

Reserved

0THRESH_LOW_FLAGRX

Low voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit.
0h - No low voltage detected
1h - Voltage below the low voltage threshold was detected.

1.1.4.118 CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT Register ( Offset = 181B4h) [reset = X]

CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT is shown in Figure 5-119 and described in Table 5-246.

Return to Summary Table.

Shows the status of the voltage glitch detector circuit monitoring the VDDR_CPU voltage domain.

Table 5-245 CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 81B4h
Figure 5-119 CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTHRESH_HI_FLAG
R-0hR-X
76543210
RESERVEDTHRESH_LOW_FLAG
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-246 CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8THRESH_HI_FLAGRX

High voltage flag. This flag is cleared by clearing the VDDR_CPU_GLDTC_CTRL_rstb bit.
0h - No high voltage detected
1h - Voltage above the high voltage threshold was detected.

7-1RESERVEDR0h

Reserved

0THRESH_LOW_FLAGRX

Low voltage flag. This flag is cleared by clearing the VDDR_CPU_GLDTC_CTRL_rstb bit.
0h - No low voltage detected
1h - Voltage below the low voltage threshold was detected.

1.1.4.119 CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT Register ( Offset = 181B8h) [reset = X]

CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT is shown in Figure 5-120 and described in Table 5-248.

Return to Summary Table.

Shows the status of the voltage glitch detector circuit monitoring the VDDR_CORE voltage domain.

Table 5-247 CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 81B8h
Figure 5-120 CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTHRESH_HI_FLAG
R-0hR-X
76543210
RESERVEDTHRESH_LOW_FLAG
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-248 CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8THRESH_HI_FLAGRX

High voltage flag. This flag is cleared by clearing the VDDR_CORE_GLDTC_CTRL_rstb bit.
0h - No high voltage detected
1h - Voltage above the high voltage threshold was detected.

7-1RESERVEDR0h

Reserved

0THRESH_LOW_FLAGRX

Low voltage flag. This flag is cleared by clearing the VDDR_CORE_GLDTC_CTRL_rstb bit.
0h - No low voltage detected
1h - Voltage below the low voltage threshold was detected.

1.1.4.120 CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL Register ( Offset = 181C0h) [reset = X]

CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL is shown in Figure 5-121 and described in Table 5-250.

Return to Summary Table.

Controls the voltage glitch detector circuit monitoring the VDD_MCU voltage domain.

Table 5-249 CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 81C0h
Figure 5-121 CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL Register
3130292827262524
PWDBRSTBRESERVED
R/W-0hR/W-0hR-0h
2322212019181716
RESERVEDLP_FILTER_SEL
R-0hR/W-X
15141312111098
RESERVEDTHRESH_HI_SEL
R-0hR/W-X
76543210
RESERVEDTHRESH_LO_SEL
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-250 CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31PWDBR/W0h

Power down - active low.
0h - Disable all functions
1h - Enable glitch detectors

30RSTBR/W0h

Reset - active low. To ensure proper operation, rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally, rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings to prevent abnormal trigger events.
0h - Reset glitch detector flags
1h - Glitch detection flags are enabled

29-19RESERVEDR0h

Reserved

18-16LP_FILTER_SELR/WX

Selects the glitch detect low-pass filter bandwidth

0h - 150 kHz

1h - 125 kHz

2h - 100 kHz

3h - 80 kHz

4h - 60 kHz

5h - 45 kHz

6h - 30 kHz

7h - 15 kHz

15-14RESERVEDR0h

Reserved

13-8THRESH_HI_SELR/WX

Selects the high voltage glitch threshold as a percentage of the monitored voltage

0h - 93.5% of VDD

1h - 94.0% of VDD

2h - 94.5% of VDD

3h - 95.0% of VDD

4h - 95.5% of VDD

5h - 96.0% of VDD

6h - 96.5% of VDD

7h - 97.0% of VDD

8h - 97.5% of VDD

9h - 98.0% of VDD

Ah - 98.5% of VDD

Bh - 99.0% of VDD

Ch - 99.5% of VDD

Dh - 100.0% of VDD

Eh - 100.5% of VDD

Fh - 101.0% of VDD

10h - 101.5% of VDD

11h - 102.0% of VDD

12h - 102.5% of VDD

13h - 103.0% of VDD

14h - 103.5% of VDD

15h - 104.0% of VDD

16h - 104.5% of VDD

17h - 105.0% of VDD

18h - 105.5% of VDD

19h - 106.0% of VDD

1Ah - 106.5% of VDD

1Bh - 107.0% of VDD

1Ch - 107.5% of VDD

1Dh - 108.0% of VDD

1Eh - 108.5% of VDD

1Fh - 109.0% of VDD

20h - 109.5% of VDD

21h - 110.0% of VDD

22h - 111.0% of VDD

23h - 112.0% of VDD

24h - 113.0% of VDD

25h - 114.0% of VDD

26h - 115.0% of VDD

27h - 116.0% of VDD

28h - 117.0% of VDD

29h - 118.0% of VDD

2Ah - 119.0% of VDD

2Bh - 120.0% of VDD

2Ch - 121.0% of VDD

2Dh - 122.0% of VDD

2Eh - 123.0% of VDD

2Fh - 124.0% of VDD

30h - 125.0% of VDD

31h - 126.0% of VDD

32h - 127.0% of VDD

33h - 128.0% of VDD

34h - 129.0% of VDD

35h - 130.0% of VDD

36h - 131.0% of VDD

37h - 132.0% of VDD

38h - 133.0% of VDD

39h - 134.0% of VDD

3Ah - 135.0% of VDD

3Bh - 136.0% of VDD

3Ch - 137.0% of VDD

3Dh - 138.0% of VDD

3Eh - 139.0% of VDD

3Fh - 140.0% of VDD

7-6RESERVEDR0h

Reserved

5-0THRESH_LO_SELR/WX

Selects the low voltage glitch threshold as a percentage of the monitored voltage

0h - 106.5% of VDD

1h - 106.0% of VDD

2h - 105.5% of VDD

3h - 105.0% of VDD

4h - 104.5% of VDD

5h - 104.0% of VDD

6h - 103.5% of VDD

7h - 103.0% of VDD

8h - 102.5% of VDD

9h - 102.0% of VDD

Ah - 101.5% of VDD

Bh - 101.0% of VDD

Ch - 100.5% of VDD

Dh - 100.0% of VDD

Eh - 99.5% of VDD

Fh - 99.0% of VDD

10h - 98.5% of VDD

11h - 98.0% of VDD

12h - 97.5% of VDD

13h - 97.0% of VDD

14h - 96.5% of VDD

15h - 96.0% of VDD

16h - 95.5% of VDD

17h - 95.0% of VDD

18h - 94.5% of VDD

19h - 94.0% of VDD

1Ah - 93.5% of VDD

1Bh - 93.0% of VDD

1Ch - 92.5% of VDD

1Dh - 92.0% of VDD

1Eh - 91.5% of VDD

1Fh - 91.0% of VDD

20h - 90.5% of VDD

21h - 90.0% of VDD

22h - 89.0% of VDD

23h - 88.0% of VDD

24h - 87.0% of VDD

25h - 86.0% of VDD

26h - 85.0% of VDD

27h - 84.0% of VDD

28h - 83.0% of VDD

29h - 82.0% of VDD

2Ah - 81.0% of VDD

2Bh - 80.0% of VDD

2Ch - 79.0% of VDD

2Dh - 78.0% of VDD

2Eh - 77.0% of VDD

2Fh - 76.0% of VDD

30h - 75.0% of VDD

31h - 74.0% of VDD

32h - 73.0% of VDD

33h - 72.0% of VDD

34h - 71.0% of VDD

35h - 70.0% of VDD

36h - 69.0% of VDD

37h - 68.0% of VDD

38h - 67.0% of VDD

39h - 66.0% of VDD

3Ah - 65.0% of VDD

3Bh - 64.0% of VDD

3Ch - 63.0% of VDD

3Dh - 62.0% of VDD

3Eh - 61.0% of VDD

3Fh - 60.0% of VDD

1.1.4.121 CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL Register ( Offset = 181C4h) [reset = X]

CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL is shown in Figure 5-122 and described in Table 5-252.

Return to Summary Table.

Controls the voltage glitch detector circuit monitoring the VDDR_MCU voltage domain.

Table 5-251 CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 81C4h
Figure 5-122 CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL Register
3130292827262524
PWDBRSTBRESERVED
R/W-0hR/W-0hR-0h
2322212019181716
RESERVEDLP_FILTER_SEL
R-0hR/W-X
15141312111098
RESERVEDTHRESH_HI_SEL
R-0hR/W-X
76543210
RESERVEDTHRESH_LO_SEL
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-252 CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31PWDBR/W0h

Power down - active low.
0h - Disable all functions
1h - Enable glitch detectors

30RSTBR/W0h

Reset - active low. To ensure proper operation, rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally, rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings to prevent abnormal trigger events.
0h - Reset glitch detector flags
1h - Glitch detection flags are enabled

29-19RESERVEDR0h

Reserved

18-16LP_FILTER_SELR/WX

Selects the glitch detect low-pass filter bandwidth

0h - 150 kHz

1h - 125 kHz

2h - 100 kHz

3h - 80 kHz

4h - 60 kHz

5h - 45 kHz

6h - 30 kHz

7h - 15 kHz

15-14RESERVEDR0h

Reserved

13-8THRESH_HI_SELR/WX

Selects the high voltage glitch threshold as a percentage of the monitored voltage

0h - 93.5% of VDD

1h - 94.0% of VDD

2h - 94.5% of VDD

3h - 95.0% of VDD

4h - 95.5% of VDD

5h - 96.0% of VDD

6h - 96.5% of VDD

7h - 97.0% of VDD

8h - 97.5% of VDD

9h - 98.0% of VDD

Ah - 98.5% of VDD

Bh - 99.0% of VDD

Ch - 99.5% of VDD

Dh - 100.0% of VDD

Eh - 100.5% of VDD

Fh - 101.0% of VDD

10h - 101.5% of VDD

11h - 102.0% of VDD

12h - 102.5% of VDD

13h - 103.0% of VDD

14h - 103.5% of VDD

15h - 104.0% of VDD

16h - 104.5% of VDD

17h - 105.0% of VDD

18h - 105.5% of VDD

19h - 106.0% of VDD

1Ah - 106.5% of VDD

1Bh - 107.0% of VDD

1Ch - 107.5% of VDD

1Dh - 108.0% of VDD

1Eh - 108.5% of VDD

1Fh - 109.0% of VDD

20h - 109.5% of VDD

21h - 110.0% of VDD

22h - 111.0% of VDD

23h - 112.0% of VDD

24h - 113.0% of VDD

25h - 114.0% of VDD

26h - 115.0% of VDD

27h - 116.0% of VDD

28h - 117.0% of VDD

29h - 118.0% of VDD

2Ah - 119.0% of VDD

2Bh - 120.0% of VDD

2Ch - 121.0% of VDD

2Dh - 122.0% of VDD

2Eh - 123.0% of VDD

2Fh - 124.0% of VDD

30h - 125.0% of VDD

31h - 126.0% of VDD

32h - 127.0% of VDD

33h - 128.0% of VDD

34h - 129.0% of VDD

35h - 130.0% of VDD

36h - 131.0% of VDD

37h - 132.0% of VDD

38h - 133.0% of VDD

39h - 134.0% of VDD

3Ah - 135.0% of VDD

3Bh - 136.0% of VDD

3Ch - 137.0% of VDD

3Dh - 138.0% of VDD

3Eh - 139.0% of VDD

3Fh - 140.0% of VDD

7-6RESERVEDR0h

Reserved

5-0THRESH_LO_SELR/WX

Selects the low voltage glitch threshold as a percentage of the monitored voltage

0h - 106.5% of VDD

1h - 106.0% of VDD

2h - 105.5% of VDD

3h - 105.0% of VDD

4h - 104.5% of VDD

5h - 104.0% of VDD

6h - 103.5% of VDD

7h - 103.0% of VDD

8h - 102.5% of VDD

9h - 102.0% of VDD

Ah - 101.5% of VDD

Bh - 101.0% of VDD

Ch - 100.5% of VDD

Dh - 100.0% of VDD

Eh - 99.5% of VDD

Fh - 99.0% of VDD

10h - 98.5% of VDD

11h - 98.0% of VDD

12h - 97.5% of VDD

13h - 97.0% of VDD

14h - 96.5% of VDD

15h - 96.0% of VDD

16h - 95.5% of VDD

17h - 95.0% of VDD

18h - 94.5% of VDD

19h - 94.0% of VDD

1Ah - 93.5% of VDD

1Bh - 93.0% of VDD

1Ch - 92.5% of VDD

1Dh - 92.0% of VDD

1Eh - 91.5% of VDD

1Fh - 91.0% of VDD

20h - 90.5% of VDD

21h - 90.0% of VDD

22h - 89.0% of VDD

23h - 88.0% of VDD

24h - 87.0% of VDD

25h - 86.0% of VDD

26h - 85.0% of VDD

27h - 84.0% of VDD

28h - 83.0% of VDD

29h - 82.0% of VDD

2Ah - 81.0% of VDD

2Bh - 80.0% of VDD

2Ch - 79.0% of VDD

2Dh - 78.0% of VDD

2Eh - 77.0% of VDD

2Fh - 76.0% of VDD

30h - 75.0% of VDD

31h - 74.0% of VDD

32h - 73.0% of VDD

33h - 72.0% of VDD

34h - 71.0% of VDD

35h - 70.0% of VDD

36h - 69.0% of VDD

37h - 68.0% of VDD

38h - 67.0% of VDD

39h - 66.0% of VDD

3Ah - 65.0% of VDD

3Bh - 64.0% of VDD

3Ch - 63.0% of VDD

3Dh - 62.0% of VDD

3Eh - 61.0% of VDD

3Fh - 60.0% of VDD

1.1.4.122 CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT Register ( Offset = 181D0h) [reset = X]

CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT is shown in Figure 5-123 and described in Table 5-254.

Return to Summary Table.

Shows the status of the voltage glitch detector circuit monitoring the VDD_MCU voltage domain.

Table 5-253 CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 81D0h
Figure 5-123 CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTHRESH_HI_FLAG
R-0hR-X
76543210
RESERVEDTHRESH_LOW_FLAG
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-254 CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8THRESH_HI_FLAGRX

High voltage flag. This flag is cleared by clearing the VDD_MCU_GLDTC_CTRL_rstb bit.
0h - No high voltage detected
1h - Voltage above the high voltage threshold was detected.

7-1RESERVEDR0h

Reserved

0THRESH_LOW_FLAGRX

Low voltage flag. This flag is cleared by clearing the VDD_MCU_GLDTC_CTRL_rstb bit.
0h - No low voltage detected
1h - Voltage below the low voltage threshold was detected.

1.1.4.123 CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT Register ( Offset = 181D4h) [reset = X]

CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT is shown in Figure 5-124 and described in Table 5-256.

Return to Summary Table.

Shows the status of the voltage glitch detector circuit monitoring the VDDR_MCU voltage domain.

Table 5-255 CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 81D4h
Figure 5-124 CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTHRESH_HI_FLAG
R-0hR-X
76543210
RESERVEDTHRESH_LOW_FLAG
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-256 CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8THRESH_HI_FLAGRX

High voltage flag. This flag is cleared by clearing the VDDR_MCU_GLDTC_CTRL_rstb bit.
0h - No high voltage detected
1h - Voltage above the high voltage threshold was detected.

7-1RESERVEDR0h

Reserved

0THRESH_LOW_FLAGRX

Low voltage flag. This flag is cleared by clearing the VDDR_MCU_GLDTC_CTRL_rstb bit.
0h - No low voltage detected
1h - Voltage below the low voltage threshold was detected.

1.1.4.124 CTRLMMR_WKUP_PRG_PP_MCU_CTRL Register ( Offset = 18200h) [reset = 20007h]

CTRLMMR_WKUP_PRG_PP_MCU_CTRL is shown in Figure 5-125 and described in Table 5-258.

Return to Summary Table.

Configures the MCU PRG_PP controller.

Table 5-257 CTRLMMR_WKUP_PRG_PP_MCU_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8200h
Figure 5-125 CTRLMMR_WKUP_PRG_PP_MCU_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDPOK_PP_ENRESERVEDRESERVED
R-0hR/W-0hR-0hR/W-2h
15141312111098
POK_EN_SELRESERVEDPOK_VMON_CAP_MCU_GEN_OV_SELPOK_VDDR_MCU_OV_SELPOK_VDDSHV_WKUP_GEN_OV_SEL
R/W-0hR-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDPOK_VMON_CAP_MCU_GEN_ENPOK_VDDR_MCU_ENPOK_VDDSHV_WKUP_GEN_EN
R-0hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-258 CTRLMMR_WKUP_PRG_PP_MCU_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h

Reserved

19POK_PP_ENR/W0h

POK ping-pong enable. When set, enables automatic switching between undervoltage and overvoltage detection on VDDSHV_WKUP_GENERAL, VDDR_MCU and VMON_CAP_MCU_GENERAL POKs. This bit has no effect if the POK's ov_sel bit = 1.
0h - No pingpong operation. UV/OV operation selected by each POK ov_sel bit
1h - Pingpong operation enabled .

18RESERVEDR0h

Reserved

17-16RESERVEDR/W2h

Reserved

15POK_EN_SELR/W0h

Select POK enable source
0h - POK enables come from hardware tie-offs
1h - POK enables come from CTRLMMR_WKUP_PRG_PP_MCU_CTRL register

14-11RESERVEDR0h

Reserved

10POK_VMON_CAP_MCU_GEN_OV_SELR/W0h

Force VMON_CAP_MCU_GENERAL POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

9POK_VDDR_MCU_OV_SELR/W0h

Force VDDR_MCU POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

8POK_VDDSHV_WKUP_GEN_OV_SELR/W0h

Force VDDSHV_WKUP_GENERAL POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

7-3RESERVEDR0h

Reserved

2POK_VMON_CAP_MCU_GEN_ENR/W1h

Enable VMON_CAP_MCU_GENERAL POK detection
0h - POK detection disabled
1h - POK detection enabled

1POK_VDDR_MCU_ENR/W1h

Enable VDDR_MCU POK detection
0h - POK detection disabled
1h - POK detection enabled

0POK_VDDSHV_WKUP_GEN_ENR/W1h

Enable VDDSHV_WKUP_GENERAL POK detection
0h - POK detection disabled
1h - POK detection enabled

1.1.4.125 CTRLMMR_WKUP_PRG_PP_MCU_STAT Register ( Offset = 18204h) [reset = X]

CTRLMMR_WKUP_PRG_PP_MCU_STAT is shown in Figure 5-126 and described in Table 5-260.

Return to Summary Table.

Provides MCU PRG_PP controller status and status clear control.

Table 5-259 CTRLMMR_WKUP_PRG_PP_MCU_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8204h
Figure 5-126 CTRLMMR_WKUP_PRG_PP_MCU_STAT Register
3130292827262524
POK_CLRRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDPOK_VMON_CAP_MCU_GEN_OVPOK_VDDR_MCU_OVPOK_VDDSHV_WKUP_GEN_OV
R-0hR-XR-XR-X
76543210
RESERVEDPOK_VMON_CAP_MCU_GEN_UVPOK_VDDR_MCU_UVPOK_VDDSHV_WKUP_GEN_UV
R-0hR-XR-XR-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-260 CTRLMMR_WKUP_PRG_PP_MCU_STAT Register Field Descriptions
BitFieldTypeResetDescription
31POK_CLRR/W0h

When set, resets pgood sticky bits for VDDSHV_WKUP_GENERAL, VDDR_MCU, and VMON_CAP_MCU_GENERAL voltage POK detection.

30-11RESERVEDR0h

Reserved

10POK_VMON_CAP_MCU_GEN_OVRX

VMON_CAP_MCU_GENERAL overvoltage POK
0h - Voltage good
1h - Voltage above threshold

9POK_VDDR_MCU_OVRX

VDDR_MCU overvoltage POK
0h - Voltage good
1h - Voltage above threshold

8POK_VDDSHV_WKUP_GEN_OVRX

VDDSHV_WKUP_GENERAL overvoltage POK
0h - Voltage good
1h - Voltage above threshold

7-3RESERVEDR0h

Reserved

2POK_VMON_CAP_MCU_GEN_UVRX

VMON_CAP_MCU_GENERAL undervoltage POK
0h - Voltage good
1h - Voltage below threshold

1POK_VDDR_MCU_UVRX

VDDR_MCU undervoltage POK
0h - Voltage good
1h - Voltage below threshold

0POK_VDDSHV_WKUP_GEN_UVRX

VDDSHV_WKUP_GENERAL undervoltage POK
0h - Voltage good
1h - Voltage below threshold

1.1.4.126 CTRLMMR_WKUP_PRG_PP_POR_CTRL Register ( Offset = 18208h) [reset = 2001Fh]

CTRLMMR_WKUP_PRG_PP_POR_CTRL is shown in Figure 5-127 and described in Table 5-262.

Return to Summary Table.

Configures the POR PRG_PP controller.

Table 5-261 CTRLMMR_WKUP_PRG_PP_POR_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8208h
Figure 5-127 CTRLMMR_WKUP_PRG_PP_POR_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDEGLITCH_SEL
R-0hR/W-2h
15141312111098
POK_EN_SELRESERVED
R/W-0hR-0h
76543210
RESERVEDPOK_VDDA_PMIC_IN_UV_ENPOK_VDD_MCU_OV_ENPOK_VDD_MCU_UV_ENPOK_VDDA_MCU_OV_ENPOK_VDDA_MCU_UV_EN
R-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-262 CTRLMMR_WKUP_PRG_PP_POR_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h

Reserved

17-16DEGLITCH_SELR/W2h

Deglitch period for PRG_PP_POR POKs
Not used on this device - PRG_PP_POR deglitch_sel is tied off to 2h

0h - 5 us

1h - 10 us

2h - 15 us

3h - 20 us

15POK_EN_SELR/W0h

Select POK enable source
0h - POK enables come from hardware tie-offs
1h - POK enables come from CTRLMMR_WKUP_PRG_PP_POR_CTRL register

14-5RESERVEDR0h

Reserved

4POK_VDDA_PMIC_IN_UV_ENR/W1h

Enable VDDA_PMIC_IN undervoltage POK detection
0h - POK detection disabled
1h - POK detection enabled

3POK_VDD_MCU_OV_ENR/W1h

Enable VDD_MCU overvoltage POK detection
0h - POK detection disabled
1h - POK detection enabled

2POK_VDD_MCU_UV_ENR/W1h

Enable VDD_MCU undervoltage POK detection
0h - POK detection disabled
1h - POK detection enabled

1POK_VDDA_MCU_OV_ENR/W1h

Enable 1.8V VDDA_MCU overvoltage POK detection
0h - POK detection disabled
1h - POK detection enabled

0POK_VDDA_MCU_UV_ENR/W1h

Enable 1.8V VDDA_MCU undervoltage POK detection
0h - POK detection disabled
1h - POK detection enabled

1.1.4.127 CTRLMMR_WKUP_PRG_PP_POR_STAT Register ( Offset = 1820Ch) [reset = X]

CTRLMMR_WKUP_PRG_PP_POR_STAT is shown in Figure 5-128 and described in Table 5-264.

Return to Summary Table.

Provides POR PRG_PP controller status and status clear control.

Table 5-263 CTRLMMR_WKUP_PRG_PP_POR_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 820Ch
Figure 5-128 CTRLMMR_WKUP_PRG_PP_POR_STAT Register
3130292827262524
POK_CLRRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDPOK_VDD_MCU_OVPOK_VDDA_MCU_OV
R-0hR-XR-X
76543210
RESERVEDPOK_VDDA_PMIC_IN_UVPOK_VDD_MCU_UVPOK_VDDA_MCU_UV
R-0hR-XR-XR-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-264 CTRLMMR_WKUP_PRG_PP_POR_STAT Register Field Descriptions
BitFieldTypeResetDescription
31POK_CLRR/W0h

When set, resets pgood sticky bits for VDDA_MCU, VDD_MCU, and VDDA_PMIC_IN voltage POK detection.

30-10RESERVEDR0h

Reserved

9POK_VDD_MCU_OVRX

VDD_MCU overvoltage POK detection
0h - Voltage good
1h - Voltage above threshold

8POK_VDDA_MCU_OVRX

1.8V VDDA_MCU overvoltage POK detection
0h - Voltage good
1h - Voltage above threshold

7-3RESERVEDR0h

Reserved

2POK_VDDA_PMIC_IN_UVRX

VDDA_PMIC_IN undervoltage POK detection
0h - Voltage good
1h - Voltage below threshold

1POK_VDD_MCU_UVRX

VDD_MCU undervoltage POK detection
0h - Voltage good
1h - Voltage below threshold

0POK_VDDA_MCU_UVRX

1.8V VDDA_MCU undervoltage POK detection
0h - Voltage good
1h - Voltage below threshold

1.1.4.128 CTRLMMR_WKUP_PRG_PP_MAIN_CTRL Register ( Offset = 18210h) [reset = 2003Fh]

CTRLMMR_WKUP_PRG_PP_MAIN_CTRL is shown in Figure 5-129 and described in Table 5-266.

Return to Summary Table.

Configures the MAIN PRG_PP controller.

Table 5-265 CTRLMMR_WKUP_PRG_PP_MAIN_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8210h
Figure 5-129 CTRLMMR_WKUP_PRG_PP_MAIN_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDPOK_PP_ENRESERVEDDEGLITCH_SEL
R-0hR/W-0hR-0hR/W-2h
15141312111098
POK_EN_SELRESERVEDPOK_VMON_EXT_MAIN3P3_OV_SELPOK_VMON_EXT_MAIN1P8_OV_SELPOK_VMON_EXT_OV_SELPOK_VDDR_CORE_OV_SELPOK_VDD_CPU_OV_SELPOK_VDD_CORE_OV_SEL
R/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDPOK_VMON_EXT_MAIN3P3_ENPOK_VMON_EXT_MAIN1P8_ENPOK_VMON_EXT_ENPOK_VDDR_CORE_ENPOK_VDD_CPU_ENPOK_VDD_CORE_EN
R-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-266 CTRLMMR_WKUP_PRG_PP_MAIN_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h

Reserved

19POK_PP_ENR/W0h

POK ping-pong enable. When set, enables automatic switching between undervoltage and overvoltage detection on VDD_CORE, VDD_CPU, VDDR_CORE, VMON_EXT, VMON_EXT_MAIN1P8 and VMON_EXT_MAIN3P3. This bit has no effect if the POK's ov_sel bit = 1.
0h - No pingpong operation. UV/OV operation selected by each POK ov_sel bit
1h - Pingpong operation enabled .

18RESERVEDR0h

Reserved

17-16DEGLITCH_SELR/W2h

Deglitch period for PRG_PP_MAIN POKs

0h - 5 us

1h - 10 us

2h - 15 us

3h - 20 us

15POK_EN_SELR/W0h

Select POK enable source
0h - POK enables come from hardware tie-offs
1h - POK enables come from CTRLMMR_WKUP_PRG_PP_MAIN_CTRL register

14RESERVEDR0h

Reserved

13POK_VMON_EXT_MAIN3P3_OV_SELR/W0h

Force VMON_EXT_MAIN 3.3V POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

12POK_VMON_EXT_MAIN1P8_OV_SELR/W0h

Force VMON_EXT_MAIN 1.8V POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

11POK_VMON_EXT_OV_SELR/W0h

Force VMON_EXT POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

10POK_VDDR_CORE_OV_SELR/W0h

Force VDDR_CORE POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

9POK_VDD_CPU_OV_SELR/W0h

Force VDD_CPU POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

8POK_VDD_CORE_OV_SELR/W0h

Force VDD_CORE POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled.
0h - Undervoltage detection or UV/OV ping-pong operation
1- Overvoltage detection only

7-6RESERVEDR0h

Reserved

5POK_VMON_EXT_MAIN3P3_ENR/W1h

Enable VMON_EXT_MAIN 3.3V POK detection
0h - POK detection disabled
1h - POK detection enabled

4POK_VMON_EXT_MAIN1P8_ENR/W1h

Enable VMON_EXT_MAIN 1.8V POK detection
0h - POK detection disabled
1h - POK detection enabled

3POK_VMON_EXT_ENR/W1h

Enable VMON_EXT POK detection
0h - POK detection disabled
1h - POK detection enabled

2POK_VDDR_CORE_ENR/W1h

Enable VDDR_CORE POK detection
0h - POK detection disabled
1h - POK detection enabled

1POK_VDD_CPU_ENR/W1h

Enable VDD_CPU POK detection
0h - POK detection disabled
1h - POK detection enabled

0POK_VDD_CORE_ENR/W1h

Enable VDD_CORE POK detection
0h - POK detection disabled
1h - POK detection enabled

1.1.4.129 CTRLMMR_WKUP_PRG_PP_MAIN_STAT Register ( Offset = 18214h) [reset = X]

CTRLMMR_WKUP_PRG_PP_MAIN_STAT is shown in Figure 5-130 and described in Table 5-268.

Return to Summary Table.

Provides MAIN PRG_PP controller status and status clear control.

Table 5-267 CTRLMMR_WKUP_PRG_PP_MAIN_STAT Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8214h
Figure 5-130 CTRLMMR_WKUP_PRG_PP_MAIN_STAT Register
3130292827262524
POK_CLRRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDPOK_VMON_EXT_MAIN3P3_OVPOK_VMON_EXT_MAIN1P8_OVPOK_VMON_EXT_OVPOK_VDDR_CORE_OVPOK_VDD_CPU_OVPOK_VDD_CORE_OV
R-0hR-XR-XR-XR-XR-XR-X
76543210
RESERVEDPOK_VMON_EXT_MAIN3P3_UVPOK_VMON_EXT_MAIN1P8_UVPOK_VMON_EXT_UVPOK_VDDR_CORE_UVPOK_VDD_CPU_UVPOK_VDD_CORE_UV
R-0hR-XR-XR-XR-XR-XR-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-268 CTRLMMR_WKUP_PRG_PP_MAIN_STAT Register Field Descriptions
BitFieldTypeResetDescription
31POK_CLRR/W0h

When set, resets pgood sticky bits for V DD_CORE, VDD_CPU, VDDR_CORE, VMON_EXT, VMON_EXT_MAIN1P8, and VMON_EXT_MAIN3P3 voltage POK detection.

30-14RESERVEDR0h

Reserved

13POK_VMON_EXT_MAIN3P3_OVRX

VMON_EXT_MAIN 3.3V overvoltage POK
0h - Voltage good
1h - Voltage above threshold

12POK_VMON_EXT_MAIN1P8_OVRX

VMON_EXT_MAIN 1.8V overvoltage POK
0h - Voltage good
1h - Voltage above threshold

11POK_VMON_EXT_OVRX

VMON_EXT overvoltage POK
0h - Voltage good
1h - Voltage above threshold

10POK_VDDR_CORE_OVRX

VDDR_CORE overvoltage POK
0h - Voltage good
1h - Voltage above threshold

9POK_VDD_CPU_OVRX

VDD_CPU overvoltage POK
0h - Voltage good
1h - Voltage above threshold

8POK_VDD_CORE_OVRX

VDD_CORE overvoltage POK
0h - Voltage good
1h - Voltage above threshold

7-6RESERVEDR0h

Reserved

5POK_VMON_EXT_MAIN3P3_UVRX

VMON_EXT_MAIN 3.3V undervoltage POK
0h - Voltage good
1h - Voltage below threshold

4POK_VMON_EXT_MAIN1P8_UVRX

VMON_EXT_MAIN 1.8V undervoltage POK
0h - Voltage good
1h - Voltage below threshold

3POK_VMON_EXT_UVRX

VMON_EXT undervoltage POK
0h - Voltage good
1h - Voltage below threshold

2POK_VDDR_CORE_UVRX

VDDR_CORE undervoltage POK
0h - Voltage good
1h - Voltage below threshold

1POK_VDD_CPU_UVRX

VDD_CPU undervoltage POK
0h - Voltage good
1h - Voltage below threshold

0POK_VDD_CORE_UVRX

VDD_CORE undervoltage POK
0h - Voltage good
1h - Voltage below threshold

1.1.4.130 CTRLMMR_WKUP_CLKGATE_CTRL Register ( Offset = 18280h) [reset = X]

CTRLMMR_WKUP_CLKGATE_CTRL is shown in Figure 5-131 and described in Table 5-270.

Return to Summary Table.

Controls the power clock gating feature of WKUP domain modules and busses.

Table 5-269 CTRLMMR_WKUP_CLKGATE_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8280h
Figure 5-131 CTRLMMR_WKUP_CLKGATE_CTRL Register
3130292827262524
WKUP_NOGATE_RSVD
R/W-X
2322212019181716
WKUP_NOGATE_RSVD
R/W-X
15141312111098
WKUP_NOGATE_RSVD
R/W-X
76543210
WKUP_NOGATE_RSVDWKUP_ECC_AGG_NOGATEWKUP_FW_CBA_NOGATEWKUP_CBA_NOGATE
R/W-XR/W-XR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-270 CTRLMMR_WKUP_CLKGATE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3WKUP_NOGATE_RSVDR/WX

WKUP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

2WKUP_ECC_AGG_NOGATER/WX

WKUP ECC Aggregator clock gate disable
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

1WKUP_FW_CBA_NOGATER/W1h

WKUP domain Firewall bus (wkup_fw_cbass) clock gate disable
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

0WKUP_CBA_NOGATER/W1h

WKUP domain Data bus (wkup_cbass) clock gate disable
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

1.1.4.131 CTRLMMR_WKUP_MCU_CLKGATE_CTRL Register ( Offset = 18284h) [reset = X]

CTRLMMR_WKUP_MCU_CLKGATE_CTRL is shown in Figure 5-132 and described in Table 5-272.

Return to Summary Table.

Controls the power clock gating feature of MCU domain modules and busses.

Table 5-271 CTRLMMR_WKUP_MCU_CLKGATE_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8284h
Figure 5-132 CTRLMMR_WKUP_MCU_CLKGATE_CTRL Register
3130292827262524
MCU_PER_NOGATE_RSVD
R/W-X
2322212019181716
MCU_PER_NOGATE_RSVDMCU_PDMA_G2_NOGATEMCU_PDMA_G0_NOGATEMCU_PULSAR_NOGATEMCU_NAV_UDMASS_NOGATEMCU_NAV_MODSS_NOGATE
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
15141312111098
MCU_CBA_NOGATE_RSVD
R/W-X
76543210
MCU_CBA_NOGATE_RSVDMCU_DBG_CBA_NOGATEMCU_ECC_AGG_NOGATEMCU_FW_CBA_NOGATEMCU_CBA_NOGATE
R/W-XR/W-XR/W-XR/W-1hR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-272 CTRLMMR_WKUP_MCU_CLKGATE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-21MCU_PER_NOGATE_RSVDR/WX

MCU reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

20MCU_PDMA_G2_NOGATER/WX

MCU domain MCAN1/USART0 PDMA clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

19MCU_PDMA_G0_NOGATER/WX

MCU domain MCAN0/SPI0 PDMA clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

18MCU_PULSAR_NOGATER/WX

MCU domain Pulsar clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

17MCU_NAV_UDMASS_NOGATER/WX

MCU NavSS UDMA interface clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

16MCU_NAV_MODSS_NOGATER/WX

MCU NavSS MODSS interface clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

15-4MCU_CBA_NOGATE_RSVDR/WX

MCU reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

3MCU_DBG_CBA_NOGATER/WX

MCU domain Debug bus (mcu_dbg_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

2MCU_ECC_AGG_NOGATER/WX

MCU ECC Aggregator clock gate disable
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

1MCU_FW_CBA_NOGATER/W1h

MCU domain Firewall bus (mcu_fw_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

0MCU_CBA_NOGATER/W1h

MCU domain Data bus (mcu_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

1.1.4.132 CTRLMMR_WKUP_MAIN_CLKGATE_CTRL0 Register ( Offset = 18288h) [reset = X]

CTRLMMR_WKUP_MAIN_CLKGATE_CTRL0 is shown in Figure 5-133 and described in Table 5-274.

Return to Summary Table.

Controls the power clock gating feature of MAIN domain modules and busses.

Table 5-273 CTRLMMR_WKUP_MAIN_CLKGATE_CTRL0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8288h
Figure 5-133 CTRLMMR_WKUP_MAIN_CLKGATE_CTRL0 Register
3130292827262524
MAIN_CBA_NOGATE_RSVD
R/W-X
2322212019181716
MAIN_HC_CFG_CBA_NOGATEMAIN_HC_ECC_AGG_NOGATEMAIN_HC_FW_CBA_NOGATEMAIN_HC_CBA_NOGATEMAIN_DBG_DATA_CBA_NOGATEMAIN_DBG_CBA_NOGATEMAIN_IP_NOGATE_RSVDMAIN_IP_MCASP_CBA_NOGATE
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
15141312111098
MAIN_IP_NONSAFE_CBA_NOGATEMAIN_IP_ECC_AGGR_NOGATEMAIN_IP_FW_CBA_NOGATEMAIN_IP_CBA_NOGATEMAIN_RC_CFG_CBA_NOGATEMAIN_RC_ECC_AGG_NOGATEMAIN_RC_FW_CBA_NOGATEMAIN_RC_CBA_NOGATE
R/W-XR/W-XR/W-XR/W-1hR/W-XR/W-XR/W-XR/W-X
76543210
MAIN_INFRA_NOGATE_RSVDMAIN_PULSAR0_MEM_NOGATEMAIN_PULSAR0_SLV_NOGATEMAIN_INFRA_NONSAFE_CBA_NOGATEMAIN_INFRA_ECC_AGG_NOGATEMAIN_INFRA_FW_CBA_NOGATEMAIN_INFRA_CBA_NOGATE
R/W-XR/W-1hR/W-XR/W-XR/W-XR/W-XR/W-X
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-274 CTRLMMR_WKUP_MAIN_CLKGATE_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
31-24MAIN_CBA_NOGATE_RSVDR/WX

MAIN CBA reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

23MAIN_HC_CFG_CBA_NOGATER/WX

MAIN domain HC Configuration bus (hc_cfg_cbass_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

22MAIN_HC_ECC_AGG_NOGATER/WX

MAIN domain HC ECC aggregator (nogate) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

21MAIN_HC_FW_CBA_NOGATER/WX

MAIN domain HC Firewall bus (main_hc2_fw_cbass_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

20MAIN_HC_CBA_NOGATER/WX

MAIN domain HC Data bus (hc2_cbass_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

19MAIN_DBG_DATA_CBA_NOGATER/WX

MAIN domain Debug Data bus (debug_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

18MAIN_DBG_CBA_NOGATER/WX

MAIN domain Debug bus (debug_cbass_wrap_main_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

17MAIN_IP_NOGATE_RSVDR/WX

MAIN Interface Peripheral reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

16MAIN_IP_MCASP_CBA_NOGATER/WX

MAIN domain Interface Peripheral McASP IP bus (ipphy_mcasp_g0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

15MAIN_IP_NONSAFE_CBA_NOGATER/WX

MAIN domain Interface Peripheral nonsafety IP bus (ipphy_cbass_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

14MAIN_IP_ECC_AGGR_NOGATER/WX

MAIN domain Interface Peripheral ECC aggregator (main_spi0_g0_main_0_ecc_aggr_main_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

13MAIN_IP_FW_CBA_NOGATER/WX

MAIN domain Interface Peripheral Firewall bus (ipphy_cbass_main_fw_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

12MAIN_IP_CBA_NOGATER/W1h

MAIN domain Interface Peripheral bus (ipphy_safe_cbass_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

11MAIN_RC_CFG_CBA_NOGATER/WX

MAIN domain RC Configuration bus (rc_cfg_cbass_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

10MAIN_RC_ECC_AGG_NOGATER/WX

MAIN domain RC ECC aggregator (main_rc_ecc_aggr_main_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

9MAIN_RC_FW_CBA_NOGATER/WX

MAIN domain RC Firewall bus (rc_cbass_main_fw_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

8MAIN_RC_CBA_NOGATER/WX

MAIN domain RC Data bus (rc_cbass_0) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

7-6MAIN_INFRA_NOGATE_RSVDR/WX

MAIN Infrastructure reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

5MAIN_PULSAR0_MEM_NOGATER/W1h

MAIN domain Pulsar memory bus (pulsar0_mem_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

4MAIN_PULSAR0_SLV_NOGATER/WX

MAIN domain Pulsar slave bus (pulsar0_slv_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

3MAIN_INFRA_NONSAFE_CBA_NOGATER/WX

MAIN domain Infrastructure non-safety IP bus (main_infra_non_safe_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

2MAIN_INFRA_ECC_AGG_NOGATER/WX

MAIN domain Infrastructure ECC aggregator (main_infra_ecc_aggr) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

1MAIN_INFRA_FW_CBA_NOGATER/WX

MAIN domain Infrastructure Firewall bus (main_infra_fw_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

0MAIN_INFRA_CBA_NOGATER/WX

MAIN domain Infrastructure bus (main_infra_cbass) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

1.1.4.133 CTRLMMR_WKUP_MAIN_CLKGATE_CTRL1 Register ( Offset = 1828Ch) [reset = X]

CTRLMMR_WKUP_MAIN_CLKGATE_CTRL1 is shown in Figure 5-134 and described in Table 5-276.

Return to Summary Table.

Controls the power clock gating feature of MAIN domain modules and busses.

Table 5-275 CTRLMMR_WKUP_MAIN_CLKGATE_CTRL1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 828Ch
Figure 5-134 CTRLMMR_WKUP_MAIN_CLKGATE_CTRL1 Register
3130292827262524
MAIN_GMPC_STOG_P2M_NOGATEMAIN_STOG_NOGATE_RSVDMAIN_IP_STOG_M2P_NOGATEMAIN_IP_STOG_P2M_NOGATEMAIN_INFRA_STOG_M2P_NOGATEMAIN_INFRA_STOG_P2M_NOGATEMAIN_PDMA_NOGATE_RSVD
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
2322212019181716
MAIN_PDMA_NOGATE_RSVDMAIN_PDMA_MCAN_NOGATEMAIN_PDMA_USART_PSILSS_NOGATEMAIN_PDMA_SPI_G1_NOGATEMAIN_PDMA_SPI_G0_NOGATEMAIN_PDMA_SPI_PSILSS_NOGATE
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
15141312111098
MAIN_IP1_NOGATE_RSVDMAIN_PULSAR_NOGATE
R/W-XR/W-1h
76543210
MAIN_IP0_NOGATE_RSVDMAIN_NAV_MV_FW_NOGATEMAIN_NAV_VIRTSS_NOGATEMAIN_NAV_NBSS_NOGATEMAIN_NAV_UDMASS_NOGATEMAIN_NAV_MODSS_NOGATE
R/W-XR/W-XR/W-1hR/W-1hR/W-XR/W-X
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-276 CTRLMMR_WKUP_MAIN_CLKGATE_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
31MAIN_GMPC_STOG_P2M_NOGATER/WX

MAIN domain GPMC Slave Timeout Gasket output (rc_to_gpmc_stog_p2m_pwr_dis) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

30MAIN_STOG_NOGATE_RSVDR/WX

MAIN STOG clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

29MAIN_IP_STOG_M2P_NOGATER/WX

MAIN domain IP Slave Timeout Gasket output (ipphy_to_ipphy_stog_p2m_pwr_dis) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

28MAIN_IP_STOG_P2M_NOGATER/WX

MAIN domain IP Slave Timeout Gasket input (ipphy_to_ipphy_stog_p2m_pwr_dis) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

27MAIN_INFRA_STOG_M2P_NOGATER/WX

MAIN domain Infrastructure Slave Timeout Gasket output (main_infra_0_mst_stog_p2m_pwr_dis) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

26MAIN_INFRA_STOG_P2M_NOGATER/WX

MAIN domain Infrastructure Slave Timeout Gasket input (main_infra_0_mst_stog_p2m_pwr_dis) clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

25-21MAIN_PDMA_NOGATE_RSVDR/WX

MAIN PDMA clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

20MAIN_PDMA_MCAN_NOGATER/WX

MAIN domain PDMA MCAN clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

19MAIN_PDMA_USART_PSILSS_NOGATER/WX

MAIN domain PDMA USART PSILSS clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

18MAIN_PDMA_SPI_G1_NOGATER/WX

MAIN domain PDMA SPI_G1 clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

17MAIN_PDMA_SPI_G0_NOGATER/WX

MAIN domain PDMA SPI_G0 clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

16MAIN_PDMA_SPI_PSILSS_NOGATER/WX

MAIN domain PDMA SPI PSILSS clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

15-9MAIN_IP1_NOGATE_RSVDR/WX

MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

8MAIN_PULSAR_NOGATER/W1h

MAIN domain Pulsar clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

7-5MAIN_IP0_NOGATE_RSVDR/WX

MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

4MAIN_NAV_MV_FW_NOGATER/WX

MAIN NavSS Mod/Virt Firewall interface clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

3MAIN_NAV_VIRTSS_NOGATER/W1h

MAIN NavSS VIRTSS interface clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

2MAIN_NAV_NBSS_NOGATER/W1h

MAIN NavSS NB interface clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

1MAIN_NAV_UDMASS_NOGATER/WX

Main NavSS UDMA interface clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

0MAIN_NAV_MODSS_NOGATER/WX

MAIN NavSS MODSS interface clock gate disable.
0h - Clocks are gated on idle for power savings
1h - Clocks are not gated on idle, power saving disabled

1.1.4.134 CTRLMMR_WKUP_CANUART_WAKE_CTRL Register ( Offset = 18300h) [reset = 0h]

CTRLMMR_WKUP_CANUART_WAKE_CTRL is shown in Figure 5-135 and described in Table 5-278.

Return to Summary Table.

Controls the operation of IO wakeup on the MAIN CANUART pins.

Table 5-277 CTRLMMR_WKUP_CANUART_WAKE_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8300h
Figure 5-135 CTRLMMR_WKUP_CANUART_WAKE_CTRL Register
3130292827262524
MW
R/W-0h
2322212019181716
MW
R/W-0h
15141312111098
MW
R/W-0h
76543210
MWMW_LOAD_EN
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-278 CTRLMMR_WKUP_CANUART_WAKE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-1MWR/W0h

CANUART IO magic word.
This 31-bit value that enables placing of the CANUART I/Os into isolation for daisy-chain wakeup operation.

0x2AAAAAAA - Magic word value to enable isolation when qualified with mw_load bit
Others - Any other value will prevent isolation when mw_load transitions from 0 to 1.

0MW_LOAD_ENR/W0h

Magic word load enable
Setting this bit to 1 loads and locks the mw field for CANUART IO isolation. If the mw field matches the magic word value then the value is latched into the CANUART IO voltage domain and CANUART IO isolation is enabled.
0h - Unlock and do not load mw value for comparison
1h - Load and lock mw for magic word value comparison

1.1.4.135 CTRLMMR_WKUP_CANUART_WAKE_STAT0 Register ( Offset = 18308h) [reset = X]

CTRLMMR_WKUP_CANUART_WAKE_STAT0 is shown in Figure 5-136 and described in Table 5-280.

Return to Summary Table.

Provides the status of MAIN CANUART_WAKE control bits These bits come from the daisy-chain wakeup logic and maintain their value across core powerdown if isolation is enabled.

Table 5-279 CTRLMMR_WKUP_CANUART_WAKE_STAT0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8308h
Figure 5-136 CTRLMMR_WKUP_CANUART_WAKE_STAT0 Register
3130292827262524
MW_STAT
R-X
2322212019181716
MW_STAT
R-X
15141312111098
MW_STAT
R-X
76543210
MW_STATMW_LOAD_STAT
R-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-280 CTRLMMR_WKUP_CANUART_WAKE_STAT0 Register Field Descriptions
BitFieldTypeResetDescription
31-1MW_STATRX

CANUART magic word status
Indicates the latched value of the mw field.

0MW_LOAD_STATRX

Magic word load status.
Indicates the latched value of the mw_load_en bit

1.1.4.136 CTRLMMR_WKUP_CANUART_WAKE_STAT1 Register ( Offset = 1830Ch) [reset = X]

CTRLMMR_WKUP_CANUART_WAKE_STAT1 is shown in Figure 5-137 and described in Table 5-282.

Return to Summary Table.

Provides MAIN CANUART IO isolation status These bits come from the daisy-chain wakeup logic and maintain their value across core powerdown if isolation is enabled.

Table 5-281 CTRLMMR_WKUP_CANUART_WAKE_STAT1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 830Ch
Figure 5-137 CTRLMMR_WKUP_CANUART_WAKE_STAT1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCANUART_IO_MODE
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-282 CTRLMMR_WKUP_CANUART_WAKE_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0CANUART_IO_MODERX

Indicates if CANUART IO wakeup mode is enabled.
0h - Not enabled (load_en not set or mw doesn't match magic word)
1h - CANUART IO mode enabled

1.1.4.137 CTRLMMR_WKUP_MCU_GEN_WAKE_CTRL Register ( Offset = 18310h) [reset = 0h]

CTRLMMR_WKUP_MCU_GEN_WAKE_CTRL is shown in Figure 5-138 and described in Table 5-284.

Return to Summary Table.

Controls the operation of IO wakeup on the MCU_GENERAL pins.

Table 5-283 CTRLMMR_WKUP_MCU_GEN_WAKE_CTRL Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8310h
Figure 5-138 CTRLMMR_WKUP_MCU_GEN_WAKE_CTRL Register
3130292827262524
MW
R/W-0h
2322212019181716
MW
R/W-0h
15141312111098
MW
R/W-0h
76543210
MWMW_LOAD_EN
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-284 CTRLMMR_WKUP_MCU_GEN_WAKE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-1MWR/W0h

MCU_GENERAL IO magic word.
This 31-bit value that enables placing of the MCU_GENERAL I/Os into isolation for daisy-chain wakeup operation.

0x2AAAAAAA - Magic word value to enable isolation when qualified with mw_load bit
Others - Any other value will prevent isolation when mw_load transitions from 0 to 1.

0MW_LOAD_ENR/W0h

Magic word load enable
Setting this bit to 1 loads and locks the mw field for MCU_GENERAL IO isolation. If the mw field matches the magic word value then the value is latched into the MCU_GENERAL IO voltage domain and MCU_GENERAL IO isolation is enabled.
0h - Unlock and do not load mw value for comparison
1h - Load and lock mw for magic word value comparison

1.1.4.138 CTRLMMR_WKUP_MCU_GEN_WAKE_STAT0 Register ( Offset = 18318h) [reset = X]

CTRLMMR_WKUP_MCU_GEN_WAKE_STAT0 is shown in Figure 5-139 and described in Table 5-286.

Return to Summary Table.

Provides the status of MCU_GEN_WAKE control bits These bits come from the daisy-chain wakeup logic and maintain their value across core powerdown if isolation is enabled.

Table 5-285 CTRLMMR_WKUP_MCU_GEN_WAKE_STAT0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 8318h
Figure 5-139 CTRLMMR_WKUP_MCU_GEN_WAKE_STAT0 Register
3130292827262524
MW_STAT
R-X
2322212019181716
MW_STAT
R-X
15141312111098
MW_STAT
R-X
76543210
MW_STATMW_LOAD_STAT
R-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-286 CTRLMMR_WKUP_MCU_GEN_WAKE_STAT0 Register Field Descriptions
BitFieldTypeResetDescription
31-1MW_STATRX

MCU_GENERAL magic word status
Indicates the latched value of the mw field.

0MW_LOAD_STATRX

Magic word load status.
Indicates the latched value of the mw_load_en bit

1.1.4.139 CTRLMMR_WKUP_MCU_GEN_WAKE_STAT1 Register ( Offset = 1831Ch) [reset = X]

CTRLMMR_WKUP_MCU_GEN_WAKE_STAT1 is shown in Figure 5-140 and described in Table 5-288.

Return to Summary Table.

Provides MCU_GENERAL IO isolation status These bits come from the daisy-chain wakeup logic and maintain their value across core powerdown if isolation is enabled.

Table 5-287 CTRLMMR_WKUP_MCU_GEN_WAKE_STAT1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 831Ch
Figure 5-140 CTRLMMR_WKUP_MCU_GEN_WAKE_STAT1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMCU_GEN_IO_MODE
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-288 CTRLMMR_WKUP_MCU_GEN_WAKE_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0MCU_GEN_IO_MODERX

Indicates if MCU_GENERAL IO wakeup mode is enabled.
0h - Not enabled (load_en not set or mw doesn't match magic word)
1h - MCU_GENERAL IO mode enabled

1.1.4.140 CTRLMMR_WKUP_LOCK6_KICK0 Register ( Offset = 19008h) [reset = 0h]

CTRLMMR_WKUP_LOCK6_KICK0 is shown in Figure 5-141 and described in Table 5-290.

Return to Summary Table.

Lower 32-bits of Partition6 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_WKUP_LOCK6_KICK1 with its key value before write-protected Partition 6 registers can be written.

Table 5-289 CTRLMMR_WKUP_LOCK6_KICK0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 9008h
Figure 5-141 CTRLMMR_WKUP_LOCK6_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-290 CTRLMMR_WKUP_LOCK6_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers

0UNLOCKEDR0h

Unlock status.
When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.4.141 CTRLMMR_WKUP_LOCK6_KICK1 Register ( Offset = 1900Ch) [reset = 0h]

CTRLMMR_WKUP_LOCK6_KICK1 is shown in Figure 5-142 and described in Table 5-292.

Return to Summary Table.

Upper 32-bits of Partition 6 write lock key. This register must be written with the designated key value after a write to CTRLMMR_WKUP_LOCK6_KICK0 with its key value before write-protected Partition 6 registers can be written.

Table 5-291 CTRLMMR_WKUP_LOCK6_KICK1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 900Ch
Figure 5-142 CTRLMMR_WKUP_LOCK6_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-292 CTRLMMR_WKUP_LOCK6_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition6 registers

1.1.4.142 CTRLMMR_WKUP_PADCONFIG0 Register ( Offset = 1C000h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG0 is shown in Figure 5-143 and described in Table 5-294.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-293 CTRLMMR_WKUP_PADCONFIG0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C000h
Figure 5-143 CTRLMMR_WKUP_PADCONFIG0 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-294 CTRLMMR_WKUP_PADCONFIG0 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.143 CTRLMMR_WKUP_PADCONFIG1 Register ( Offset = 1C004h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG1 is shown in Figure 5-144 and described in Table 5-296.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-295 CTRLMMR_WKUP_PADCONFIG1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C004h
Figure 5-144 CTRLMMR_WKUP_PADCONFIG1 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-296 CTRLMMR_WKUP_PADCONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.144 CTRLMMR_WKUP_PADCONFIG2 Register ( Offset = 1C008h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG2 is shown in Figure 5-145 and described in Table 5-298.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-297 CTRLMMR_WKUP_PADCONFIG2 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C008h
Figure 5-145 CTRLMMR_WKUP_PADCONFIG2 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-298 CTRLMMR_WKUP_PADCONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.145 CTRLMMR_WKUP_PADCONFIG3 Register ( Offset = 1C00Ch) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG3 is shown in Figure 5-146 and described in Table 5-300.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-299 CTRLMMR_WKUP_PADCONFIG3 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C00Ch
Figure 5-146 CTRLMMR_WKUP_PADCONFIG3 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-300 CTRLMMR_WKUP_PADCONFIG3 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.146 CTRLMMR_WKUP_PADCONFIG4 Register ( Offset = 1C010h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG4 is shown in Figure 5-147 and described in Table 5-302.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-301 CTRLMMR_WKUP_PADCONFIG4 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C010h
Figure 5-147 CTRLMMR_WKUP_PADCONFIG4 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-302 CTRLMMR_WKUP_PADCONFIG4 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.147 CTRLMMR_WKUP_PADCONFIG5 Register ( Offset = 1C014h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG5 is shown in Figure 5-148 and described in Table 5-304.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-303 CTRLMMR_WKUP_PADCONFIG5 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C014h
Figure 5-148 CTRLMMR_WKUP_PADCONFIG5 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-304 CTRLMMR_WKUP_PADCONFIG5 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.148 CTRLMMR_WKUP_PADCONFIG6 Register ( Offset = 1C018h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG6 is shown in Figure 5-149 and described in Table 5-306.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-305 CTRLMMR_WKUP_PADCONFIG6 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C018h
Figure 5-149 CTRLMMR_WKUP_PADCONFIG6 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-306 CTRLMMR_WKUP_PADCONFIG6 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.149 CTRLMMR_WKUP_PADCONFIG7 Register ( Offset = 1C01Ch) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG7 is shown in Figure 5-150 and described in Table 5-308.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-307 CTRLMMR_WKUP_PADCONFIG7 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C01Ch
Figure 5-150 CTRLMMR_WKUP_PADCONFIG7 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-308 CTRLMMR_WKUP_PADCONFIG7 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.150 CTRLMMR_WKUP_PADCONFIG8 Register ( Offset = 1C020h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG8 is shown in Figure 5-151 and described in Table 5-310.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-309 CTRLMMR_WKUP_PADCONFIG8 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C020h
Figure 5-151 CTRLMMR_WKUP_PADCONFIG8 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-310 CTRLMMR_WKUP_PADCONFIG8 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.151 CTRLMMR_WKUP_PADCONFIG9 Register ( Offset = 1C024h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG9 is shown in Figure 5-152 and described in Table 5-312.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-311 CTRLMMR_WKUP_PADCONFIG9 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C024h
Figure 5-152 CTRLMMR_WKUP_PADCONFIG9 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-312 CTRLMMR_WKUP_PADCONFIG9 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.152 CTRLMMR_WKUP_PADCONFIG10 Register ( Offset = 1C028h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG10 is shown in Figure 5-153 and described in Table 5-314.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-313 CTRLMMR_WKUP_PADCONFIG10 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C028h
Figure 5-153 CTRLMMR_WKUP_PADCONFIG10 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-314 CTRLMMR_WKUP_PADCONFIG10 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.153 CTRLMMR_WKUP_PADCONFIG11 Register ( Offset = 1C02Ch) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG11 is shown in Figure 5-154 and described in Table 5-316.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-315 CTRLMMR_WKUP_PADCONFIG11 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C02Ch
Figure 5-154 CTRLMMR_WKUP_PADCONFIG11 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-316 CTRLMMR_WKUP_PADCONFIG11 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.154 CTRLMMR_WKUP_PADCONFIG12 Register ( Offset = 1C030h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG12 is shown in Figure 5-155 and described in Table 5-318.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-317 CTRLMMR_WKUP_PADCONFIG12 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C030h
Figure 5-155 CTRLMMR_WKUP_PADCONFIG12 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-318 CTRLMMR_WKUP_PADCONFIG12 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.155 CTRLMMR_WKUP_PADCONFIG14 Register ( Offset = 1C038h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG14 is shown in Figure 5-156 and described in Table 5-320.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-319 CTRLMMR_WKUP_PADCONFIG14 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C038h
Figure 5-156 CTRLMMR_WKUP_PADCONFIG14 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-320 CTRLMMR_WKUP_PADCONFIG14 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.156 CTRLMMR_WKUP_PADCONFIG15 Register ( Offset = 1C03Ch) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG15 is shown in Figure 5-157 and described in Table 5-322.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-321 CTRLMMR_WKUP_PADCONFIG15 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C03Ch
Figure 5-157 CTRLMMR_WKUP_PADCONFIG15 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-322 CTRLMMR_WKUP_PADCONFIG15 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.157 CTRLMMR_WKUP_PADCONFIG26 Register ( Offset = 1C068h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG26 is shown in Figure 5-158 and described in Table 5-324.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-323 CTRLMMR_WKUP_PADCONFIG26 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C068h
Figure 5-158 CTRLMMR_WKUP_PADCONFIG26 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-324 CTRLMMR_WKUP_PADCONFIG26 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.158 CTRLMMR_WKUP_PADCONFIG27 Register ( Offset = 1C06Ch) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG27 is shown in Figure 5-159 and described in Table 5-326.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-325 CTRLMMR_WKUP_PADCONFIG27 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C06Ch
Figure 5-159 CTRLMMR_WKUP_PADCONFIG27 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-326 CTRLMMR_WKUP_PADCONFIG27 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.159 CTRLMMR_WKUP_PADCONFIG28 Register ( Offset = 1C070h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG28 is shown in Figure 5-160 and described in Table 5-328.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-327 CTRLMMR_WKUP_PADCONFIG28 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C070h
Figure 5-160 CTRLMMR_WKUP_PADCONFIG28 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-328 CTRLMMR_WKUP_PADCONFIG28 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.160 CTRLMMR_WKUP_PADCONFIG29 Register ( Offset = 1C074h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG29 is shown in Figure 5-161 and described in Table 5-330.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-329 CTRLMMR_WKUP_PADCONFIG29 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C074h
Figure 5-161 CTRLMMR_WKUP_PADCONFIG29 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-330 CTRLMMR_WKUP_PADCONFIG29 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.161 CTRLMMR_WKUP_PADCONFIG30 Register ( Offset = 1C078h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG30 is shown in Figure 5-162 and described in Table 5-332.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-331 CTRLMMR_WKUP_PADCONFIG30 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C078h
Figure 5-162 CTRLMMR_WKUP_PADCONFIG30 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-332 CTRLMMR_WKUP_PADCONFIG30 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.162 CTRLMMR_WKUP_PADCONFIG31 Register ( Offset = 1C07Ch) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG31 is shown in Figure 5-163 and described in Table 5-334.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-333 CTRLMMR_WKUP_PADCONFIG31 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C07Ch
Figure 5-163 CTRLMMR_WKUP_PADCONFIG31 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-334 CTRLMMR_WKUP_PADCONFIG31 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.163 CTRLMMR_WKUP_PADCONFIG32 Register ( Offset = 1C080h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG32 is shown in Figure 5-164 and described in Table 5-336.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-335 CTRLMMR_WKUP_PADCONFIG32 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C080h
Figure 5-164 CTRLMMR_WKUP_PADCONFIG32 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-336 CTRLMMR_WKUP_PADCONFIG32 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.164 CTRLMMR_WKUP_PADCONFIG33 Register ( Offset = 1C084h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG33 is shown in Figure 5-165 and described in Table 5-338.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-337 CTRLMMR_WKUP_PADCONFIG33 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C084h
Figure 5-165 CTRLMMR_WKUP_PADCONFIG33 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-338 CTRLMMR_WKUP_PADCONFIG33 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.165 CTRLMMR_WKUP_PADCONFIG34 Register ( Offset = 1C088h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG34 is shown in Figure 5-166 and described in Table 5-340.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-339 CTRLMMR_WKUP_PADCONFIG34 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C088h
Figure 5-166 CTRLMMR_WKUP_PADCONFIG34 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-340 CTRLMMR_WKUP_PADCONFIG34 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.166 CTRLMMR_WKUP_PADCONFIG35 Register ( Offset = 1C08Ch) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG35 is shown in Figure 5-167 and described in Table 5-342.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-341 CTRLMMR_WKUP_PADCONFIG35 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C08Ch
Figure 5-167 CTRLMMR_WKUP_PADCONFIG35 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-342 CTRLMMR_WKUP_PADCONFIG35 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.167 CTRLMMR_WKUP_PADCONFIG36 Register ( Offset = 1C090h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG36 is shown in Figure 5-168 and described in Table 5-344.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-343 CTRLMMR_WKUP_PADCONFIG36 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C090h
Figure 5-168 CTRLMMR_WKUP_PADCONFIG36 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-344 CTRLMMR_WKUP_PADCONFIG36 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.168 CTRLMMR_WKUP_PADCONFIG37 Register ( Offset = 1C094h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG37 is shown in Figure 5-169 and described in Table 5-346.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-345 CTRLMMR_WKUP_PADCONFIG37 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C094h
Figure 5-169 CTRLMMR_WKUP_PADCONFIG37 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-346 CTRLMMR_WKUP_PADCONFIG37 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.169 CTRLMMR_WKUP_PADCONFIG38 Register ( Offset = 1C098h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG38 is shown in Figure 5-170 and described in Table 5-348.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-347 CTRLMMR_WKUP_PADCONFIG38 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C098h
Figure 5-170 CTRLMMR_WKUP_PADCONFIG38 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-348 CTRLMMR_WKUP_PADCONFIG38 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.170 CTRLMMR_WKUP_PADCONFIG39 Register ( Offset = 1C09Ch) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG39 is shown in Figure 5-171 and described in Table 5-350.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-349 CTRLMMR_WKUP_PADCONFIG39 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C09Ch
Figure 5-171 CTRLMMR_WKUP_PADCONFIG39 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-350 CTRLMMR_WKUP_PADCONFIG39 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.171 CTRLMMR_WKUP_PADCONFIG40 Register ( Offset = 1C0A0h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG40 is shown in Figure 5-172 and described in Table 5-352.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-351 CTRLMMR_WKUP_PADCONFIG40 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0A0h
Figure 5-172 CTRLMMR_WKUP_PADCONFIG40 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-352 CTRLMMR_WKUP_PADCONFIG40 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.172 CTRLMMR_WKUP_PADCONFIG41 Register ( Offset = 1C0A4h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG41 is shown in Figure 5-173 and described in Table 5-354.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-353 CTRLMMR_WKUP_PADCONFIG41 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0A4h
Figure 5-173 CTRLMMR_WKUP_PADCONFIG41 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-354 CTRLMMR_WKUP_PADCONFIG41 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.173 CTRLMMR_WKUP_PADCONFIG42 Register ( Offset = 1C0A8h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG42 is shown in Figure 5-174 and described in Table 5-356.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-355 CTRLMMR_WKUP_PADCONFIG42 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0A8h
Figure 5-174 CTRLMMR_WKUP_PADCONFIG42 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-356 CTRLMMR_WKUP_PADCONFIG42 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.174 CTRLMMR_WKUP_PADCONFIG43 Register ( Offset = 1C0ACh) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG43 is shown in Figure 5-175 and described in Table 5-358.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-357 CTRLMMR_WKUP_PADCONFIG43 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0ACh
Figure 5-175 CTRLMMR_WKUP_PADCONFIG43 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-358 CTRLMMR_WKUP_PADCONFIG43 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.175 CTRLMMR_WKUP_PADCONFIG44 Register ( Offset = 1C0B0h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG44 is shown in Figure 5-176 and described in Table 5-360.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-359 CTRLMMR_WKUP_PADCONFIG44 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0B0h
Figure 5-176 CTRLMMR_WKUP_PADCONFIG44 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-360 CTRLMMR_WKUP_PADCONFIG44 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.176 CTRLMMR_WKUP_PADCONFIG45 Register ( Offset = 1C0B4h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG45 is shown in Figure 5-177 and described in Table 5-362.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-361 CTRLMMR_WKUP_PADCONFIG45 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0B4h
Figure 5-177 CTRLMMR_WKUP_PADCONFIG45 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-362 CTRLMMR_WKUP_PADCONFIG45 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.177 CTRLMMR_WKUP_PADCONFIG46 Register ( Offset = 1C0B8h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG46 is shown in Figure 5-178 and described in Table 5-364.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-363 CTRLMMR_WKUP_PADCONFIG46 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0B8h
Figure 5-178 CTRLMMR_WKUP_PADCONFIG46 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-364 CTRLMMR_WKUP_PADCONFIG46 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.178 CTRLMMR_WKUP_PADCONFIG47 Register ( Offset = 1C0BCh) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG47 is shown in Figure 5-179 and described in Table 5-366.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-365 CTRLMMR_WKUP_PADCONFIG47 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0BCh
Figure 5-179 CTRLMMR_WKUP_PADCONFIG47 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-366 CTRLMMR_WKUP_PADCONFIG47 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.179 CTRLMMR_WKUP_PADCONFIG48 Register ( Offset = 1C0C0h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG48 is shown in Figure 5-180 and described in Table 5-368.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-367 CTRLMMR_WKUP_PADCONFIG48 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0C0h
Figure 5-180 CTRLMMR_WKUP_PADCONFIG48 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-368 CTRLMMR_WKUP_PADCONFIG48 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.180 CTRLMMR_WKUP_PADCONFIG49 Register ( Offset = 1C0C4h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG49 is shown in Figure 5-181 and described in Table 5-370.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-369 CTRLMMR_WKUP_PADCONFIG49 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0C4h
Figure 5-181 CTRLMMR_WKUP_PADCONFIG49 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-370 CTRLMMR_WKUP_PADCONFIG49 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.181 CTRLMMR_WKUP_PADCONFIG50 Register ( Offset = 1C0C8h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG50 is shown in Figure 5-182 and described in Table 5-372.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-371 CTRLMMR_WKUP_PADCONFIG50 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0C8h
Figure 5-182 CTRLMMR_WKUP_PADCONFIG50 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-372 CTRLMMR_WKUP_PADCONFIG50 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.182 CTRLMMR_WKUP_PADCONFIG51 Register ( Offset = 1C0CCh) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG51 is shown in Figure 5-183 and described in Table 5-374.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-373 CTRLMMR_WKUP_PADCONFIG51 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0CCh
Figure 5-183 CTRLMMR_WKUP_PADCONFIG51 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-374 CTRLMMR_WKUP_PADCONFIG51 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.183 CTRLMMR_WKUP_PADCONFIG52 Register ( Offset = 1C0D0h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG52 is shown in Figure 5-184 and described in Table 5-376.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-375 CTRLMMR_WKUP_PADCONFIG52 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0D0h
Figure 5-184 CTRLMMR_WKUP_PADCONFIG52 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-376 CTRLMMR_WKUP_PADCONFIG52 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.184 CTRLMMR_WKUP_PADCONFIG53 Register ( Offset = 1C0D4h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG53 is shown in Figure 5-185 and described in Table 5-378.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-377 CTRLMMR_WKUP_PADCONFIG53 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0D4h
Figure 5-185 CTRLMMR_WKUP_PADCONFIG53 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-378 CTRLMMR_WKUP_PADCONFIG53 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.185 CTRLMMR_WKUP_PADCONFIG54 Register ( Offset = 1C0D8h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG54 is shown in Figure 5-186 and described in Table 5-380.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-379 CTRLMMR_WKUP_PADCONFIG54 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0D8h
Figure 5-186 CTRLMMR_WKUP_PADCONFIG54 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-380 CTRLMMR_WKUP_PADCONFIG54 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.186 CTRLMMR_WKUP_PADCONFIG55 Register ( Offset = 1C0DCh) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG55 is shown in Figure 5-187 and described in Table 5-382.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-381 CTRLMMR_WKUP_PADCONFIG55 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0DCh
Figure 5-187 CTRLMMR_WKUP_PADCONFIG55 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-382 CTRLMMR_WKUP_PADCONFIG55 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.187 CTRLMMR_WKUP_PADCONFIG56 Register ( Offset = 1C0E0h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG56 is shown in Figure 5-188 and described in Table 5-384.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-383 CTRLMMR_WKUP_PADCONFIG56 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0E0h
Figure 5-188 CTRLMMR_WKUP_PADCONFIG56 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-384 CTRLMMR_WKUP_PADCONFIG56 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.188 CTRLMMR_WKUP_PADCONFIG57 Register ( Offset = 1C0E4h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG57 is shown in Figure 5-189 and described in Table 5-386.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-385 CTRLMMR_WKUP_PADCONFIG57 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0E4h
Figure 5-189 CTRLMMR_WKUP_PADCONFIG57 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-386 CTRLMMR_WKUP_PADCONFIG57 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.189 CTRLMMR_WKUP_PADCONFIG58 Register ( Offset = 1C0E8h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG58 is shown in Figure 5-190 and described in Table 5-388.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-387 CTRLMMR_WKUP_PADCONFIG58 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0E8h
Figure 5-190 CTRLMMR_WKUP_PADCONFIG58 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-388 CTRLMMR_WKUP_PADCONFIG58 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.190 CTRLMMR_WKUP_PADCONFIG59 Register ( Offset = 1C0ECh) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG59 is shown in Figure 5-191 and described in Table 5-390.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-389 CTRLMMR_WKUP_PADCONFIG59 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0ECh
Figure 5-191 CTRLMMR_WKUP_PADCONFIG59 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-390 CTRLMMR_WKUP_PADCONFIG59 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.191 CTRLMMR_WKUP_PADCONFIG60 Register ( Offset = 1C0F0h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG60 is shown in Figure 5-192 and described in Table 5-392.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-391 CTRLMMR_WKUP_PADCONFIG60 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0F0h
Figure 5-192 CTRLMMR_WKUP_PADCONFIG60 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-392 CTRLMMR_WKUP_PADCONFIG60 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.192 CTRLMMR_WKUP_PADCONFIG61 Register ( Offset = 1C0F4h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG61 is shown in Figure 5-193 and described in Table 5-394.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-393 CTRLMMR_WKUP_PADCONFIG61 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0F4h
Figure 5-193 CTRLMMR_WKUP_PADCONFIG61 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-394 CTRLMMR_WKUP_PADCONFIG61 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.193 CTRLMMR_WKUP_PADCONFIG62 Register ( Offset = 1C0F8h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG62 is shown in Figure 5-194 and described in Table 5-396.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-395 CTRLMMR_WKUP_PADCONFIG62 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0F8h
Figure 5-194 CTRLMMR_WKUP_PADCONFIG62 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-396 CTRLMMR_WKUP_PADCONFIG62 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.194 CTRLMMR_WKUP_PADCONFIG63 Register ( Offset = 1C0FCh) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG63 is shown in Figure 5-195 and described in Table 5-398.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-397 CTRLMMR_WKUP_PADCONFIG63 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C0FCh
Figure 5-195 CTRLMMR_WKUP_PADCONFIG63 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-398 CTRLMMR_WKUP_PADCONFIG63 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.195 CTRLMMR_WKUP_PADCONFIG64 Register ( Offset = 1C100h) [reset = 44000h]

CTRLMMR_WKUP_PADCONFIG64 is shown in Figure 5-196 and described in Table 5-400.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-399 CTRLMMR_WKUP_PADCONFIG64 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C100h
Figure 5-196 CTRLMMR_WKUP_PADCONFIG64 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENRESERVEDDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVERESERVED
R/W-0hR/W-0hR/W-0hR-0hR/W-1hR-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-400 CTRLMMR_WKUP_PADCONFIG64 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28-27RESERVEDR0h

Reserved

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17-16RESERVEDR0h

Reserved

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.196 CTRLMMR_WKUP_PADCONFIG65 Register ( Offset = 1C104h) [reset = 44000h]

CTRLMMR_WKUP_PADCONFIG65 is shown in Figure 5-197 and described in Table 5-402.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-401 CTRLMMR_WKUP_PADCONFIG65 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C104h
Figure 5-197 CTRLMMR_WKUP_PADCONFIG65 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENRESERVEDDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVERESERVED
R/W-0hR/W-0hR/W-0hR-0hR/W-1hR-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-402 CTRLMMR_WKUP_PADCONFIG65 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28-27RESERVEDR0h

Reserved

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17-16RESERVEDR0h

Reserved

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.197 CTRLMMR_WKUP_PADCONFIG66 Register ( Offset = 1C108h) [reset = 44000h]

CTRLMMR_WKUP_PADCONFIG66 is shown in Figure 5-198 and described in Table 5-404.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-403 CTRLMMR_WKUP_PADCONFIG66 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C108h
Figure 5-198 CTRLMMR_WKUP_PADCONFIG66 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENRESERVEDDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVERESERVED
R/W-0hR/W-0hR/W-0hR-0hR/W-1hR-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-404 CTRLMMR_WKUP_PADCONFIG66 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28-27RESERVEDR0h

Reserved

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17-16RESERVEDR0h

Reserved

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.198 CTRLMMR_WKUP_PADCONFIG67 Register ( Offset = 1C10Ch) [reset = 44000h]

CTRLMMR_WKUP_PADCONFIG67 is shown in Figure 5-199 and described in Table 5-406.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-405 CTRLMMR_WKUP_PADCONFIG67 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C10Ch
Figure 5-199 CTRLMMR_WKUP_PADCONFIG67 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENRESERVEDDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVERESERVED
R/W-0hR/W-0hR/W-0hR-0hR/W-1hR-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-406 CTRLMMR_WKUP_PADCONFIG67 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28-27RESERVEDR0h

Reserved

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17-16RESERVEDR0h

Reserved

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.199 CTRLMMR_WKUP_PADCONFIG68 Register ( Offset = 1C110h) [reset = 8214007h]

CTRLMMR_WKUP_PADCONFIG68 is shown in Figure 5-200 and described in Table 5-408.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-407 CTRLMMR_WKUP_PADCONFIG68 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C110h
Figure 5-200 CTRLMMR_WKUP_PADCONFIG68 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-408 CTRLMMR_WKUP_PADCONFIG68 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.200 CTRLMMR_WKUP_PADCONFIG69 Register ( Offset = 1C114h) [reset = 44000h]

CTRLMMR_WKUP_PADCONFIG69 is shown in Figure 5-201 and described in Table 5-410.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-409 CTRLMMR_WKUP_PADCONFIG69 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C114h
Figure 5-201 CTRLMMR_WKUP_PADCONFIG69 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-410 CTRLMMR_WKUP_PADCONFIG69 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.201 CTRLMMR_WKUP_PADCONFIG70 Register ( Offset = 1C118h) [reset = 10264000h]

CTRLMMR_WKUP_PADCONFIG70 is shown in Figure 5-202 and described in Table 5-412.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-411 CTRLMMR_WKUP_PADCONFIG70 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C118h
Figure 5-202 CTRLMMR_WKUP_PADCONFIG70 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-412 CTRLMMR_WKUP_PADCONFIG70 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W1h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W1h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.202 CTRLMMR_WKUP_PADCONFIG71 Register ( Offset = 1C11Ch) [reset = 8014000h]

CTRLMMR_WKUP_PADCONFIG71 is shown in Figure 5-203 and described in Table 5-414.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-413 CTRLMMR_WKUP_PADCONFIG71 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C11Ch
Figure 5-203 CTRLMMR_WKUP_PADCONFIG71 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-414 CTRLMMR_WKUP_PADCONFIG71 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.203 CTRLMMR_WKUP_PADCONFIG72 Register ( Offset = 1C120h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG72 is shown in Figure 5-204 and described in Table 5-416.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-415 CTRLMMR_WKUP_PADCONFIG72 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C120h
Figure 5-204 CTRLMMR_WKUP_PADCONFIG72 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-416 CTRLMMR_WKUP_PADCONFIG72 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.204 CTRLMMR_WKUP_PADCONFIG73 Register ( Offset = 1C124h) [reset = 10264000h]

CTRLMMR_WKUP_PADCONFIG73 is shown in Figure 5-205 and described in Table 5-418.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-417 CTRLMMR_WKUP_PADCONFIG73 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C124h
Figure 5-205 CTRLMMR_WKUP_PADCONFIG73 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-418 CTRLMMR_WKUP_PADCONFIG73 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W1h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W1h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.205 CTRLMMR_WKUP_PADCONFIG74 Register ( Offset = 1C128h) [reset = 244000h]

CTRLMMR_WKUP_PADCONFIG74 is shown in Figure 5-206 and described in Table 5-420.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-419 CTRLMMR_WKUP_PADCONFIG74 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C128h
Figure 5-206 CTRLMMR_WKUP_PADCONFIG74 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-420 CTRLMMR_WKUP_PADCONFIG74 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.206 CTRLMMR_WKUP_PADCONFIG75 Register ( Offset = 1C12Ch) [reset = 10264000h]

CTRLMMR_WKUP_PADCONFIG75 is shown in Figure 5-207 and described in Table 5-422.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-421 CTRLMMR_WKUP_PADCONFIG75 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C12Ch
Figure 5-207 CTRLMMR_WKUP_PADCONFIG75 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-422 CTRLMMR_WKUP_PADCONFIG75 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W1h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W1h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.207 CTRLMMR_WKUP_PADCONFIG76 Register ( Offset = 1C130h) [reset = 10264000h]

CTRLMMR_WKUP_PADCONFIG76 is shown in Figure 5-208 and described in Table 5-424.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-423 CTRLMMR_WKUP_PADCONFIG76 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C130h
Figure 5-208 CTRLMMR_WKUP_PADCONFIG76 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-424 CTRLMMR_WKUP_PADCONFIG76 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W1h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W1h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.208 CTRLMMR_WKUP_PADCONFIG77 Register ( Offset = 1C134h) [reset = 0h]

CTRLMMR_WKUP_PADCONFIG77 is shown in Figure 5-209 and described in Table 5-426.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-425 CTRLMMR_WKUP_PADCONFIG77 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C134h
Figure 5-209 CTRLMMR_WKUP_PADCONFIG77 Register
3130292827262524
LOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDEBOUNCE_SELRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDVGPIO_SELRESERVED
R-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-426 CTRLMMR_WKUP_PADCONFIG77 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30-14RESERVEDR0h

Reserved

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for ADC0 (MCU_ADC0_CTRL_gpi_mode_en=1)

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0RESERVEDR0h

Reserved

1.1.4.209 CTRLMMR_WKUP_PADCONFIG78 Register ( Offset = 1C138h) [reset = 0h]

CTRLMMR_WKUP_PADCONFIG78 is shown in Figure 5-210 and described in Table 5-428.

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Register to control pin configuration and muxing.

Table 5-427 CTRLMMR_WKUP_PADCONFIG78 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C138h
Figure 5-210 CTRLMMR_WKUP_PADCONFIG78 Register
3130292827262524
LOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDEBOUNCE_SELRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDVGPIO_SELRESERVED
R-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-428 CTRLMMR_WKUP_PADCONFIG78 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30-14RESERVEDR0h

Reserved

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for ADC0 (MCU_ADC0_CTRL_gpi_mode_en=1)

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0RESERVEDR0h

Reserved

1.1.4.210 CTRLMMR_WKUP_PADCONFIG79 Register ( Offset = 1C13Ch) [reset = 0h]

CTRLMMR_WKUP_PADCONFIG79 is shown in Figure 5-211 and described in Table 5-430.

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Register to control pin configuration and muxing.

Table 5-429 CTRLMMR_WKUP_PADCONFIG79 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C13Ch
Figure 5-211 CTRLMMR_WKUP_PADCONFIG79 Register
3130292827262524
LOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDEBOUNCE_SELRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDVGPIO_SELRESERVED
R-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-430 CTRLMMR_WKUP_PADCONFIG79 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30-14RESERVEDR0h

Reserved

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for ADC0 (MCU_ADC0_CTRL_gpi_mode_en=1)

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0RESERVEDR0h

Reserved

1.1.4.211 CTRLMMR_WKUP_PADCONFIG80 Register ( Offset = 1C140h) [reset = 0h]

CTRLMMR_WKUP_PADCONFIG80 is shown in Figure 5-212 and described in Table 5-432.

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Register to control pin configuration and muxing.

Table 5-431 CTRLMMR_WKUP_PADCONFIG80 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C140h
Figure 5-212 CTRLMMR_WKUP_PADCONFIG80 Register
3130292827262524
LOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDEBOUNCE_SELRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDVGPIO_SELRESERVED
R-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-432 CTRLMMR_WKUP_PADCONFIG80 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30-14RESERVEDR0h

Reserved

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for ADC0 (MCU_ADC0_CTRL_gpi_mode_en=1)

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0RESERVEDR0h

Reserved

1.1.4.212 CTRLMMR_WKUP_PADCONFIG81 Register ( Offset = 1C144h) [reset = 0h]

CTRLMMR_WKUP_PADCONFIG81 is shown in Figure 5-213 and described in Table 5-434.

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Register to control pin configuration and muxing.

Table 5-433 CTRLMMR_WKUP_PADCONFIG81 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C144h
Figure 5-213 CTRLMMR_WKUP_PADCONFIG81 Register
3130292827262524
LOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDEBOUNCE_SELRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDVGPIO_SELRESERVED
R-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-434 CTRLMMR_WKUP_PADCONFIG81 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30-14RESERVEDR0h

Reserved

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for ADC0 (MCU_ADC0_CTRL_gpi_mode_en=1)

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0RESERVEDR0h

Reserved

1.1.4.213 CTRLMMR_WKUP_PADCONFIG82 Register ( Offset = 1C148h) [reset = 0h]

CTRLMMR_WKUP_PADCONFIG82 is shown in Figure 5-214 and described in Table 5-436.

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Register to control pin configuration and muxing.

Table 5-435 CTRLMMR_WKUP_PADCONFIG82 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C148h
Figure 5-214 CTRLMMR_WKUP_PADCONFIG82 Register
3130292827262524
LOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDEBOUNCE_SELRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDVGPIO_SELRESERVED
R-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-436 CTRLMMR_WKUP_PADCONFIG82 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30-14RESERVEDR0h

Reserved

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for ADC0 (MCU_ADC0_CTRL_gpi_mode_en=1)

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0RESERVEDR0h

Reserved

1.1.4.214 CTRLMMR_WKUP_PADCONFIG83 Register ( Offset = 1C14Ch) [reset = 0h]

CTRLMMR_WKUP_PADCONFIG83 is shown in Figure 5-215 and described in Table 5-438.

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Register to control pin configuration and muxing.

Table 5-437 CTRLMMR_WKUP_PADCONFIG83 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C14Ch
Figure 5-215 CTRLMMR_WKUP_PADCONFIG83 Register
3130292827262524
LOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDEBOUNCE_SELRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDVGPIO_SELRESERVED
R-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-438 CTRLMMR_WKUP_PADCONFIG83 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30-14RESERVEDR0h

Reserved

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for ADC0 (MCU_ADC0_CTRL_gpi_mode_en=1)

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0RESERVEDR0h

Reserved

1.1.4.215 CTRLMMR_WKUP_PADCONFIG84 Register ( Offset = 1C150h) [reset = 0h]

CTRLMMR_WKUP_PADCONFIG84 is shown in Figure 5-216 and described in Table 5-440.

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Register to control pin configuration and muxing.

Table 5-439 CTRLMMR_WKUP_PADCONFIG84 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C150h
Figure 5-216 CTRLMMR_WKUP_PADCONFIG84 Register
3130292827262524
LOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDEBOUNCE_SELRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDVGPIO_SELRESERVED
R-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-440 CTRLMMR_WKUP_PADCONFIG84 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30-14RESERVEDR0h

Reserved

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this pin. This allows protection between two different Processor virtual worlds. These bits have no effect if GPI mode is not selected for ADC0 (MCU_ADC0_CTRL_gpi_mode_en=1)

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0RESERVEDR0h

Reserved

1.1.4.216 CTRLMMR_WKUP_PADCONFIG93 Register ( Offset = 1C174h) [reset = 10264000h]

CTRLMMR_WKUP_PADCONFIG93 is shown in Figure 5-217 and described in Table 5-442.

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Register to control pin configuration and muxing.

Table 5-441 CTRLMMR_WKUP_PADCONFIG93 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C174h
Figure 5-217 CTRLMMR_WKUP_PADCONFIG93 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-442 CTRLMMR_WKUP_PADCONFIG93 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W1h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W1h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.217 CTRLMMR_WKUP_PADCONFIG94 Register ( Offset = 1C178h) [reset = 8014000h]

CTRLMMR_WKUP_PADCONFIG94 is shown in Figure 5-218 and described in Table 5-444.

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Register to control pin configuration and muxing.

Table 5-443 CTRLMMR_WKUP_PADCONFIG94 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C178h
Figure 5-218 CTRLMMR_WKUP_PADCONFIG94 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-444 CTRLMMR_WKUP_PADCONFIG94 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.218 CTRLMMR_WKUP_PADCONFIG95 Register ( Offset = 1C17Ch) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG95 is shown in Figure 5-219 and described in Table 5-446.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-445 CTRLMMR_WKUP_PADCONFIG95 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C17Ch
Figure 5-219 CTRLMMR_WKUP_PADCONFIG95 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-446 CTRLMMR_WKUP_PADCONFIG95 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.219 CTRLMMR_WKUP_PADCONFIG96 Register ( Offset = 1C180h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG96 is shown in Figure 5-220 and described in Table 5-448.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-447 CTRLMMR_WKUP_PADCONFIG96 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C180h
Figure 5-220 CTRLMMR_WKUP_PADCONFIG96 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-448 CTRLMMR_WKUP_PADCONFIG96 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.220 CTRLMMR_WKUP_PADCONFIG97 Register ( Offset = 1C184h) [reset = 8254007h]

CTRLMMR_WKUP_PADCONFIG97 is shown in Figure 5-221 and described in Table 5-450.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-449 CTRLMMR_WKUP_PADCONFIG97 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C184h
Figure 5-221 CTRLMMR_WKUP_PADCONFIG97 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-450 CTRLMMR_WKUP_PADCONFIG97 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.221 CTRLMMR_WKUP_PADCONFIG98 Register ( Offset = 1C188h) [reset = 10264000h]

CTRLMMR_WKUP_PADCONFIG98 is shown in Figure 5-222 and described in Table 5-452.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-451 CTRLMMR_WKUP_PADCONFIG98 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C188h
Figure 5-222 CTRLMMR_WKUP_PADCONFIG98 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-452 CTRLMMR_WKUP_PADCONFIG98 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W1h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W1h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.222 CTRLMMR_WKUP_PADCONFIG99 Register ( Offset = 1C18Ch) [reset = 10024000h]

CTRLMMR_WKUP_PADCONFIG99 is shown in Figure 5-223 and described in Table 5-454.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-453 CTRLMMR_WKUP_PADCONFIG99 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C18Ch
Figure 5-223 CTRLMMR_WKUP_PADCONFIG99 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-454 CTRLMMR_WKUP_PADCONFIG99 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W1h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W1h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.223 CTRLMMR_WKUP_PADCONFIG100 Register ( Offset = 1C190h) [reset = 8010000h]

CTRLMMR_WKUP_PADCONFIG100 is shown in Figure 5-224 and described in Table 5-456.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-455 CTRLMMR_WKUP_PADCONFIG100 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 C190h
Figure 5-224 CTRLMMR_WKUP_PADCONFIG100 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-456 CTRLMMR_WKUP_PADCONFIG100 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported on MCU_GENERAL IO domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output enable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep is active
1h - IO state is forced to OFF mode value when Deep Sleep is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W0h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debounce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual WKUP_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO_WKUP_0 instance

1h - Implement GPIO in GPIO_WKUP_1 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

Fh - Mux Mode 15

1.1.4.224 CTRLMMR_WKUP_LOCK7_KICK0 Register ( Offset = 1D008h) [reset = 0h]

CTRLMMR_WKUP_LOCK7_KICK0 is shown in Figure 5-225 and described in Table 5-458.

Return to Summary Table.

Lower 32-bits of Partition7 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_WKUP_LOCK7_KICK1 with its key value before write-protected Partition 7 registers can be written.

Table 5-457 CTRLMMR_WKUP_LOCK7_KICK0 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 D008h
Figure 5-225 CTRLMMR_WKUP_LOCK7_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-458 CTRLMMR_WKUP_LOCK7_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers

0UNLOCKEDR0h

Unlock status.
When set, indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.4.225 CTRLMMR_WKUP_LOCK7_KICK1 Register ( Offset = 1D00Ch) [reset = 0h]

CTRLMMR_WKUP_LOCK7_KICK1 is shown in Figure 5-226 and described in Table 5-460.

Return to Summary Table.

Upper 32-bits of Partition 7 write lock key. This register must be written with the designated key value after a write to CTRLMMR_WKUP_LOCK7_KICK0 with its key value before write-protected Partition 7 registers can be written.

Table 5-459 CTRLMMR_WKUP_LOCK7_KICK1 Instances
InstancePhysical Address
WKUP_CTRL_MMR0_CFG04301 D00Ch
Figure 5-226 CTRLMMR_WKUP_LOCK7_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-460 CTRLMMR_WKUP_LOCK7_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers