SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5405 lists the memory-mapped registers for the GTC0_GTC_CFG1. All register offset addresses not listed in Table 12-5405 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
GTC0_GTC_CFG1 | 00A9 0000h |
Offset | Acronym | Register Name | GTC0_GTC_CFG1 Physical Address |
---|---|---|---|
0h | GTC_CNTCR | Counter control register | 00A9 0000h |
4h | GTC_CNTSR | Counter status register | 00A9 0004h |
8h | GTC_CNTCV_LO | Counter count value (low) register | 00A9 0008h |
Ch | GTC_CNTCV_HI | Counter count value (high) register | 00A9 000Ch |
20h | GTC_CNTFID0 | Counter frequency ID0 register | 00A9 0020h |
24h | GTC_CNTFID1 | Counter frequency ID1 register | 00A9 0024h |
GTC_CNTCR is shown in Figure 12-2829 and described in Table 12-5407.
Return to Summary Table.
This register enables the system counter and controls counter operation during debug.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG1 | 00A9 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FCREQ | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FCREQ | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FCREQ | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HDBG | EN | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | FCREQ | R | 0h | Frequency change request. Indicates the number of the entry in the frequency table to select. For this device, this field is implemented as read-only, pointing to the base frequency table entry (000000h). |
7-2 | RESERVED | R | 0h | Reserved. Always read as 0. |
1 | HDBG | R/W | 0h | Halt on debug 0 = System counter ignores debug halt 1 = System counter is halted when debug halt is asserted |
0 | EN | R/W | 0h | Enable system counter 0 = System counter is disabled 1 = System counter is enabled |
GTC_CNTSR is shown in Figure 12-2830 and described in Table 12-5409.
Return to Summary Table.
This register provides system counter frequency status information.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG1 | 00A9 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FCACK | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FCACK | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FCACK | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DBGH | RESERVED | |||||
R-0h | R-X | R-0h | |||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | FCACK | R | 0h | Frequency change ackowledge. Indicates the currently selected entry in the frequency table. For this device, this field is tied to 0. |
7-2 | RESERVED | R | 0h | Reserved. Always read as 0. |
1 | DBGH | R | X | Debug halt. Indicates if the system counter is halted due to debug. 0 = System counter is not halted by a debug halt 1 = System counter is halted by a debug halt |
0 | RESERVED | R | 0h | Reserved. Always read as 0. |
GTC_CNTCV_LO is shown in Figure 12-2831 and described in Table 12-5411.
Return to Summary Table.
Indicates the current system counter count value and can be used to set the system counter count value.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG1 | 00A9 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTVALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNTVALUE | R/W | 0h | Indicates bits [31:0] of the system counter value. This field is only writable when the system counter is disabled. The read value is the current value of system counter count [31:0]. |
GTC_CNTCV_HI is shown in Figure 12-2832 and described in Table 12-5413.
Return to Summary Table.
Indicates the current system counter count value and can be used to set the system counter count value.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG1 | 00A9 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTVALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNTVALUE | R/W | 0h | Indicates bits [63:32] of the system counter value. This field is only writable when the system counter is disabled. The read value is the current value of system counter count [63:32]. |
GTC_CNTFID0 is shown in Figure 12-2833 and described in Table 12-5415.
Return to Summary Table.
Indicates base frequency of the system counter. Device bootcode/firmware should write this register with the frequency of the selected GTC clock source before enabling the system counter.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG1 | 00A9 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQVALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FREQVALUE | R/W | 0h | Indicates the base update frequency of the system counter in Hz. |
GTC_CNTFID1 is shown in Figure 12-2834 and described in Table 12-5417.
Return to Summary Table.
Indicates the system counter increment frequency.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG1 | 00A9 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQVALUE | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FREQVALUE | R | 0h | Frequency table end indicator. All 0s value marks the end of the frequency table. |