The FSS provides access to external Flash and RAM devices. It supports XIP (Execute-in-Place) and BC (Block Copy) operations.
Figure 12-1959
shows the FSS block diagram.
FSS Blocks:
- MCU_CBASS0: The MCU_CBASS0 interconnect allows FSS to communicate with the device modules and subsystems.
- Data Interface (FSS0): It is 64-bit data/32-bit address multi issue data interface with coherent in-band bypass. It provides accessibility to either the OSPI0 or HyperBus interface.
- Config Interface: It is used for configuration of the memory mapped registers within the FSS.
- Interface Clock and Reset:
- For more information, see MCU_FSS0 Clocks and Resets.
- For more information, see MCU_FSS0_OSPI Clocks
and Resets.
- For more information, see MCU_FSS0_HPB0 Clocks
and Resets.
- Memory Mapped Registers: This block conditionally
includes registers from the following blocks: FSS, ECC, MUX, and DF. The
configuration of these registers defines which FSS interface is selected and also which FSS features and operation modes are used. For
more information, see MCU_FSS0_SYSCONFIG.
- MUX: The Muxing (MUX) block is used as a software
controlled switch in the FSS interface. It defines which interface to be used (OSPI0 or
HyperBus interface). The MUX block can switch only when the traffic is idle.
The software has responsibility to cause the traffic to be stopped.
- DF: The Dynamic Fragmenter (DF) module is responsible for fragmenting write data to the flash region so that all writes to the flash region are done in 16-bits chunks (a requirement for HyperFlash). It passes all other transaction through unaffected.
- ECC: The Single
Error Correction and Double Error Detection (SECDED) mechanism is used. Each
32-byte block is protected by four SECDED bytes. For more information, see ECC
Support.
- FSS Interfaces:
- MCU_FSS0_OSPI0: Octal
Serial Peripheral Interface.
- MCU_FSS0_HPB0:
HyperBus interface.
- FSS I/O Pins:
- HyperBus I/O Pins: All used MCU_FSS0_HPB0
interface pins (for more information, see HyperBus I/O
Signals).