SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Not all channels within a DMA controller require the same performance capabilities. Raw bandwidth and latency tolerance requirements will vary greatly between data transfers at various points in the system. Several different classes of DMA channels are provided in the UDMA-P and are described in Table 10-1
Class Name | Description |
---|---|
Normal Capacity | Provides baseline amount of descriptor and TR prefetch and Tx/Rx control and data buffering. Suitable for most peripheral transfers which are communicating with on-chip memories and DDR |
High Capacity | Provides an elevated amount of descriptor and TR prefetch and custom Tx/Rx control and data buffering. Suitable for applications which require moderate per-channel bandwidth with significantly increased latency (for example Transferring data to/from PCIe) |
Ultra-high Capacity | Provides identical descriptor and TR prefetch as High Capacity but with increased Tx data buffering to allow for more read data in flight. Suitable for applications requiring high per-channel bandwidth with significantly increased latency (for example 16+ Gbps transfers to/from PCIe). |