SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 8-3304 lists the memory-mapped registers for the NAVSS_PVU_CFG. All register offset addresses not listed in Table 8-3304 should be considered as reserved locations and the register contents should not be modified.
KS3 DMA Virtual Address Translation Config Region
Instance | Base Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0000h |
NAVSS0_DMA_PVU0_CFG | 30F8 1000h |
Offset | Acronym | Register Name | NAVSS0_IO_PVU0_CFG Physical Address | NAVSS0_DMA_PVU0_CFG Physical Address |
---|---|---|---|---|
0h | PVU_PID | Revision Register | 30F8 0000h | 30F8 1000h |
4h | PVU_CONFIG | Config Register | 30F8 0004h | 30F8 1004h |
10h | PVU_ENABLE | Enable Register | 30F8 0010h | 30F8 1010h |
14h | PVU_VIRTID_MAP1 | Map Register 1 | 30F8 0014h | 30F8 1014h |
18h | PVU_VIRTID_MAP2 | Map Register 2 | 30F8 0018h | 30F8 1018h |
30h | PVU_EXCEPTION_LOGGING_DISABLE | Exception Logging Disable Register | 30F8 0030h | 30F8 1030h |
104h | PVU_DESTINATION_ID | Destination ID Register | 30F8 0104h | 30F8 1104h |
120h | PVU_EXCEPTION_LOGGING_CONTROL | Exception Logging Control Register | 30F8 0120h | 30F8 1120h |
124h | PVU_EXCEPTION_LOGGING_HEADER0 | Exception Logging Header 0 Register | 30F8 0124h | 30F8 1124h |
128h | PVU_EXCEPTION_LOGGING_HEADER1 | Exception Logging Header 1 Register | 30F8 0128h | 30F8 1128h |
12Ch | PVU_EXCEPTION_LOGGING_DATA0 | Exception Logging Data 0 Register | 30F8 012Ch | 30F8 112Ch |
130h | PVU_EXCEPTION_LOGGING_DATA1 | Exception Logging Data 1 Register | 30F8 0130h | 30F8 1130h |
134h | PVU_EXCEPTION_LOGGING_DATA2 | Exception Logging Data 2 Register | 30F8 0134h | 30F8 1134h |
138h | PVU_EXCEPTION_LOGGING_DATA3 | Exception Logging Data 3 Register | 30F8 0138h | 30F8 1138h |
140h | PVU_EXCEPTION_PEND_SET | Exception Logging Interrupt Pending Set Register | 30F8 0140h | 30F8 1140h |
144h | PVU_EXCEPTION_PEND_CLEAR | Exception Logging Interrupt Pending Clear Register | 30F8 0144h | 30F8 1144h |
148h | PVU_EXCEPTION_ENABLE_SET | Exception Logging Interrupt Enable Set Register | 30F8 0148h | 30F8 1148h |
14Ch | PVU_EXCEPTION_ENABLE_CLEAR | Exception Logging Interrupt Enable Clear Register | 30F8 014Ch | 30F8 114Ch |
150h | PVU_EOI_REG | EOI Register | 30F8 0150h | 30F8 1150h |
PVU_PID is shown in Figure 8-1643 and described in Table 8-3307.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0000h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNC | |||||||||||||
R-1h | R-2h | R-688h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-9h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | PID register scheme |
29-28 | BU | R | 2h | BU |
27-16 | FUNC | R | 688h | Module ID |
15-11 | RTL | R | 9h | RTL revision. Fh in this device. |
10-8 | MAJOR | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 0h | Minor revision |
PVU_CONFIG is shown in Figure 8-1644 and described in Table 8-3309.
Return to Summary Table.
The Config Register contains the configuration values for the module.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0004h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TLB_ENTRIES | ||||||||||||||
R-X | R-8h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLBS | |||||||||||||||
R-100h | |||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | X | |
23-16 | TLB_ENTRIES | R | 8h | Number of TLB entries per channel |
15-0 | TLBS | R | 100h | Number of TLBs 40h in this device |
PVU_ENABLE is shown in Figure 8-1645 and described in Table 8-3311.
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The Enable Register enables the PVU.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0010h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EN | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EN | R/W | 0h | PVU Enable bit. 0 = PVU disabled 1 = PVU enabled |
PVU_VIRTID_MAP1 is shown in Figure 8-1646 and described in Table 8-3313.
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The Map Register 1 defines the virtid mapping for the PVU.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0014h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DMA_CL3 | DMA_CL2 | DMA_CL1 | DMA_CL0 | ||||
R/W-3h | R/W-2h | R/W-1h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMA_CNT | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_CNT | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-22 | DMA_CL3 | R/W | 3h | Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n. |
21-20 | DMA_CL2 | R/W | 2h | Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n. |
19-18 | DMA_CL1 | R/W | 1h | Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n. |
17-16 | DMA_CL0 | R/W | 0h | Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n. |
15-12 | RESERVED | R/W | X | |
11-0 | DMA_CNT | R/W | 0h | VirtID count for DMA class that use sub-classes. |
PVU_VIRTID_MAP2 is shown in Figure 8-1647 and described in Table 8-3315.
Return to Summary Table.
The Map Register 2 defines the virtid mapping for the PVU.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0018h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAX_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | X | |
11-0 | MAX_CNT | R/W | 0h | VirtID maximum for PVU. |
PVU_EXCEPTION_LOGGING_DISABLE is shown in Figure 8-1648 and described in Table 8-3317.
Return to Summary Table.
The Exception Logging Disable Register defines which types of faults are disabled for logging.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0030h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MISS_DIS | PREF_DIS | EXEC_DIS | WRITE_DIS | READ_DIS | RESERVED | VIRTID_DIS |
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | X | |
6 | MISS_DIS | R/W | 0h | Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging. |
5 | PREF_DIS | R/W | 0h | Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging. |
4 | EXEC_DIS | R/W | 0h | Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging. |
3 | WRITE_DIS | R/W | 0h | Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging. |
2 | READ_DIS | R/W | 0h | Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging. |
1 | RESERVED | R/W | X | |
0 | VIRTID_DIS | R/W | 0h | Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging. |
PVU_DESTINATION_ID is shown in Figure 8-1649 and described in Table 8-3319.
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The Destination ID Register defines the destination ID value for error messages.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0104h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DEST_ID | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | DEST_ID | R/W | 0h | The destination ID. |
PVU_EXCEPTION_LOGGING_CONTROL is shown in Figure 8-1650 and described in Table 8-3321.
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The Exception Logging Control Register controls the exception logging.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0120h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DISABLE_INTR | DISABLE_F | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | DISABLE_INTR | R/W | 0h | Disables logging interrupt when set. This will not disable logging, so if cleared the current log should also be cleared to guarantee the next log generates the interrupt. |
0 | DISABLE_F | R/W | 0h | Disables logging when set. This will also disable interrupts. |
PVU_EXCEPTION_LOGGING_HEADER0 is shown in Figure 8-1651 and described in Table 8-3323.
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The Exception Logging Header 0 Register contains the first word of the header.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0124h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1124h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TYPE_F | SRC_ID | DEST_ID | |||||||||||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | TYPE_F | R | 0h | Type. 6 = PVU. |
23-8 | SRC_ID | R | 0h | Source ID. |
7-0 | DEST_ID | R | 0h | Destination ID. |
PVU_EXCEPTION_LOGGING_HEADER1 is shown in Figure 8-1652 and described in Table 8-3325.
Return to Summary Table.
The Exception Logging Header 1 Register contains the second word of the header.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0128h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1128h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GROUP | CODE | RESERVED | |||||||||||||||||||||||||||||
R-0h | R-0h | R-X | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | GROUP | R | 0h | Group. |
23-16 | CODE | R | 0h | Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation. |
15-0 | RESERVED | R | X |
PVU_EXCEPTION_LOGGING_DATA0 is shown in Figure 8-1653 and described in Table 8-3327.
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The Exception Logging Data 0 Register contains the first word of the data.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 012Ch |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 112Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_L | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR_L | R | 0h | Input virtual address lower 32 bits. |
PVU_EXCEPTION_LOGGING_DATA1 is shown in Figure 8-1654 and described in Table 8-3329.
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The Exception Logging Data 1 Register contains the second word of the data.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0130h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1130h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR_H | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | ADDR_H | R | 0h | Input virtual address upper 12 bits. |
PVU_EXCEPTION_LOGGING_DATA2 is shown in Figure 8-1655 and described in Table 8-3331.
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The Exception Logging Data 2 Register contains the third word of the data.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0134h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1134h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ROUTEID | ||||||
R-X | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ROUTEID | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WRITE | READ | DEBUG | CACHEABLE | PRIV | SECURE | |
R-X | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRIV_ID | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | X | |
27-16 | ROUTEID | R | 0h | Route ID. |
15-14 | RESERVED | R | X | |
13 | WRITE | R | 0h | Write. |
12 | READ | R | 0h | Read. |
11 | DEBUG | R | 0h | Debug. |
10 | CACHEABLE | R | 0h | Cacheable. |
9 | PRIV | R | 0h | Priv. |
8 | SECURE | R | 0h | Secure. |
7-0 | PRIV_ID | R | 0h | Priv ID. |
PVU_EXCEPTION_LOGGING_DATA3 is shown in Figure 8-1656 and described in Table 8-3333.
Return to Summary Table.
The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0138h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1138h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BYTECNT | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | X | |
9-0 | BYTECNT | R | 0h | Byte count. |
PVU_EXCEPTION_PEND_SET is shown in Figure 8-1657 and described in Table 8-3335.
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The Exception Logging Interrupt Pending Set Register allows to set the pend signal.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0140h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PEND_SET | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | PEND_SET | R/W1S | 0h | Write a 1 to set the exception pend signal. |
PVU_EXCEPTION_PEND_CLEAR is shown in Figure 8-1658 and described in Table 8-3337.
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The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0144h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1144h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PEND_CLR | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | PEND_CLR | R/W1C | 0h | Write a 1 to clear the exception pend signal. |
PVU_EXCEPTION_ENABLE_SET is shown in Figure 8-1659 and described in Table 8-3339.
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The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0148h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1148h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_SET | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | ENABLE_SET | R/W1S | 0h | Write a 1 to set the exception interrupt enable signal. |
PVU_EXCEPTION_ENABLE_CLEAR is shown in Figure 8-1660 and described in Table 8-3341.
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The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 014Ch |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 114Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_CLR | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | ENABLE_CLR | R/W1C | 0h | Write a 1 to clear the exception interrupt enable signal. |
PVU_EOI_REG is shown in Figure 8-1661 and described in Table 8-3343.
Return to Summary Table.
EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG | 30F8 0150h |
NAVSS0_DMA_IO_PVU0_CFG | 30F8 1150h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||||||||||||||||||||||||||
R-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | EOI_WR | R/W | 0h | EOI Register |