SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-11 lists the memory-mapped registers for the ADC. All register offset addresses not listed in Table 12-11 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_ADC0 | 4020 0000h |
Offset | Acronym | Register Name | MCU_ADC0 Physical Address |
---|---|---|---|
0h | ADC_REVISION | Revision Identifier Register | 4020 0000h |
20h | ADC_EOI | End of Interrupt Register | 4020 0020h |
24h | ADC_STATUS_RAW | Raw Interrupt Status Register | 4020 0024h |
28h | ADC_STATUS | Interrupt Status Register | 4020 0028h |
2Ch | ADC_ENABLE_SET | Interrupt Enable Register | 4020 002Ch |
30h | ADC_ENABLE_CLR | Interrupt Disable Register | 4020 0030h |
38h | ADC_DMAENABLE_SET | DMA Request Enable Register | 4020 0038h |
3Ch | ADC_DMAENABLE_CLR | DMA Request Disable Register | 4020 003Ch |
40h | ADC_CONTROL | Control Register | 4020 0040h |
44h | ADC_SEQUENCER_STAT | Sequencer Status Register | 4020 0044h |
48h | ADC_RANGE | Range Check Register | 4020 0048h |
50h | ADC_MISC | AFE Input/Output Control Register | 4020 0050h |
54h | ADC_STEPENABLE | Sequencer Step Enable Register | 4020 0054h |
64h + formula | ADC_STEPCONFIG_j | Step Configuration Register | 4020 0000h |
68h + formula | ADC_STEPDELAY_j | Step Delay Register | 4020 0000h |
E4h | ADC_FIFO0WC | FIFO0 Word Count Register | 4020 00E4h |
E8h | ADC_FIFO0THRESHOLD | FIFO0 Threshold Level Register | 4020 00E8h |
ECh | ADC_FIFO0DMAREQ | FIFO0 DMA Request Level Register | 4020 00ECh |
F0h | ADC_FIFO1WC | FIFO1 Word Count Register | 4020 00F0h |
F4h | ADC_FIFO1THRESHOLD | FIFO1 Threshold Level Register | 4020 00F4h |
F8h | ADC_FIFO1DMAREQ | FIFO1 DMA Request Level Register | 4020 00F8h |
100h | ADC_FIFO0DATA | FIFO0 Read Data Register | 4020 0100h |
200h | ADC_FIFO1DATA | FIFO1 Read Data Register | 4020 0200h |
ADC_REVISION is shown in Figure 12-7 and described in Table 12-13.
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IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R-69C0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-7h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 69C0h | Module ID field |
15-11 | REVRTL | R | 7h | RTL ADC_REVISION. Will vary depending on release. |
10-8 | REVMAJ | R | 1h | Major ADC_REVISION |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | REVMIN | R | 0h | Minor ADC_REVISION |
ADC_EOI is shown in Figure 12-8 and described in Table 12-15.
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The End of Interrupt (ADC_EOI) ADC_MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the ADC_EOI for ADC_MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt sources remain. This register will be reset one cycle after it has been written to.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINENUMEOI | ||||||
R-0h | W-0h | ||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | LINENUMEOI | W | 0h | Software End Of Interrupt (EOI) control. |
ADC_STATUS_RAW is shown in Figure 12-9 and described in Table 12-17.
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The ADC_STATUS_RAW register allows the MCU_ADC0 interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OUTOFRANGE | ||||||
R-0h | R/W1S-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFO1UNFL | FIFO1OVFL | FIFO1THRS | FIFO0UNFL | FIFO0OVFL | FIFO0THRS | ENDOFEQUENCE | AFE_EOC_MISSING |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | OUTOFRANGE | R/W1S | 0h | Status raw for out of range interrupt. |
7 | FIFO1UNFL | R/W1S | 0h | Status raw for FIFO1 under-flow interrupt. |
6 | FIFO1OVFL | R/W1S | 0h | Status raw for FIFO1 over-flow interrupt. |
5 | FIFO1THRS | R/W1S | 0h | Status raw for FIFO1 threshold interrupt. |
4 | FIFO0UNFL | R/W1S | 0h | Status raw for FIFO0 under-flow interrupt. |
3 | FIFO0OVFL | R/W1S | 0h | Status raw for FIFO0 over-flow interrupt. |
2 | FIFO0THRS | R/W1S | 0h | Status raw for FIFO0 threshold interrupt. |
1 | ENDOFEQUENCE | R/W1S | 0h | Status raw for end of sequence interrupt. |
0 | AFE_EOC_MISSING | R/W1S | 0h | Status raw for missing AFE EOC interrupt. |
ADC_STATUS is shown in Figure 12-10 and described in Table 12-19.
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The ADC_STATUS register allows the MCU_ADC0 interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OUTOFRANGE | ||||||
R-0h | R/W1C-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFO1UNFL | FIFO1OVFL | FIFO1THRS | FIFO0UNFL | FIFO0OVFL | FIFO0THRS | ENDOFEQUENCE | AFE_EOC_MISSING |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | OUTOFRANGE | R/W1C | 0h | Enabled status for out of range interrupt. |
7 | FIFO1UNFL | R/W1C | 0h | Enabled status for FIFO1 under-flow interrupt. |
6 | FIFO1OVFL | R/W1C | 0h | Enabled status for FIFO1 over-flow interrupt. |
5 | FIFO1THRS | R/W1C | 0h | Enabled status for FIFO1 threshold interrupt. |
4 | FIFO0UNFL | R/W1C | 0h | Enabled status for FIFO0 under-flow interrupt. |
3 | FIFO0OVFL | R/W1C | 0h | Enabled status for FIFO0 over-flow interrupt. |
2 | FIFO0THRS | R/W1C | 0h | Enabled status for FIFO0 threshold interrupt. |
1 | ENDOFEQUENCE | R/W1C | 0h | Enabled status for end of sequence interrupt. |
0 | AFE_EOC_MISSING | R/W1C | 0h | Enable status for missing AFE EOC interrupt. |
ADC_ENABLE_SET is shown in Figure 12-11 and described in Table 12-21.
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The ADC_ENABLE_SET register allows the MCU_ADC0 interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OUTOFRANGE | ||||||
R-0h | R/W1S-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFO1UNFL | FIFO1OVFL | FIFO1THRS | FIFO0UNFL | FIFO0OVFL | FIFO0THRS | ENDOFEQUENCE | AFE_EOC_MISSING |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | OUTOFRANGE | R/W1S | 0h | Out of range interrupt enable. |
7 | FIFO1UNFL | R/W1S | 0h | FIFO1 under-flow interrupt enable. |
6 | FIFO1OVFL | R/W1S | 0h | FIFO1 over-flow interrupt enable. |
5 | FIFO1THRS | R/W1S | 0h | FIFO1 threshold interrupt enable. |
4 | FIFO0UNFL | R/W1S | 0h | FIFO0 under-flow interrupt enable. |
3 | FIFO0OVFL | R/W1S | 0h | FIFO0 over-flow interrupt enable. |
2 | FIFO0THRS | R/W1S | 0h | FIFO0 threshold interrupt enable. |
1 | ENDOFEQUENCE | R/W1S | 0h | End of sequence interrupt enable. |
0 | AFE_EOC_MISSING | R/W1S | 0h | Missing AFE EOC interrupt enable. |
ADC_ENABLE_CLR is shown in Figure 12-12 and described in Table 12-23.
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The ADC_ENABLE_CLR register allows the MCU_ADC0 interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OUTOFRANGE | ||||||
R-0h | R/W1C-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFO1UNFL | FIFO1OVFL | FIFO1THRS | FIFO0UNFL | FIFO0OVFL | FIFO0THRS | ENDOFEQUENCE | AFE_EOC_MISSING |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | OUTOFRANGE | R/W1C | 0h | Out of range interrupt disable. |
7 | FIFO1UNFL | R/W1C | 0h | FIFO1 under-flow interrupt disable. |
6 | FIFO1OVFL | R/W1C | 0h | FIFO1 over-flow interrupt disable. |
5 | FIFO1THRS | R/W1C | 0h | FIFO1 threshold interrupt disable. |
4 | FIFO0UNFL | R/W1C | 0h | FIFO0 under-flow interrupt disable. |
3 | FIFO0OVFL | R/W1C | 0h | FIFO0 over-flow interrupt disable. |
2 | FIFO0THRS | R/W1C | 0h | FIFO0 threshold interrupt disable. |
1 | ENDOFEQUENCE | R/W1C | 0h | End of sequence interrupt disable. |
0 | AFE_EOC_MISSING | R/W1C | 0h | Missing AFE EOC interrupt disable. |
ADC_DMAENABLE_SET is shown in Figure 12-13 and described in Table 12-25.
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The ADC_DMAENABLE_SET register allows the enabling of DMA requests.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE1 | ENABLE0 | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30-2 | RESERVED | R | 0h | Reserved |
1 | ENABLE1 | R/W1S | 0h | Enable DMA event to FIFO1 |
0 | ENABLE0 | R/W1S | 0h | Enable DMA event to FIFO0 |
ADC_DMAENABLE_CLR is shown in Figure 12-14 and described in Table 12-27.
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The ADC_DMAENABLE_CLR register allows the disabling of DMA requests.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE1 | ENABLE0 | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30-2 | RESERVED | R | 0h | Reserved |
1 | ENABLE1 | R/W1C | 0h | Clears the enable of the DMA event to FIFO1. Disable DMA event to FIFO1 Write 0h = No action Write 1h = Disable DMA event Read 0h = DMA event disabled Read 1h = DMA event enabled |
0 | ENABLE0 | R/W1C | 0h | Clears the enable of the DMA event to FIFO0. Disable DMA event to FIFO0 Write 0h = No action Write 1h = Disable DMA event Read 0h = DMA event disabled Read 1h = DMA event enabled |
ADC_CONTROL is shown in Figure 12-15 and described in Table 12-29.
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Controls various parameters of the cotroller state.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HI_MID_SEL | HI_MID_EN | HW_PREEMPT | HW_MAP | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PD | RESERVED | STEP_ID_EN | MODULE_ENABLE | |||
R-0h | R/W-1h | R-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | HI_MID_SEL | R/W | 0h | Reference select for functional internal diagnostic debug mode. 0h = VMID 1h = REFP |
10 | HI_MID_EN | R/W | 0h | Functional internal diagnostic debug mode. 0h = disabled 1h = enabled |
9 | HW_PREEMPT | R/W | 0h | 0h = SW steps are not preempted by HW events 1h = SW steps are preempted by HW events |
8 | HW_MAP | R/W | 0h | 0h = HW events are disabled 1h = HW events are enabled |
7-5 | RESERVED | R | 0h | Reserved |
4 | PD | R/W | 1h | ADC Power Down control. 0h = AFE is powered up 1h = AFE is powered down (default) At default, AFE is powered down; Software must write 0 to turn on the power and wait 4 us before starting a conversion |
3 | BIAS_SEL | R/W | 0h | AFE select bias ADC control register |
2 | RESERVED | R | 0h | Reserved |
1 | STEP_ID_EN | R/W | 0h | Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO. 0h = Write zeros 1h = Store the input (channel) ID tag |
0 | MODULE_ENABLE | R/W | 0h | ADC module enable bit. After programming all the configuration and step enable registers, write a 1 to this bit to start conversion. Writing a 0 will disable the module after the current conversion. Before turning on again, the ADC_SEQUENCER_STAT register show read back STEP_IDLE = 10h and FSM_BUSY = 0h. Enabling the controller will be held off until MEM_INIT_DONE = 1h. |
ADC_SEQUENCER_STAT is shown in Figure 12-16 and described in Table 12-31.
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SW can read this register to find out the currently scheduled step id being converted on the ADC port. If you want to turn the controller off and then back on, the step_id bit should be checked and compared to IDLE before enabling the ADC module again. Also, before enabling the controller again, the user should wait for the FSM bit 5 to read idl.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MEM_INIT_DONE | FSM_BUSY | STEP_IDLE | ||||
R-0h | R-0h | R-1h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | GPADC_BUSY | R | 0h | Monitor the AFE internal calibration (busy bit) |
7 | RESERVED | R | 0h | Reserved |
6 | MEM_INIT_DONE | R | 0h | ADC_STATUS of RAM initialization for ECC. 1h = RAM initialization to 0 after reset is done. |
5 | FSM_BUSY | R | 1h | ADC_STATUS of FSM. 0h = Idle 1h = Conversion in progress |
4-0 | STEP_IDLE | R | 0h | 10h = Idle 0h - Fh = Corresponds to Step 1 - Step 16 |
ADC_RANGE is shown in Figure 12-17 and described in Table 12-33.
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This feature requires the ADC_RANGE check interrupt bit to be enabled first. The user can decide which input (channel) is compared by programming the RangeCheck bit of the ADC_STEPCONFIG_j Registers. It is up to software to sort through FIFO data to determine which input (channel) data was out of ADC_RANGE.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | HIRANGE | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOWRANGE | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-16 | HIRANGE | R/W | 0h | Sampled ADC data is compared to this value. If the sampled data is > HIRANGE, then interrupt is generated. |
15-12 | RESERVED | R | 0h | Reserved |
11-0 | LOWRANGE | R/W | 0h | Sampled ADC data is compared to this value. If the sampled data is < LOWRANGE, then interrupt is generated. |
ADC_MISC is shown in Figure 12-18 and described in Table 12-35.
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Spare inputs of the AFE are driven by this register, spare outputs from the AFE are read.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | AFE_SPARE_OUT | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AFE_SPARE_IN | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-8 | AFE_SPARE_OUT | R | 0h | Connected to AFE Spare Output pins, reserved in normal operation. |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | AFE_SPARE_IN | R/W | 0h | Connected to AFE Spare Input pins, reserved in normal operation. |
ADC_STEPENABLE is shown in Figure 12-19 and described in Table 12-37.
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Contains the enable bit for each step in the sequencer. When all steps are disabled, the FSM will stay in IDLE state.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | STEP16 | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
STEP15 | STEP14 | STEP13 | STEP12 | STEP11 | STEP10 | STEP9 | STEP8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STEP7 | STEP6 | STEP5 | STEP4 | STEP3 | STEP2 | STEP1 | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved |
16 | STEP16 | R/W | 0h | Enable step 16 |
15 | STEP15 | R/W | 0h | Enable step 15 |
14 | STEP14 | R/W | 0h | Enable step 14 |
13 | STEP13 | R/W | 0h | Enable step 13 |
12 | STEP12 | R/W | 0h | Enable step 12 |
11 | STEP11 | R/W | 0h | Enable step 11 |
10 | STEP10 | R/W | 0h | Enable step 10 |
9 | STEP9 | R/W | 0h | Enable step 9 |
8 | STEP8 | R/W | 0h | Enable step 8 |
7 | STEP7 | R/W | 0h | Enable step 7 |
6 | STEP6 | R/W | 0h | Enable step 6 |
5 | STEP5 | R/W | 0h | Enable step 5 |
4 | STEP4 | R/W | 0h | Enable step 4 |
3 | STEP3 | R/W | 0h | Enable step 3 |
2 | STEP2 | R/W | 0h | Enable step 2 |
1 | STEP1 | R/W | 0h | Enable step 1 |
0 | RESERVED | R | 0h | Reserved |
ADC_STEPCONFIG_j is shown in Figure 12-20 and described in Table 12-39.
Return to Summary Table.
The user should write the appropriate value to this register that is required to configure the various functions of each step.
Offset = 64h + (j * 8h); where j = 0h to Fh
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RANGECHECK | FIFOSEL | DIFF_CNTRL | RESERVED | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SEL_INP_SWC | SEL_INM_SWM | |||||
R-0h | R/W-0h | R/W-8h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEL_INM_SWM | RESERVED | ||||||
R/W-8h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AVERAGING | MODE | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27 | RANGECHECK | R/W | 0h | 0h = Disable ADC_RANGE check 1h = compare ADC data with ADC_RANGE |
26 | FIFOSEL | R/W | 0h | Sampled data will be stored in FIFO. 0h = FIFO0 1h = FIFO1 |
25 | DIFF_CNTRL | R/W | 0h | Differential ADC_CONTROL. 0h = Single ended input, SEL_INM_SWM must be 8h 1h = Differential input |
24-23 | RESERVED | R | 0h | Reserved |
22-19 | SEL_INP_SWC | R/W | 0h | Select source for positive ADC input (INP). 0h = Input (channel) 0 1h = Input (channel) 1 2h = Input (channel) 2 3h = Input (channel) 3 4h = Input (channel) 4 5h = Input (channel) 5 6h = Input (channel) 6 7h = Input (channel) 7 8h = REFN |
18-15 | SEL_INM_SWM | R/W | 8h | Select source for negative ADC input (INM). 0h = Input (channel) 0 1h = Input (channel) 1 2h = Input (channel) 2 3h = Input (channel) 3 4h = Input (channel) 4 5h = Input (channel) 5 6h = Input (channel) 6 7h = Input (channel) 7 8h = REFN |
14-5 | RESERVED | R | 0h | Reserved |
4-2 | AVERAGING | R/W | 0h | Number of samplings to average. 0h = no average 1h = 2 samples average 2h = 4 samples average 3h = 8 samples average 4h = 16 samples average |
1-0 | MODE | R/W | 0h | 0h = SW enabled, one-shot 1h = SW enabled, continuous 2h = HW synchronized, one-shot 3h = HW synchronized, continuous |
ADC_STEPDELAY_j is shown in Figure 12-21 and described in Table 12-41.
Return to Summary Table.
Controls number of SMPL_CLK periods to sample and delay.
Offset = 68h + (j × 8h); where j = 0h to Fh
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SAMPLEDELAY | RESERVED | OPENDELAY | |||||||||||||
R/W-0h | R-0h | R/W-0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OPENDELAY | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | SAMPLEDELAY | R/W | 0h | This register will control the number of SMPL_CLK cycles to sample the input signal (hold SOC high). Any value programmed here will be added to the minimum time of 2 SMPL_CLK cycles. |
23-18 | RESERVED | R | 0h | Reserved |
17-0 | OPENDELAY | R/W | 0h | Program the number of SMPL_CLK cycles to wait after applying the step configuration registers and before sending the start of ADC conversion. |
ADC_FIFO0WC is shown in Figure 12-22 and described in Table 12-43.
Return to Summary Table.
FIFO word count ADC_STATUS
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 00E4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUMWDS | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8-0 | NUMWDS | R | 0h | Number of words currently in the FIFO0. |
ADC_FIFO0THRESHOLD is shown in Figure 12-23 and described in Table 12-45.
Return to Summary Table.
FIFO threshold
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 00E8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRESHOLD | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | THRESHOLD | R/W | 0h | Program the desired FIFO0 data sample level minus 1 to reach before generating interrupt to CPU. |
ADC_FIFO0DMAREQ is shown in Figure 12-24 and described in Table 12-47.
Return to Summary Table.
DMA request.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 00ECh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAREQLEVEL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DMAREQLEVEL | R/W | 0h | Number of words in FIFO0 before generating a DMA request. |
ADC_FIFO1WC is shown in Figure 12-25 and described in Table 12-49.
Return to Summary Table.
FIFO word count ADC_STATUS
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 00F0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUMWDS | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8-0 | NUMWDS | R | 0h | Number of words currently in the FIFO1. |
ADC_FIFO1THRESHOLD is shown in Figure 12-26 and described in Table 12-51.
Return to Summary Table.
FIFO threshold
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 00F4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRESHOLD | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | THRESHOLD | R/W | 0h | Program the desired FIFO1 data sample level minus 1 to reach before generating interrupt to CPU. |
ADC_FIFO1DMAREQ is shown in Figure 12-27 and described in Table 12-53.
Return to Summary Table.
DMA request.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 00F8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAREQLEVEL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DMAREQLEVEL | R/W | 0h | Number of words in FIFO1 before generating a DMA request. |
ADC_FIFO0DATA is shown in Figure 12-28 and described in Table 12-55.
Return to Summary Table.
A read from this register will auto increment the FIFO read pointer. If you read when FIFO is empty, it will trigger an underflow interrupt.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ADCCHANLID | ||||||||||||||
R-0h | R-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADCDATA | ||||||||||||||
R-X | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | ADCCHANLID | R | 0h | Optional ID tag of input (channel) that captured the data. If tag option is disabled, these bits will be 0. |
15-12 | RESERVED | R | X | Reserved |
11-0 | ADCDATA | R | 0h | Sampled ADC converted data value stored in FIFO0. |
ADC_FIFO1DATA is shown in Figure 12-29 and described in Table 12-57.
Return to Summary Table.
A read from this register will auto increment the FIFO read pointer. If you read when FIFO is empty, it will trigger an underflow interrupt.
Instance | Physical Address |
---|---|
MCU_ADC0 | 4020 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ADCCHANLID | ||||||||||||||
R-0h | R-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADCDATA | ||||||||||||||
R-X | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | ADCCHANLID | R | 0h | Optional ID tag of input (channel) that captured the data. If tag option is disabled, these bits will be 0. |
15-12 | RESERVED | R | X | Reserved |
11-0 | ADCDATA | R | 0h | Sampled ADC converted data value stored in FIFO1. |
Table 12-59 lists the memory-mapped registers for the MCU_ADC0_FIFO0/1. All register offset addresses not listed in Table 12-59 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_ADC0_FIFO | 4020 8000h |
Offset | Acronym | Register Name | MCU_ADC0_FIFO Physical Address |
---|---|---|---|
100h | ADC_FIFO0DMADATA | MCU_ADC0_FIFO0 Memory Register | 4020 8100h |
200h | ADC_FIFO1DMADATA | MCU_ADC0_FIFO1 Memory Register | 4020 8200h |
ADC_FIFO0DMADATA is shown in Figure 12-30 and described in Table 12-61.
Return to Summary Table.
DMA sample FIFO
Instance | Physical Address |
---|---|
MCU_ADC0_FIFO | 4020 8100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ADCCHANLID | ||||||||||||||
R-0h | R-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADCDATA | ||||||||||||||
R-0h | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | ADCCHANLID | R | 0h | Optional ID tag of input (channel) that captured the data. If tag option is disabled, these bits will be 0. |
15-12 | RESERVED | R | 0h | Reserved |
11-0 | ADCDATA | R | 0h | Sampled ADC converted data value stored in FIFO0. |
ADC_FIFO1DMADATA is shown in Figure 12-31 and described in Table 12-63.
Return to Summary Table.
DMA sample FIFO
Instance | Physical Address |
---|---|
MCU_ADC0_FIFO | 4020 8200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ADCCHANLID | ||||||||||||||
R-0h | R-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADCDATA | ||||||||||||||
R-0h | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | ADCCHANLID | R | 0h | Optional ID tag of input (channel) that captured the data. If tag option is disabled, these bits will be 0. |
15-12 | RESERVED | R | 0h | Reserved |
11-0 | ADCDATA | R | 0h | Sampled ADC converted data value stored in FIFO1. |
Table 12-65 lists the memory-mapped registers for the ADC ECC. All register offset addresses not listed in Table 12-65 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_ADC0_ECC | 4070 7000h |
Offset | Acronym | Register Name | MCU_ADC0_ECC Physical Address |
---|---|---|---|
0h | ADC_AGGR_REVISION | Aggregator Revision Register | 4070 7000h |
8h | ADC_ECC_VECTOR | ECC Vector Register | 4070 7008h |
Ch | ADC_MISC_STATUS | Misc Status Register | 4070 700Ch |
3Ch | ADC_ECC_SEC_EOI_REG | SEC End of Interrupt Register | 4070 703Ch |
40h | ADC_ECC_SEC_STATUS_REG0 | Interrupt Status Register | 4070 7040h |
80h | ADC_ECC_SEC_ENABLE_SET_REG0 | Interrupt Enable Set Register | 4070 7080h |
C0h | ADC_ECC_SEC_ENABLE_CLR_REG0 | Interrupt Enable Clear Register | 4070 70C0h |
13Ch | ADC_ECC_DED_EOI_REG | DED End of Interrupt Register | 4070 713Ch |
140h | ADC_ECC_DED_STATUS_REG0 | Interrupt Status Register | 4070 7140h |
180h | ADC_ECC_DED_ENABLE_SET_REG0 | Interrupt Enable Set Register | 4070 7180h |
1C0h | ADC_ECC_DED_ENABLE_CLR_REG0 | Interrupt Enable Clear Register | 4070 71C0h |
200h | ADC_AGGR_ENABLE_SET | AGGR interrupt enable set Register | 4070 7200h |
204h | ADC_AGGR_ENABLE_CLR | AGGR interrupt enable clear Register | 4070 7204h |
208h | ADC_AGGR_STATUS_SET | AGGR interrupt status set Register | 4070 7208h |
20Ch | ADC_AGGR_STATUS_CLR | AGGR interrupt status clear Register | 4070 720Ch |
ADC_AGGR_REVISION is shown in Figure 12-32 and described in Table 12-67.
Return to Summary Table.
Revision parameters
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 0h | Minor version |
ADC_ECC_VECTOR is shown in Figure 12-33 and described in Table 12-69.
Return to Summary Table.
ECC Vector Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1h = Trigger a read on the serial VBUS |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for ADC_CONTROL or ADC_STATUS |
ADC_MISC_STATUS is shown in Figure 12-34 and described in Table 12-71.
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Misc Status
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 700Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-2h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 2h | Indicates the number of RAMS serviced by the ECC aggregator |
ADC_ECC_WRAP_REV is shown in Figure 12-35 and described in Table 12-73.
Return to Summary Table.
Revision parameters
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6h | Module ID |
15-11 | REVRTL | R | 1h | RTL version |
10-8 | REVMAJ | R | 1h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 0h | Minor version |
ADC_ECC_CTRL is shown in Figure 12-36 and described in Table 12-75.
Return to Summary Table.
ECC Control Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERROR_ONCE | FORCE_N_ROW | FORCE_DED | FORCE_SEC | ENABLE_RMW | ECC_CHECK | ECC_ENABLE |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-1h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6 | ERROR_ONCE | R/W | 0h | Force Error only once |
5 | FORCE_N_ROW | R/W | 0h | Force Error on any RAM read |
4 | FORCE_DED | R/W | 0h | Force Double Bit Error |
3 | FORCE_SEC | R/W | 0h | Force Single Bit Error |
2 | ENABLE_RMW | R/W | 1h | Enable rmw |
1 | ECC_CHECK | R/W | 1h | Enable ECC check |
0 | ECC_ENABLE | R/W | 1h | Enable ECC |
ADC_ECC_ERR_CTRL1 is shown in Figure 12-37 and described in Table 12-77.
Return to Summary Table.
ECC Error Control1 Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_ROW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ECC_ROW | R/W | 0h | Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set |
ADC_ECC_ERR_CTRL2 is shown in Figure 12-38 and described in Table 12-79.
Return to Summary Table.
ECC Error Control2 Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 701Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_BIT2 | ECC_BIT1 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ECC_BIT2 | R/W | 0h | Data bit that needs to be flipped if double bit error needs to be forced |
15-0 | ECC_BIT1 | R/W | 0h | Data bit that needs to be flipped when force_sec is set |
ADC_ECC_ERR_STAT1 is shown in Figure 12-39 and described in Table 12-81.
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ECC Error Status1 Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ECC_BIT1 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ECC_BIT1 | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLR_ECC_OTHER | CLR_ECC_DED | CLR_ECC_SEC | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECC_OTHER | ECC_DED | ECC_SEC | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ECC_BIT1 | R | 0h | Data bit that corresponds to the single-bit error |
15-11 | RESERVED | R | 0h | Reserved |
10 | CLR_ECC_OTHER | R/W | 0h | Clear other Error Status |
9 | CLR_ECC_DED | R/W | 0h | Clear Double Bit Error Status |
8 | CLR_ECC_SEC | R/W | 0h | Clear Single Bit Error Status |
7-3 | RESERVED | R | 0h | Reserved |
2 | ECC_OTHER | R/W | 0h | Successive single-bit errors have occurred while a writeback is still pending, Level interrupt |
1 | ECC_DED | R/W | 0h | Level Double Bit Error Status |
0 | ECC_SEC | R/W | 0h | Level Single Bit Error Status |
ADC_ECC_ERR_STAT2 is shown in Figure 12-40 and described in Table 12-83.
Return to Summary Table.
ECC Error Status1 Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_ROW | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ECC_ROW | R | 0h | Row address where the single or double-bit error has occurred |
ADC_ECC_SEC_EOI_REG is shown in Figure 12-41 and described in Table 12-85.
Return to Summary Table.
ADC_EOI Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 703Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | ADC_EOI Register |
ADC_ECC_SEC_STATUS_REG0 is shown in Figure 12-42 and described in Table 12-87.
Return to Summary Table.
Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAM1_PEND | RAM0_PEND | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RAM1_PEND | R/W1S | 0h | Interrupt Pending Status for ram1_pend |
0 | RAM0_PEND | R/W1S | 0h | Interrupt Pending Status for ram0_pend |
ADC_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-43 and described in Table 12-89.
Return to Summary Table.
Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAM1_ENABLE_SET | RAM0_ENABLE_SET | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RAM1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ram1_pend |
0 | RAM0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ram0_pend |
ADC_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-44 and described in Table 12-91.
Return to Summary Table.
Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 70C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAM1_ENABLE_CLR | RAM0_ENABLE_CLR | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ram1_pend |
0 | RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ram0_pend |
ADC_ECC_DED_EOI_REG is shown in Figure 12-45 and described in Table 12-93.
Return to Summary Table.
ADC_EOI Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 713Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | ADC_EOI Register |
ADC_ECC_DED_STATUS_REG0 is shown in Figure 12-46 and described in Table 12-95.
Return to Summary Table.
Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAM1_PEND | RAM0_PEND | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RAM1_PEND | R/W1S | 0h | Interrupt Pending Status for ram1_pend |
0 | RAM0_PEND | R/W1S | 0h | Interrupt Pending Status for ram0_pend |
ADC_ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-47 and described in Table 12-97.
Return to Summary Table.
Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAM1_ENABLE_SET | RAM0_ENABLE_SET | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RAM1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ram1_pend |
0 | RAM0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ram0_pend |
ADC_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-48 and described in Table 12-99.
Return to Summary Table.
Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 71C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAM1_ENABLE_CLR | RAM0_ENABLE_CLR | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ram1_pend |
0 | RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ram0_pend |
aggr_enable_set is shown in Figure 12-49 and described in Table 12-101.
Return to the Summary Table.
AGGR interrupt enable set Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
aggr_enable_clr is shown in Figure 12-50 and described in Table 12-103.
Return to the Summary Table.
AGGR interrupt enable clear Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
aggr_status_set is shown in Figure 12-51 and described in Table 12-105.
Return to the Summary Table.
AGGR interrupt status set Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 7208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | interrupt status set for parity errors |
aggr_status_clr is shown in Figure 12-52 and described in Table 12-107.
Return to the Summary Table.
AGGR interrupt status clear Register
Instance | Physical Address |
---|---|
MCU_ADC0_ECC | 4070 720Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | interrupt status clear for parity errors |