SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
DCC has provision to read the counts during operation. This is performed using DCC_CNT0, DCC_VALID0, and DCC_CNT1 registers. Read from these registers in default mode allows reading the present value of count. This is useful when in single shot mode or mode where DCC stops upon error.
These registers can be used to read the FIFO through the DCC_GCTRL2[7-4] FIFO_READ configuration. Reads on the empty FIFO shall provide the contents of last pointed location. Application shall track the empty/full conditions of the FIFOs to track the count records consistently.
Regardless of FIFO_READ configuration, the FIFO internally keeps updating records based on configured triggers till full.