SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
MCU_OBSCLK0 output is controlled by CTRLMMR_WKUP_MCU_OBSCLK_CTRL register in the WKUP_CTRL_MMR0 module; for more information about control registers, see Section 5.1, Control Module (CTRL_MMR). Two muxes are connected in series - MCU_OBSCLK0_MUX0 and MCU_OBSCLK0_MUX1, see Figure 5-753.
How to select the output of MCU_OBSCLK0_MUX1 is described in Table 5-1569.
CTRLMMR_WKUP_MCU_OBSCLK_CTRL(2)[3-0] CLK_SEL | MCU_OBSCLK0_MUX1 Output Clock Selection(1) |
---|---|
0x0 | CLK_12M_RC |
0x1 | 0 (GND)(3) |
0x2 | MCU_PLL0_HSDIV0_CLKOUT |
0x3 | WKUP_PLLCTL_OBSCLK (MCU_PLL0 input reference clock) |
0x4 | MCU_PLL1_HSDIV1_CLKOUT |
0x5 | MCU_PLL1_HSDIV2_CLKOUT |
0x6 | MCU_PLL1_HSDIV3_CLKOUT |
0x7 | MCU_PLL1_HSDIV4_CLKOUT |
0x8 | MCU_PLL2_HSDIV0_CLKOUT |
0x9 | CLK_32K |
0xA | MCU_PLL2_HSDIV1_CLKOUT |
0xB | MCU_PLL2_HSDIV2_CLKOUT |
0xC | MCU_PLL2_HSDIV3_CLKOUT |
0xD | MCU_PLL2_HSDIV4_CLKOUT |
0xE | WKUP_HFOSC0_CLKOUT |
0xF | WKUP_LFOSC0_CLKOUT |
The value of the software-controlled 4-bit divider is determined by register CTRLMMR_WKUP_MCU_OBSCLK_CTRL[11-8] MCU_OBSCLK_CTRL_CLK _DIV in the WKUP_CTRL_MMR0 module; for more information about control registers, see Section 5.1, Control Module (CTRL_MMR).