SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-625 lists the memory-mapped registers for the PSI-L CFG_PROXY modules which are used to read and write the PSI-L configuration registers described in Section 10.2.8.3. All register offset addresses not listed in Table 10-625 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY | 31F78000h |
MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY | 2A268000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_PSILCFG0_CFG_PROXY Physical Address | MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY Physical Address |
---|---|---|---|---|
0h | PSIL_CFG_PROXY_REVISION | Revision Register | 31F78000h | 2A268000h |
10h | PSIL_CFG_PROXY_TO | PSI-L Proxy Timeout Register | 31F78010h | 2A268010h |
100h | PSIL_CFG_PROXY_CMDA | PSI-L Configuration Proxy Command Register A | 31F78100h | 2A268100h |
104h | PSIL_CFG_PROXY_CMDB | PSI-L Configuration Proxy Command Register B | 31F78104h | 2A268104h |
108h | PSIL_CFG_PROXY_WDATA | PSI-L Configuration Proxy Write Data Register | 31F78108h | 2A268108h |
140h | PSIL_CFG_PROXY_RDATA | PSI-L Configuration Proxy Read Data Register | 31F78140h | 2A268140h |
PSIL_CFG_PROXY_REVISION is shown in Figure 10-231 and described in Table 10-627.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY | 31F78000h |
MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY | 2A268000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66C00100h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66C00100h | TI internal data. |
PSIL_CFG_PROXY_TO is shown in Figure 10-232 and described in Table 10-629.
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The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY | 31F78010h |
MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY | 2A268010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TOUT | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TOUT_CNT | |||||||
R/W-400h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOUT_CNT | |||||||
R/W-400h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | TOUT | R/W | 0h | Timeout occurred. When set indicates that a timeout has occurred on a configuration access. Once set, this bit is persistent until manually cleared. |
30-16 | RESERVED | R/W | X | |
15-0 | TOUT_CNT | R/W | 400h | Timeout period. Specifies how many cycles to wait before closing up a configuration read or write transaction and asserting the TOUT bit |
PSIL_CFG_PROXY_CMDA is shown in Figure 10-233 and described in Table 10-631.
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The Command Register A contains the busy indicator, direction, and thread number for the configuration transaction.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY | 31F78100h |
MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY | 2A268100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BUSY | DIR | TO | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-X | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
THREAD_ID | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THREAD_ID | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BUSY | R/W | 0h | Indication that a configuration read or write is in progress 0h = No transaction is in progress 1h = Transaction is in progress |
30 | DIR | R/W | 0h | Direction of configuration transaction 0h = Write transaction 1h = Read transaction |
29 | TO | R/W | 0h | Indication that a timeout occurred. This bit should be written to 0h on each new transaction. 0h = Transaction completed normally 1h = Timeout occurred |
28-16 | RESERVED | R/W | X | |
15-0 | THREAD_ID | R/W | 0h | Thread ID to which configuration read or write is being sent. The thread ID mapping is shown in PSI-L System Thread Map (All NAVSS) of Navigator Subsystem (NAVSS). |
PSIL_CFG_PROXY_CMDB is shown in Figure 10-234 and described in Table 10-633.
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The Command Register B contains the byte enables and word address for the configuration transaction.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY | 31F78104h |
MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY | 2A268104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BYTEN | RESERVED | ||||||||||||||
R/W-0h | R/W-X | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | BYTEN | R/W | 0h | Byte enables to use for configuration read or write |
27-16 | RESERVED | R/W | X | |
15-0 | ADDRESS | R/W | 0h | Word (32-bit) address within thread configuration space for transaction 0h = Peer thread ID register (PSIL_PEER_THREAD_ID_REG). Implemented for source threads only. 1h = Peer credit register (PSIL_PEER_CREDIT_REG). Implemented for source threads only. 2h = Enable register (PSIL_ENABLE_REG) 40h = Capabilities register (PSIL_LOCAL_CAPABILITIES_REG) 400h = Static TR register |
PSIL_CFG_PROXY_WDATA is shown in Figure 10-235 and described in Table 10-635.
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The Write Data Register contains the data which is to be written during the configuration transaction.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY | 31F78108h |
MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY | 2A268108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDATA | R/W | 0h | Configuration data word to be written |
PSIL_CFG_PROXY_RDATA is shown in Figure 10-236 and described in Table 10-637.
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The Read Data Register contains the data which was read back during the configuration transaction.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY | 31F78140h |
MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY | 2A268140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RDATA | R/W | 0h | Configuration data word that was read |