SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
When the UART_LSR_UART register is read, the UART_LSR_UART[4-2] bit field reflects the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (the next frame status to be read).
The error is triggered by an interrupt (for IrDA mode interrupts, see Table 12-743). The STATUS FIFO must be read until empty (a maximum of eight reads is required).