SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-600 lists the memory-mapped registers for the UDMASS_INTA0_CFG_MCAST. All register offset addresses not listed in Table 10-600 should be considered as reserved locations and the register contents should not be modified.
The Global Event Multicast Registers region is accessed by setting the cfg_rsel signal to 5 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_MCAST | 3111 0000h |
MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST | 2858 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_INTA0_CFG_MCAST Physical Address | MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST Physical Address |
---|---|---|---|---|
0h + formula | UDMA_INTA_MCMAP_j | Multicast event mapping | 3111 0000h + formula | 2858 0000h + formula |
UDMA_INTA_MCMAP_j is shown in Figure 10-221 and described in Table 10-602.
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This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this register, which is selected based in the ingress event index value.
Offset = 0h + (j * 20h); where
j = 0h to 1FFh for NAVSS0_UDMASS_INTA0_CFG_MCAST
j = 0h to 7Fh for MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_MCAST | 3111 0000h + formula |
MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST | 2858 0000h + formula |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESERVED | GEVIDX1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GEVIDX0 | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-48 | RESERVED | R/W | X | |
47-32 | GEVIDX1 | R/W | FFFFh | Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable. |
31-16 | RESERVED | R/W | X | |
15-0 | GEVIDX0 | R/W | FFFFh | Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable. |