SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 5-1363 lists all the possible steps in entering LPM. In the tables further down used are the following abbreviations:
Step Label | Responsible HW/SW | Step Description |
---|---|---|
ACT-0-0 | Various | SoC fully ACTIVE |
ACT-1-0 | HLOS + PM - FW | Identify conditions to enter low power mode |
ACT-1-0.1 | HLOS + PM - FW | HLOS/RTOS + DMSC + DMSC-FW PM policy identifies conditions to enter Standby |
ACT-1-0.2 | HLOS + PM - FW | HLOS/RTOS + DMSC + DMSC-FW PM policy identifies conditions to enter CPD-OFF or DeepSleep |
ACT-1-0.3 | HLOS + PM - FW | HLOS/RTOS + DMSC + DMSC-FW PM policy: identifies conditions to enter MCU-ONLY |
ACT-1-0.4 | HLOS + PM - FW | HLOS/RTOS + DMSC + DMSC-FW PM policy: identifies conditions to enter SuspendToRAM |
ACT-1-0.5 | HLOS + PM - FW | HLOS/RTOS + DMSC + DMSC-FW PM policy: identifies conditions to enter Software Shutdown |
ACT-2-0 | SW | -Virtual-machines running in each core have completed all their tasks and any task involving other modules. - Virtual-machines running in each core have released all peripherals. - Virtual machines are either down or on standby. |
ACT-6-1-1 | SW(C71x) | - Save C71x core context in DDR. - Set C71x in IDLE instruction and memory system ready for c71x to be POWER-OFF. - Turn off power domain for C71x as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-6-2a | SW(A72) + FW | - Save A72 core context in DDR). - Set A72 core_0,1 into WFI and ready to be POWER-OFF as well as . - Set-up A72_CLUSTER_0 ready to complete POWER-OFF of each of its 2 cores. - Turn off power domains PD_A72_0, PD_A72_1 as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). - Set-up A72_CLUSTER_0 ready to POWER-OFF. - Turn off power domain PD_A72_CLUSTER_0 as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview) |
ACT-6-4 | SW | - When going from MCU-ONLY mode to SuspendToRAM no context can be saved to DDR. - Instead a limited amount of MCU context could be saved to external NOR-Flash via FSS. |
ACT-7-2 | SW(A72) + FW | - Set A72_CORE_0, A72_CORE_1 into WFI. |
ACT-8-2 | FW | Disable (SwRstDis), LPSC_MAIN_DEBUG and LPSC_MCU_DBG as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-10-1 | FW | -Save acceleratorpac context to DDR,
MAIN_ACCELLERATOR modules like ENCODER, DECODER, DMPAC. - Prepare accelerators for CLKSTOP and POWER-OFF state. - POWER-OFF power domains for acceleratorpac as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-10-2-3 | SW-FW | - Save context from remaining MAIN power-domains that could be turned OFF depending on usage scenario. - POWER-OFF all other power-domains in MAIN domain that could be POWERED-OFF, excluding PD0 since that is always-on and locked. - For PD domains of type PDRIO, they also could be powered-OFF during Low-Power Modes as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). - To be able to be powered-OFF the reset isolated modules all their RST_ISO bits needs to be cleaned inside PSC for all the LPSC components of a given power domain. - At this point the LPSCs associated with PD0 are still enabled. - Power OFF domains and disable LPSCs as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-10-4-1 | FW | - Save MSMC-CFG to DDR. - Save any other context required to DDR from the top-of the Compute Cluster and MSMC. - Save limit set of WR register values from CTRL_MMR0 to DDR. |
ACT-10-4-2 | FW | - Save CTRLMMR_MAIN_DEVSTAT in DMSC RAM. - Save CTRLMMR_MAIN_BOOTCFG register from CTRL_MMR0 in DMSC RAM. |
ACT-11-01 | SW(R5x) + FW | - R5FSS context save to DDR. - Perform cache manage and WFI sequence for R5FSS in order to get it ready for POWER-OFF. - Turn off power domains for R5FSSs cluster PD_R5FSS_0 as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-11-4a | SW(C66x) + FW | - C66x context save to DDR. - Set C66x in IDLE instruction and memory system ready for C66x to be POWER-OFF. - POWER-OFF C66x (PD_C66x_0 and PD_C66x_1) as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-11-05 | FW | - Save DDR config to DMSC-RAM. -Set LPSCs for DDR in SwRstDis state. - For PD0 (GP_CORE_CTL) (the only PD still ON) in PSC0, set ALL remaining LPSCs in SwRstDis state (except LPSC0 which is locked) as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-11-06 | FW | - Set the following LPSC to SwRstDis: LPSC_MAIN2WKUPMCU - Disable all the HSDIVs in MAIN. Except the one providing clock MAIN_PLL0_HSDIV0_CLKOUT to PLLCTRL , namely HSDIV0 of PLL0. - Disable all the PLLs in MAIN. Except PLL0. - Now set PLLCTRL (MAIN_PLL0_HSDIV0_CLKOUT) in bypass mode. - Disable PLL0. - Set all of the following LPSCs, in WKUP_PSC0, to SwRstDis as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview): LPSC_DEBUG2DMSC, LPSC_WKUPMCU2MAIN. - If it wasn't already, switch WKUP_HFOSC0 to HFOSC1 as input reference to PLL0, by writing CTRLMMR_WKUP_MAIN_PLL0_CLKSEL[0] CLK_SEL = 1. - POWER-OFF HFOSC1 by writing to CTRLMMR_WKUP_HFOSC1_CTRL[7] PD_C = 1 in WKUP_CTRL_MMR0. |
ACT-12-00 | FW | Place DDR in Self Refresh Mode |
ACT-12-02 | FW | MCU_ONLY.MCU_R5FSS_ACTIVE >> Place DDR in Self Refresh Mode |
ACT-13-01 | FW(DMSC) | Set all the other LPSCs of WKUP_PSC0 except PD0 (GP_CORE_CTL_WKUP) to SwRstDis state as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview), except for the ones below: - Keep enable the LPSCs LPSC_WKUP_ALWAYSON, LPSC_DMSC, LPSC_WKUP_GPIO. |
ACT-13-02 | FW(DMSC) | -If the WKUP_GPIOs need to detect wake-up events independently of the WKUP-IO-PM-DCH, then GPIOs need to remain fully functional and clocked during DeepSleep. - To do that do the following:
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ACT-14-01 | FW-DMSC | For Modes with R5FSS OFF, except MCU-ONLY. R5FSS-OFF>> - MCU_R5FSS context save to DDR. - Perform cache manage and WFI/WFE sequence for MCU_R5FSS in order to get it ready for POWER-OFF. - Turn off power domain - PD_MCU_R5FSS, for MCU_R5FSS as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-14-02 | FW-DMSC | For MCU_ONLY. R5FSS-OFF >> - MCU_R5FSS context save to Flash. - Perform cache manage and WFI/WFE sequence for MCU_R5FSS in order to get it ready for POWER-OFF. - Turn off power domain - PD_MCU_R5FSS, for MCU_R5FSS as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-15-1 | FW | MCU_R5FSS enters WFI/WFE mode |
ACT-14-3 | FW | ForModes with R5FSS OFF >> - DMSC off power domain for MCU_R5FSS as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-21 | FW(DMSC) | DMSC sends commands to PMIC via WKUP_I2C0 to turn off all the supply, so device goes to OFF state. |
ACT-22-1 | FW(DMSC) | DMSC sends command to PMIC via WKUP_I2C0 to set desired wakeup events inside PMIC which will trigger wake-up from SuspendToRAM. |
ACT-22-2 | FW(DMSC) | Send command to PMIC via WKUP_I2C0 to assert from the board DDR_RET chip input. |
ACT-22-3 | FW(DMSC) | DMSC sends command to PMIC via WKUP_I2C0 to turn off all the supply except the supply to DDR IO (and except RTC supply inside PMIC), for PMIC/SoC to enter SuspendToRAM mode (PMIC-LP_State). |
ACT-16-1 | FW(DMSC) | If enable, disable the following LPSCs: LPSC_MCU_DEBUG, LPSC_MCU_TEST. |
ACT-16-2 | FW(DMSC) | Before entering MCU_ONLY mode disable all VTM temperature sensors that are on the SOC_MAIN portion of the SoC: VTM_TMPSENS1-4. At the same time make sure that the TEMP sensor in the VD_WKUP is enabled and running to keep monitoring temperature: VTM_TMPSENS0 |
ACT-17-1 | FW | - Save to DMSC-RAM and disable POK modules related to SoC_MAIN core portion of the SoC via WKUP_CTRL_MMR0 module: POK_VDD_CORE_UV_CTRL, POK_VDD_CPU_UV_CTRL, POK_VDDR_CORE_UV_CTRL, POK_VMON_EXT_UV_CTRL POK_VDD_CORE_OV_CTRL,POK_VDD_CPU_OV_CTRL, POK_VDDR_CORE_OV_CTRL, POK_VMON_EXT_OV_CTRL - First save and disable their contribution to ESM events - Next save and disable their contribution to PRG reset, CTRLMMR_WKUP_MAIN_PRG_CTRL all POK_*_EN = 0. |
ACT-17-2 | FW | - Disable any still enable POK modules. - Disable any ESM event generation going OFF-Chip. |
ACT-17-2-2 | FW | - DMSC asserts PMIC_POWER_EN1 (the pin for SoC to communicate with PMIC) to turn-off the power supplies to VDD_CORE and VDD_CPU and IO-supplies that feed - USB, SERDES and PLLs in MAIN. or - DMSC sends commands to PMIC via WKUP_I2C0 to turn-off the power supplies to VDD_CORE and VDD_CPU and IO-supplies that feed - USB, SERDES and PLLs in MAIN. |
ACT-18 | FW | DMSC informs PMIC to shut off supply to WKUP/MCU domain and only keep supply to DDR IO to enter SuspendToRAM state (PMIC-LP_State) |
ACT-19-1 | FW | - Via WKUP_CTRL_MMR0 module, remove the reset-isolation blocking on the MAIN_PORZ propagation: CTRLMMR_WKUP_POR_RST_CTRL[0] POR_RST_ISO_DONE_Z = 0. - Via WKUP_CTRL_MMR0 module apply PORz to SoC_MAIN: CTRLMMR_WKUP_POR_RST_CTRL[19-16] SW_MAIN_POR = 4'b0110 . |
ACT-19-2 | FW | Set CTRLMMR_WKUP_MAIN_VDOM_CTRL[0] MAIN_VD_OFF = 1 in WKUP_CTRL_MMR0 module prior to powering off the main voltage domain to ensure proper signal isolation. |
ACT-25-00 | SW+FW | START MAIN-IO-Power-Management daisy-chain (IO-PM-DCH) low power mode entry sequence via FW: |
ACT-25-01 | SW+FW | MAIN-IO-Power-Management daisy-chain (IO-PM-DCH) low power mode entry sequence via FW: - Prior to the DMSC IO-PM-DCH sequence, Software-driver and R5F-FW determines what are the deep sleep (DS) configuration values to be set in the CTRLMMR_PADCONFIGi (i = 0 to 172) for all MAIN-IOs, and sets those registers. - Those same configuration values will apply regardless if it is any LowPowerMode entry that uses MAIN-IO-PM daisy-chain. There is only one DS setting in the PADCFG register. NOTE: If the END-TARGET LOW POWER MODE is either of MCU-ONLY or SuspendToRAM modes then:
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ACT-25-02a | FW(DMSC) | Main-IO-PM-DCH: Kick-Off propagation of all the CTRLMMR_PADCONFIGi (i = 0 to 172) registers selections for Wake-up event enables ([29] WKUP_EN bit), and iso-bypass ([23] ISO_BYP bit) to all IOs in main-region IO-PM-DCH. Read-modify write to DMSC power registers, see DMSC addendum for more information. |
ACT-25-02b | FW(DMSC) | Main-IO-PM-DCH: Kick-Off propagation of all the CTRLMMR_PADCONFIGi (i = 0 to 172) registers selections for Wake-up event enables ([29] WKUP_EN bit) to all IOs in main-region IO-PM-DCH. When the VDD_CORE is OFF NO-ISOBYPASS is supported. Read-modify write to DMSC power registers, see DMSC addendum for more information. |
ACT-25-03 | FW(DMSC) | Main-IO-PM-DCH: Kick-Off propagation of all the DeepSleep selection settings for IO inputs pupdsel, pi, gz from CTRLMMR_PADCONFIGi (i = 0 to 172) registers to all IOs in main-region IO-PM-DCH. Write WKUP_CTRL_MMR0 CTRLMMR_WKUP_DEEPSLEEP_CTRL[8] FORSE_DS_MAIN to force the deep sleep value onto pins. |
ACT-25-04 | FW(DMSC) | Main-IO-PM-DCH: Latch the wakeup event enabled in all IOs whose PADCFG register has WUEN bit set by toggling the WUCLK. WUCLK is toggled by writing '1' to a register in DMSC. WUCLK_CTRL_1 ( B[8]) then poling until PMCTRL_IO_1.WUCLK_STATUS_1 ( B[9]) = '1'. Next is to drive WUCLK=0 by writing '0' to MMR bit PMCTRL_IO_1.WUCLK_CTRL_1 ( B[8]) then poling until PMCTRL_IO_1.WUCLK_STATUS_1 ( B[9]) = '0'. |
ACT-25-05 | FW(DMSC) | Main-IO-PM-DCH: Kick-Off isolation and isolation sequence of all IOs in main-region IO-PM-DCH. Read-modify write to DMSC PMCTRL_IO_1, writing 1'b1 to bit PMCTRL_IO_1[24]. |
ACT-25-10 | SW+FW | DMSC start to set WkupMcu IO into daisy-chain low power mode: - Prior to the DMSC's Wkup-MCU IO-PM-DCH sequence, Software-driver + R5-FW determines what are the deep sleep (DS) configuration values to be set in the Wkup PAD-CFG for all Wkup-IOs, and sets those registers. - Those same config values will apply regardless if it is any LowPowerMode entry that uses Wkup-IO-PM daisy-chain. There is only one DS setting in the PADCFG MMRs. |
ACT-25-11 | FW(DMSC) | Wkup-IO-Power-Management daisy-chain (Wkup-IO-PM-DCH) low power mode entry sequence via FW: Wait for completion of Isolation in Main-IO-PM-DCH. Keep polling bit PMCTRL_IO_1[25] until it shows '1' to indicate completion of isolation sequence for Main-IO-PM-DCH. |
ACT-25-12 | FW(DMSC) | Wkup-IO-PM-DCH: Kick-Off propagation of all the CTRLMMR_WKUP_PADCONFIGi (i = 0 to 93) registers selections for Wake-up event enables ([29] WKUP_EN bit), and iso-bypass ([23] ISO_BYP bit) to all IOs in Wkup-region IO-PM-DCH. Read-modify write to DMSC register PMCTRL_IO_0, writing 2'b11 to bits PMCTRL_IO_0[16, 6] |
ACT-25-13 | FW(DMSC) | Wkup-IO-PM-DCH: Kick-Off propagation of all the DeepSleep selection settings for IO inputs pupdsel, pi, gz from CTRLMMR_WKUP_PADCONFIGi (i = 0 to 93) to all IOs in Wkup-region IO-PM-DCH. Write 0x00000001 to DMSC register FW_CTRL_OUT0_SET. |
ACT-25-14 | FW(DMSC) | Wkup-IO-PM-DCH: Latch the wakeup event enabled in all IOs whose PADCFG has WUEN bit set by toggling the WUCLK. WUCLK is toggled by writing '1' to MMR bit PMCTRL_IO_0.WUCLK_CTRL_0 ( B[8]) then poling until PMCTRL_IO_0.WUCLK_STATUS_0 ( B[9]) = '1'. Next is to drive WUCLK=0 by writing '0' to MMR bit PMCTRL_IO_0.WUCLK_CTRL_0 ( B[8]) then poling until PMCTRL_IO_0.WUCLK_STATUS_0 ( B[9]) = '0'. |
ACT-25-15 | FW(DMSC) | Wkup-IO-PM-DCH: Kick-Off isolation and isolation sequence of all IOs in Wkup-region IO-PM-DCH. Configure WKUP_CTRL_MMR POR_RST_CTRL as needed Read-modify write to DMSC's MMR PMCTRL_IO_0, writing 1'b1 to bit PMCTRL_IO_0[24]. |
ACT-25-16 | FW(DMSC) | Wkup-IO-PM-DCH: Wait for completion of Isolation in Wkup-IO-PM-DCH. Keep polling bit PMCTRL_IO_0[25] until it shows '1' to indicate completion of isolation sequence for Wkup-IO-PM-DCH. At this point the DMSC-M3 will finish/complete the low-power mode code sequence to the point it goes into WFI state. The entering of M3 into WFI causes the DMSC internal low power sequence to kick-in and DMSC will complete it and wait until a wake-up event. |
ACT-26 | FW | Set LPSC_DEBUG2DMSC, LPSC_WKUPMCU2MAIN, LPSC_MAIN2WKUPMCU to SwRstDis as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
ACT-28-01 | DMSC-FW | (If OFF-Mode or SuspendToRAM-Mode skip this) DMSC-FW config DMSC in LPM0. - Kick LPM Entry in DMSC by setting WFI in DMSC's M3. |
ACT-29-01 | DMSC-FW | (If OFF-Mode or SuspendToRAM-Mode skip this) -Configure DMSC for LPM4 or LPM3. - This should include enabling the interrupts and wake-up events that are desired to cause a wakeup out of the LPM. - The IO-PM daisy-chains for both Main-IO-PM-DCH and WKUP-IO-PM-DCH must be included among the wake-up events. |
ACT-29-02 | DMSC-FW | (If OFF-Mode or SuspendToRAM-Mode skip this) -Switch the input clock for WKUP_PLLCTRL0 from MCU_PLL0/HSDIV_CLKOUT to WKUP_HFOSC0_CLKOUT. - Set WKUP_PLL_CTRL register PLLCTL[0] PLLEN = 0 and PLLCTL[5] PLLENSRC = 1. - The IO-PM daisy-chains for both Main-IO-PM-DCH and WKUP-IO-PM-DCH must be included among the wake-up events. - Set MCU_PLL0 in bypass mode. |
ACT-29-03 | DMSC-FW | (If OFF-Mode or SuspendToRAM-Mode skip this) -Kick LPM Entry in DMSC by setting WFI in DMSC's M3. |
BR-00-1 | BRANCH | <<<< Steps-specific to MCU_ONLY.MCU_R5FSS_Active Step-set-BR-00: BEGIN |
BR-00-2 | BRANCH | >>>>Steps-specific to MCU_ONLY.MCU_R5FSS_Active Step-set-BR-00:END |
BR-10-1 | BRANCH | <<<< Steps-specific to MCU_ONLY.MCU_R5FSS_OFF Step-set-BR-10: BEGIN |
BR-10-2 | BRANCH | >>>>Steps-specific to MCU_ONLY.MCU_R5FSS_OFF Step-set-BR-10:END |
Table 5-1364 through Table 5-1368 present the steps to enter LPM states, using the Step Label from Table 5-1363.
Step | Step Label |
---|---|
1 | ACT-0-0 |
2 | ACT-1-0.1 |
3 | ACT-2-0 |
4 | ACT-7-2 |
Device in STANDBY mode |
Step | Step Label |
---|---|
1 | ACT-0-0 |
2 | ACT-1-0.2 |
3 | ACT-2-0 |
4 | ACT-6-1-1 |
5 | ACT-6-2a |
6 | ACT-11-4a |
7 | ACT-11-01 |
8 | ACT-10-1 |
9 | ACT-10-2-3 |
10 | ACT-10-4-1 |
11 | ACT-10-4-2 |
12 | ACT-25-00 |
13 | ACT-25-01 |
14 | ACT-25-02a |
15 | ACT-25-03 |
16 | ACT-25-04 |
17 | ACT-25-05 |
18 | ACT-16-1 |
19 | ACT-12-00 |
20 | ACT-22-2 |
21 | ACT-11-05 |
22 | ACT-11-06 |
Device enters CPD-OFF mode | |
23 | ACT-14-01 |
24 | ACT-12-00 |
25 | ACT-22-2 |
26 | ACT-11-05 |
27 | ACT-11-06 |
28 | ACT-25-10 |
29 | ACT-25-11 |
30 | ACT-25-12 |
31 | ACT-25-13 |
32 | ACT-25-14 |
33 | ACT-25-15 |
34 | ACT-25-16 |
35 | ACT-13-01 |
36 | ACT-13-02 |
37 | ACT-29-01 |
38 | ACT-29-02 |
39 | ACT-29-03 |
Device enters Deep-Sleep mode |
NOTICE that there are a few steps in Table 5-1365 ACTIVE to CPD-OFF part of the table which should be skip if the transition is from ACTIVE to DeepSleep. If the device is already in CPD-OFF and need to transition to DeepSleep, then the content of R5F can't be save to DDR and will have to be saved to FLASH. Alternativelly the context of R5F will be lost and the MCU_R5FSS in next wakeup if it stays in CPD-OFF state the R5Fwill start from scratch without context restored.
Step | Step Label |
---|---|
1 | ACT-0-0 |
2 | ACT-1-0 |
3 | ACT-1-0.3 |
4 | ACT-2-0 |
5 | ACT-6-1-1 |
6 | ACT-6-2a |
7 | ACT-11-01 |
8 | ACT-10-1 |
9 | ACT-10-2-3 |
10 | ACT-10-4-1 |
11 | ACT-10-4-2 |
12 | ACT-25-00 |
13 | ACT-25-01 |
14 | ACT-25-02b |
15 | ACT-25-03 |
16 | ACT-25-04 |
17 | ACT-25-05 |
18 | ACT-12-00 |
19 | ACT-22-2 |
20 | ACT-11-05 |
21 | ACT-11-06 |
22 | ACT-17-1 |
23 | ACT-19-2 |
24 | ACT-19-1 |
25 | ACT-22-2 |
26 | ACT-17-2-2 |
27 | ACT-16-1 |
28 | ACT-16-2 |
29 | ACT-15-1 |
30 | ACT-29-02 |
31 | ACT-28-01 |
Device is now in MCU-ONLY.R5FSS_ACTIVE mode | |
32 | ACT-14-02 |
33 | ACT-25-10 |
34 | ACT-25-11 |
35 | ACT-25-12 |
36 | ACT-25-13 |
37 | ACT-25-14 |
37 | ACT-25-15 |
39 | ACT-25-16 |
40 | ACT-13-01 |
41 | ACT-13-02 |
42 | ACT29-02 |
43 | ACT29-03 |
Device is now in MCU-ONLY.R5FSS_OFF mode | |
44 | ACT21 |
Device is now in OFF mode |
Step | Step Label |
---|---|
1 | ACT-0-0 |
2 | ACT-1-0.4 |
3 | ACT-2-0 |
4 | ACT-6-1-1 |
5 | ACT-6-2a |
6 | ACT-11-4a |
7 | ACT-11-01 |
8 | ACT-10-1 |
9 | ACT-10-2-3 |
10 | ACT-10-4-1 |
11 | ACT-10-4-2 |
12 | ACT-13-01 |
13 | ACT-14-01 |
14 | ACT-12-00 |
15 | ACT-13-01 |
16 | ACT-17-2 |
17 | ACT-22-1 |
18 | ACT-22-2 |
19 | ACT-22-3 |
SoC and PMIC are now in SuspendToRAM mode |
Step | Step Label |
---|---|
1 | ACT-1-0.4 |
2 | ACT-6-4 |
3 | ACT-17-2 |
4 | ACT-22-1 |
5 | ACT-22-2 |
6 | ACT-22-3 |
SoC and PMIC are now in SuspendToRAM mode |