SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are two MCAN modules integrated in the device MCU domain - MCU_MCAN0 and MCU_MCAN1.
Figure 12-2729 shows the integration of MCU_MCAN0.
Figure 12-2730 shows the integration of MCU_MCAN1.
Table 12-5196 through Table 12-5198 summarize the integration of MCU_MCAN0 and MCU_MCAN1 in the device MCU domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MCU_MCAN0 | WKUP_PSC0 | PD0 | LPSC8 | MCU_CBASS0 |
MCU_MCAN1 | WKUP_PSC0 | PD0 | LPSC9 | MCU_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCU_MCAN0 | MCU_MCAN0_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | Interface Clock |
MCU_MCAN0_FCLK | MCU_PLL2_HSDIV3_CLKOUT (default) | MCU_PLL2 HSDIV3 | Functional Clock (for more information about clock multiplexing, see CTRLMMR_MCU_MCAN0_CLKSEL[1-0] CLK_SEL bit field in Control Module (CTRL_MMR). Default: CTRLMMR_MCU_MCAN0_CLKSEL[1-0] CLK_SEL = 0h, MCU_PLL2_HSDIV3_CLKOUT is selected) | |
MCU_EXT_REFCLK0 | I/O pin | |||
MCU_PLL1_HSDIV2_CLKOUT | MCU_PLL1 HSDIV2 | |||
WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | |||
MCU_MCAN1 | MCU_MCAN1_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | Interface Clock |
MCU_MCAN1_FCLK | MCU_PLL2_HSDIV3_CLKOUT (default) | MCU_PLL2 HSDIV3 | Functional Clock (for more information about clock multiplexing, see CTRLMMR_MCU_MCAN1_CLKSEL[1-0] CLK_SEL bit field in Control Module (CTRL_MMR). Default: CTRLMMR_MCU_MCAN1_CLKSEL[1-0] CLK_SEL = 0h, MCU_PLL2_HSDIV3_CLKOUT is selected) | |
MCU_EXT_REFCLK0 | I/O pin | |||
MCU_PLL1_HSDIV2_CLKOUT | MCU_PLL1 HSDIV2 | |||
WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCU_MCAN0 | MCU_MCAN0_RST | MOD_G_RST | LPSC8 | Asynchronous Module Reset |
MCU_MCAN1 | MCU_MCAN1_RST | MOD_G_RST | LPSC9 | Asynchronous Module Reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_MCAN0 | MCU_MCAN0_MCANSS_MCAN_LVL_INT_0 | GIC500_SPI_IN_864 | COMPUTE_CLUSTER0 | MCU_MCAN0 Line 0 Interrupt Request | Level |
R5FSS0_CORE0_INTR_IN_374 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_374 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_0 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_0 | MCU_R5FSS0_CORE1 | ||||
MCU_MCAN0_MCANSS_MCAN_LVL_INT_1 | GIC500_SPI_IN_865 | COMPUTE_CLUSTER0 | MCU_MCAN0 Line 1 Interrupt Request | Level | |
R5FSS0_CORE0_INTR_IN_375 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_375 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_1 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_1 | MCU_R5FSS0_CORE1 | ||||
MCU_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 | GIC500_SPI_IN_866 | COMPUTE_CLUSTER0 | MCU_MCAN0 External TimeStamp Counter Rollover Interrupt | Level | |
R5FSS0_CORE0_INTR_IN_376 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_376 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_4 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_4 | MCU_R5FSS0_CORE1 | ||||
MCU_MCAN0_MCANSS_ECC_CORR_LVL_INT_0 | MCU_ESM0_LVL_IN_16 | MCU_ESM0 | MCU_MCAN0 ECC Correctable Error Interrupt Request | Level | |
MCU_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0 | MCU_ESM0_LVL_IN_17 | MCU_ESM0 | MCU_MCAN0 ECC Uncorrectable Error Interrupt Request | Level | |
MCU_MCAN1 | MCU_MCAN1_MCANSS_MCAN_LVL_INT_0 | GIC500_SPI_IN_867 | COMPUTE_CLUSTER0 | MCU_MCAN1 Line 0 Interrupt Request | Level |
R5FSS0_CORE0_INTR_IN_377 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_377 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_2 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_2 | MCU_R5FSS0_CORE1 | ||||
MCU_MCAN1_MCANSS_MCAN_LVL_INT_1 | GIC500_SPI_IN_868 | COMPUTE_CLUSTER0 | MCU_MCAN1 Line 1 Interrupt Request | Level | |
R5FSS0_CORE0_INTR_IN_378 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_378 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_3 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_3 | MCU_R5FSS0_CORE1 | ||||
MCU_MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 | GIC500_SPI_IN_869 | COMPUTE_CLUSTER0 | MCU_MCAN1 External TimeStamp Counter Rollover Interrupt | Level | |
R5FSS0_CORE0_INTR_IN_379 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_379 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_5 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_5 | MCU_R5FSS0_CORE1 | ||||
MCU_MCAN1_MCANSS_ECC_CORR_LVL_INT_0 | MCU_ESM0_LVL_IN_18 | MCU_ESM0 | MCU_MCAN1 ECC Correctable Error Interrupt Request | Level | |
MCU_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0 | MCU_ESM0_LVL_IN_19 | MCU_ESM0 | MCU_MCAN1 ECC Uncorrectable Error Interrupt Request | Level |