SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes WKUP_CTRL_MMR0 integration in the device, including information about clocks, resets, and hardware requests.
A single WKUP_CTRL_MMR0 module is integrated in the device WKUP domain. Figure 5-1 shows the integration of WKUP_CTRL_MMR0.
Table 5-1 through Table 5-3 summarize the integration of the WKUP_CTRL_MMR0 module in the device WKUP domain.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
WKUP_CTRL_MMR0 | WKUP_PSC0 | PD0 | LPSC0 | WKUP_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
WKUP_CTRL_MMR0 | WKUP_CTRL_MMR0_FICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | Functional and interface clock for the WKUP_CTRL_MMR0 module with frequency equal to MCU_SYSCLK0 divided by 6. |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
WKUP_CTRL_MMR0 | WKUP_CTRL_MMR0_RST | MOD_G_RST | LPSC0 | Module level main reset |
WKUP_CTRL_MMR0_POR_RST | MOD_POR_RST | LPSC0 | Module power-on reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
WKUP_CTRL_MMR0 | WKUP_CTRL_MMR0_ACCESS_ERR_0 | WKUP_DMSC0_INTR_IN_26 | WKUP_DMSC0 | Interrupt indicating protection, addressing, lock violation. | Level |
MCU_R5FSS0_CORE0_INTR_IN_119 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_119 | MCU_R5FSS0_CORE1 | ||||
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
WKUP_CTRL_MMR0 | - | - | - | - | - |
For more information about WKUP_CTRL_MMR0_ACCESS_ERR_0, see Section 5.1.1.3.1.3.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.