SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5215 lists the memory-mapped registers for the MCAN Subsystem (MCANSS). All register offset addresses not listed in Table 12-5215 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_MCAN0_SS | 4052 0000h |
MCU_MCAN1_SS | 4056 0000h |
MCAN0_SS | 0270 0000h |
MCAN1_SS | 0271 0000h |
MCAN2_SS | 0272 0000h |
MCAN3_SS | 0273 0000h |
MCAN4_SS | 0274 0000h |
MCAN5_SS | 0275 0000h |
MCAN6_SS | 0276 0000h |
MCAN7_SS | 0277 0000h |
MCAN8_SS | 0278 0000h |
MCAN9_SS | 0279 0000h |
MCAN10_SS | 027A 0000h |
MCAN11_SS | 027B 0000h |
MCAN12_SS | 027C 0000h |
MCAN13_SS | 027D 0000h |
MCAN14_SS | 0268 0000h |
MCAN15_SS | 0269 0000h |
MCAN16_SS | 026A 0000h |
MCAN17_SS | 026B 0000h |
Offset | Acronym | Register Name | MCU_MCAN0_SS Physical Address | MCU_MCAN1_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 4052 0000h | 4056 0000h |
4h | MCANSS_CTRL | Control Register | 4052 0004h | 4056 0004h |
8h | MCANSS_STAT | Status Register | 4052 0008h | 4056 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 4052 000Ch | 4056 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 4052 0010h | 4056 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 4052 0014h | 4056 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 4052 0018h | 4056 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 4052 001Ch | 4056 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 4052 0020h | 4056 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 4052 0024h | 4056 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 4052 0028h | 4056 0028h |
Offset | Acronym | Register Name | MCAN0_SS Physical Address | MCAN1_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 0270 0000h | 0271 0000h |
4h | MCANSS_CTRL | Control Register | 0270 0004h | 0271 0004h |
8h | MCANSS_STAT | Status Register | 0270 0008h | 0271 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 0270 000Ch | 0271 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 0270 0010h | 0271 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 0270 0014h | 0271 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 0270 0018h | 0271 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 0270 001Ch | 0271 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 0270 0020h | 0271 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 0270 0024h | 0271 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 0270 0028h | 0271 0028h |
Offset | Acronym | Register Name | MCAN2_SS Physical Address | MCAN3_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 0272 0000h | 0273 0000h |
4h | MCANSS_CTRL | Control Register | 0272 0004h | 0273 0004h |
8h | MCANSS_STAT | Status Register | 0272 0008h | 0273 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 0272 000Ch | 0273 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 0272 0010h | 0273 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 0272 0014h | 0273 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 0272 0018h | 0273 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 0272 001Ch | 0273 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 0272 0020h | 0273 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 0272 0024h | 0273 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 0272 0028h | 0273 0028h |
Offset | Acronym | Register Name | MCAN4_SS Physical Address | MCAN5_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 0274 0000h | 0275 0000h |
4h | MCANSS_CTRL | Control Register | 0274 0004h | 0275 0004h |
8h | MCANSS_STAT | Status Register | 0274 0008h | 0275 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 0274 000Ch | 0275 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 0274 0010h | 0275 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 0274 0014h | 0275 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 0274 0018h | 0275 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 0274 001Ch | 0275 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 0274 0020h | 0275 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 0274 0024h | 0275 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 0274 0028h | 0275 0028h |
Offset | Acronym | Register Name | MCAN6_SS Physical Address | MCAN7_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 0276 0000h | 0277 0000h |
4h | MCANSS_CTRL | Control Register | 0276 0004h | 0277 0004h |
8h | MCANSS_STAT | Status Register | 0276 0008h | 0277 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 0276 000Ch | 0277 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 0276 0010h | 0277 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 0276 0014h | 0277 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 0276 0018h | 0277 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 0276 001Ch | 0277 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 0276 0020h | 0277 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 0276 0024h | 0277 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 0276 0028h | 0277 0028h |
Offset | Acronym | Register Name | MCAN8_SS Physical Address | MCAN9_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 0278 0000h | 0279 0000h |
4h | MCANSS_CTRL | Control Register | 0278 0004h | 0279 0004h |
8h | MCANSS_STAT | Status Register | 0278 0008h | 0279 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 0278 000Ch | 0279 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 0278 0010h | 0279 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 0278 0014h | 0279 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 0278 0018h | 0279 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 0278 001Ch | 0279 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 0278 0020h | 0279 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 0278 0024h | 0279 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 0278 0028h | 0279 0028h |
Offset | Acronym | Register Name | MCAN10_SS Physical Address | MCAN11_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 027A 0000h | 027B 0000h |
4h | MCANSS_CTRL | Control Register | 027A 0004h | 027B 0004h |
8h | MCANSS_STAT | Status Register | 027A 0008h | 027B 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 027A 000Ch | 027B 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 027A 0010h | 027B 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 027A 0014h | 027B 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 027A 0018h | 027B 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 027A 001Ch | 027B 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 027A 0020h | 027B 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 027A 0024h | 027B 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 027A 0028h | 027B 0028h |
Offset | Acronym | Register Name | MCAN12_SS Physical Address | MCAN13_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 027C 0000h | 027D 0000h |
4h | MCANSS_CTRL | Control Register | 027C 0004h | 027D 0004h |
8h | MCANSS_STAT | Status Register | 027C 0008h | 027D 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 027C 000Ch | 027D 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 027C 0010h | 027D 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 027C 0014h | 027D 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 027C 0018h | 027D 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 027C 001Ch | 027D 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 027C 0020h | 027D 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 027C 0024h | 027D 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 027C 0028h | 027D 0028h |
Offset | Acronym | Register Name | MCAN14_SS Physical Address | MCAN15_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 0268 0000h | 0269 0000h |
4h | MCANSS_CTRL | Control Register | 0268 0004h | 0269 0004h |
8h | MCANSS_STAT | Status Register | 0268 0008h | 0269 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 0268 000Ch | 0269 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 0268 0010h | 0269 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 0268 0014h | 0269 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 0268 0018h | 0269 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 0268 001Ch | 0269 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 0268 0020h | 0269 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 0268 0024h | 0269 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 0268 0028h | 0269 0028h |
Offset | Acronym | Register Name | MCAN16_SS Physical Address | MCAN17_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 026A 0000h | 026B 0000h |
4h | MCANSS_CTRL | Control Register | 026A 0004h | 026B 0004h |
8h | MCANSS_STAT | Status Register | 026A 0008h | 026B 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 026A 000Ch | 026B 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 026A 0010h | 026B 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 026A 0014h | 026B 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 026A 0018h | 026B 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 026A 001Ch | 026B 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 026A 0020h | 026B 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 026A 0024h | 026B 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 026A 0028h | 026B 0028h |
MCANSS_PID is shown in Figure 12-2751 and described in Table 12-5226.
Return to Summary Table.
Revision Register
The Revision Register contains the major and minor revisions for the MCANSS.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0000h |
MCU_MCAN1_SS | 4056 0000h |
MCAN0_SS | 0270 0000h |
MCAN1_SS | 0271 0000h |
MCAN2_SS | 0272 0000h |
MCAN3_SS | 0273 0000h |
MCAN4_SS | 0274 0000h |
MCAN5_SS | 0275 0000h |
MCAN6_SS | 0276 0000h |
MCAN7_SS | 0277 0000h |
MCAN8_SS | 0278 0000h |
MCAN9_SS | 0279 0000h |
MCAN10_SS | 027A 0000h |
MCAN11_SS | 027B 0000h |
MCAN12_SS | 027C 0000h |
MCAN13_SS | 027D 0000h |
MCAN14_SS | 0268 0000h |
MCAN15_SS | 0269 0000h |
MCAN16_SS | 026A 0000h |
MCAN17_SS | 026B 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-8E0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-Ah | R-1h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | Business Unit (2h = Processors) |
27-16 | MODULE_ID | R | 8E0h | Module ID |
15-11 | RTL | R | Ah | RTL Revision |
10-8 | MAJOR | R | 1h | Major Revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 1h | Minor Revision |
MCANSS_CTRL is shown in Figure 12-2752 and described in Table 12-5228.
Return to Summary Table.
Control Register
The Control Register contains general control bits for the MCANSS.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0004h |
MCU_MCAN1_SS | 4056 0004h |
MCAN0_SS | 0270 0004h |
MCAN1_SS | 0271 0004h |
MCAN2_SS | 0272 0004h |
MCAN3_SS | 0273 0004h |
MCAN4_SS | 0274 0004h |
MCAN5_SS | 0275 0004h |
MCAN6_SS | 0276 0004h |
MCAN7_SS | 0277 0004h |
MCAN8_SS | 0278 0004h |
MCAN9_SS | 0279 0004h |
MCAN10_SS | 027A 0004h |
MCAN11_SS | 027B 0004h |
MCAN12_SS | 027C 0004h |
MCAN13_SS | 027D 0004h |
MCAN14_SS | 0268 0004h |
MCAN14_SS | 0269 0004h |
MCAN16_SS | 026A 0004h |
MCAN17_SS | 026B 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_EN | AUTOWAKEUP | WAKEUPREQEN | DBGSUSP_FREE | RESERVED | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6 | EXT_TS_CNTR_EN | R/W | 0h | External Timestamp Counter Enable |
5 | AUTOWAKEUP | R/W | 0h | Automatic Wakeup Enable |
4 | WAKEUPREQEN | R/W | 0h | Wakeup Request Enable |
3 | DBGSUSP_FREE | R/W | 1h | Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend |
2-0 | RESERVED | R | 0h | Reserved |
MCANSS_STAT is shown in Figure 12-2753 and described in Table 12-5230.
Return to Summary Table.
Status Register
The Status Register provides general status bits for the MCANSS.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0008h |
MCU_MCAN1_SS | 4056 0008h |
MCAN0_SS | 0270 0008h |
MCAN1_SS | 0271 0008h |
MCAN2_SS | 0272 0008h |
MCAN3_SS | 0273 0008h |
MCAN4_SS | 0274 0008h |
MCAN5_SS | 0275 0008h |
MCAN6_SS | 0276 0008h |
MCAN7_SS | 0277 0008h |
MCAN8_SS | 0278 0008h |
MCAN9_SS | 0279 0008h |
MCAN10_SS | 027A 0008h |
MCAN11_SS | 027B 0008h |
MCAN12_SS | 027C 0008h |
MCAN13_SS | 027D 0008h |
MCAN14_SS | 0268 0008h |
MCAN14_SS | 0269 0008h |
MCAN16_SS | 026A 0008h |
MCAN17_SS | 026B 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_FDOE | MEM_INIT_DONE | RESERVED | ||||
R-0h | R- | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | ENABLE_FDOE | R | -h | Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port, -h = mcanss_enable_fdoe. |
1 | MEM_INIT_DONE | R | 0h | Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done |
0 | RESERVED | R | 0h | Reserved |
MCANSS_ICS is shown in Figure 12-2754 and described in Table 12-5232.
Return to Summary Table.
Interrupt Clear Shadow Register
Write 1h to clear interrupt bits.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 000Ch |
MCU_MCAN1_SS | 4056 000Ch |
MCAN0_SS | 0270 000Ch |
MCAN1_SS | 0271 000Ch |
MCAN2_SS | 0272 000Ch |
MCAN3_SS | 0273 000Ch |
MCAN4_SS | 0274 000Ch |
MCAN5_SS | 0275 000Ch |
MCAN6_SS | 0276 000Ch |
MCAN7_SS | 0277 000Ch |
MCAN8_SS | 0278 000Ch |
MCAN9_SS | 0279 000Ch |
MCAN10_SS | 027A 000Ch |
MCAN11_SS | 027B 000Ch |
MCAN12_SS | 027C 000Ch |
MCAN13_SS | 027D 000Ch |
MCAN14_SS | 0268 000Ch |
MCAN14_SS | 0269 000Ch |
MCAN16_SS | 026A 000Ch |
MCAN17_SS | 026B 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | W-0h | ||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | W | 0h | External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits. |
MCANSS_IRS is shown in Figure 12-2755 and described in Table 12-5234.
Return to Summary Table.
Interrupt Raw Status Register
Write 1h to set interrupt bits.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0010h |
MCU_MCAN1_SS | 4056 0010h |
MCAN0_SS | 0270 0010h |
MCAN1_SS | 0271 0010h |
MCAN2_SS | 0272 0010h |
MCAN3_SS | 0273 0010h |
MCAN4_SS | 0274 0010h |
MCAN5_SS | 0275 0010h |
MCAN6_SS | 0276 0010h |
MCAN7_SS | 0277 0010h |
MCAN8_SS | 0278 0010h |
MCAN9_SS | 0279 0010h |
MCAN10_SS | 027A 0010h |
MCAN11_SS | 027B 0010h |
MCAN12_SS | 027C 0010h |
MCAN13_SS | 027D 0010h |
MCAN14_SS | 0268 0010h |
MCAN14_SS | 0269 0010h |
MCAN16_SS | 026A 0010h |
MCAN17_SS | 026B 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | R/W1S | 0h | External Timestamp Counter Overflow Interrupt Status Write 1h to set bits. |
MCANSS_IECS is shown in Figure 12-2756 and described in Table 12-5236.
Return to Summary Table.
Interrupt Enable Clear Shadow Register
Write 1h to clear interrupt enable bits.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0014h |
MCU_MCAN1_SS | 4056 0014h |
MCAN0_SS | 0270 0014h |
MCAN1_SS | 0271 0014h |
MCAN2_SS | 0272 0014h |
MCAN3_SS | 0273 0014h |
MCAN4_SS | 0274 0014h |
MCAN5_SS | 0275 0014h |
MCAN6_SS | 0276 0014h |
MCAN7_SS | 0277 0014h |
MCAN8_SS | 0278 0014h |
MCAN9_SS | 0279 0014h |
MCAN10_SS | 027A 0014h |
MCAN11_SS | 027B 0014h |
MCAN12_SS | 027C 0014h |
MCAN13_SS | 027D 0014h |
MCAN14_SS | 0268 0014h |
MCAN14_SS | 0269 0014h |
MCAN16_SS | 026A 0014h |
MCAN17_SS | 026B 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | W1C-0h | ||||||
LEGEND: R = Read Only; W1C = Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | W1C | 0h | External Timestamp Counter Overflow Interrupt Write 1h to clear bits. |
MCANSS_IE is shown in Figure 12-2757 and described in Table 12-5238.
Return to Summary Table.
Interrupt Enable Register
Write 1h to set interrupt bits.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0018h |
MCU_MCAN1_SS | 4056 0018h |
MCAN0_SS | 0270 0018h |
MCAN1_SS | 0271 0018h |
MCAN2_SS | 0272 0018h |
MCAN3_SS | 0273 0018h |
MCAN4_SS | 0274 0018h |
MCAN5_SS | 0275 0018h |
MCAN6_SS | 0276 0018h |
MCAN7_SS | 0277 0018h |
MCAN8_SS | 0278 0018h |
MCAN9_SS | 0279 0018h |
MCAN10_SS | 027A 0018h |
MCAN11_SS | 027B 0018h |
MCAN12_SS | 027C 0018h |
MCAN13_SS | 027D 0018h |
MCAN14_SS | 0268 0018h |
MCAN14_SS | 0269 0018h |
MCAN16_SS | 026A 0018h |
MCAN17_SS | 026B 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | R/W1S | 0h | External Timestamp Counter Overflow Interrupt Write 1h to set bits. |
MCANSS_IES is shown in Figure 12-2758 and described in Table 12-5240.
Return to Summary Table.
Interrupt Enable Status Register
Read enabled interrupts.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 001Ch |
MCU_MCAN1_SS | 4056 001Ch |
MCAN0_SS | 0270 001Ch |
MCAN1_SS | 0271 001Ch |
MCAN2_SS | 0272 001Ch |
MCAN3_SS | 0273 001Ch |
MCAN4_SS | 0274 001Ch |
MCAN5_SS | 0275 001Ch |
MCAN6_SS | 0276 001Ch |
MCAN7_SS | 0277 001Ch |
MCAN8_SS | 0278 001Ch |
MCAN9_SS | 0279 001Ch |
MCAN10_SS | 027A 001Ch |
MCAN11_SS | 027B 001Ch |
MCAN12_SS | 027C 001Ch |
MCAN13_SS | 027D 001Ch |
MCAN14_SS | 0268 001Ch |
MCAN14_SS | 0269 001Ch |
MCAN16_SS | 026A 001Ch |
MCAN17_SS | 026B 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | R | 0h | External Timestamp Counter Overflow Interrupt |
MCANSS_EOI is shown in Figure 12-2759 and described in Table 12-5242.
Return to Summary Table.
End Of Interrupt (EOI) Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0020h |
MCU_MCAN1_SS | 4056 0020h |
MCAN0_SS | 0270 0020h |
MCAN1_SS | 0271 0020h |
MCAN2_SS | 0272 0020h |
MCAN3_SS | 0273 0020h |
MCAN4_SS | 0274 0020h |
MCAN5_SS | 0275 0020h |
MCAN6_SS | 0276 0020h |
MCAN7_SS | 0277 0020h |
MCAN8_SS | 0278 0020h |
MCAN9_SS | 0279 0020h |
MCAN10_SS | 027A 0020h |
MCAN11_SS | 027B 0020h |
MCAN12_SS | 027C 0020h |
MCAN13_SS | 027D 0020h |
MCAN14_SS | 0268 0020h |
MCAN14_SS | 0269 0020h |
MCAN16_SS | 026A 0020h |
MCAN17_SS | 026B 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EOI | W | 0h | End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1h will issue another pulse interrupt. 0h = EOI value for external timestamp interrupt 1h = EOI value for mcan[0] interrupt 2h = EOI value for mcan[1] interrupt |
MCANSS_EXT_TS_PRESCALER is shown in Figure 12-2760 and described in Table 12-5244.
Return to Summary Table.
External Timestamp Prescaler Register
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0024h |
MCU_MCAN1_SS | 4056 0024h |
MCAN0_SS | 0270 0024h |
MCAN1_SS | 0271 0024h |
MCAN2_SS | 0272 0024h |
MCAN3_SS | 0273 0024h |
MCAN4_SS | 0274 0024h |
MCAN5_SS | 0275 0024h |
MCAN6_SS | 0276 0024h |
MCAN7_SS | 0277 0024h |
MCAN8_SS | 0278 0024h |
MCAN9_SS | 0279 0024h |
MCAN10_SS | 027A 0024h |
MCAN11_SS | 027B 0024h |
MCAN12_SS | 027C 0024h |
MCAN13_SS | 027D 0024h |
MCAN14_SS | 0268 0024h |
MCAN14_SS | 0269 0024h |
MCAN16_SS | 026A 0024h |
MCAN17_SS | 026B 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRESCALER | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-0 | PRESCALER | R/W | 0h | External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h. |
MCANSS_EXT_TS_UNSERVICED_INTR_CNTR is shown in Figure 12-2761 and described in Table 12-5246.
Return to Summary Table.
External Timestamp Unserviced Interrupts Counter Register
Instance | Physical Address |
---|---|
MCU_MCAN0_SS | 4052 0028h |
MCU_MCAN1_SS | 4056 0028h |
MCAN0_SS | 0270 0028h |
MCAN1_SS | 0271 0028h |
MCAN2_SS | 0272 0028h |
MCAN3_SS | 0273 0028h |
MCAN4_SS | 0274 0028h |
MCAN5_SS | 0275 0028h |
MCAN6_SS | 0276 0028h |
MCAN7_SS | 0277 0028h |
MCAN8_SS | 0278 0028h |
MCAN9_SS | 0279 0028h |
MCAN10_SS | 027A 0028h |
MCAN11_SS | 027B 0028h |
MCAN12_SS | 027C 0028h |
MCAN13_SS | 027D 0028h |
MCAN14_SS | 0268 0028h |
MCAN14_SS | 0269 0028h |
MCAN16_SS | 026A 0028h |
MCAN17_SS | 026B 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_INTR_CNTR | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4-0 | EXT_TS_INTR_CNTR | R | 0h | Number of Unserviced Rollover Interrupts If > 1h an EOI write will issue another pulse interrupt. |