SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
MSMC protects both on-chip memory resources and data busses throughout the MSMC pipelines. A mixture of SEC/DED (single-error correct/double-error detect) hamming code and simple parity protect the on-chip memory resources.
MSMC aligns to the device architecture for system reliability using ECC aggregators to report detected parity and EDC faults both from scrubbing and functional access. The MSMC associated ECC aggregators are part of COMPUTE_CLUSTER0. For more information, see Section 6.1.2.3 Compute Cluster ECC Aggregators in Section 6.1Compute Cluster.
For information about the ECC aggregator functionality, see Section 12.7.4 ECC Aggregator.