SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Figure 11-87 shows the GPIOMUX_INTRTR0 integration.
Table 9-45 through Table 9-47 summarize the GPIOMUX_INTRTR0 integration.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
GPIOMUX_INTRTR0 | PSC0 | PD0 | LPSC0 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
GPIOMUX_INTRTR0 | GPIOMUX_INTRTR0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | Module functional and interface clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
GPIOMUX_INTRTR0 | GPIOMUX_INTRTR0_RST | MOD_G_RST | LPSC0 | Module hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
GPIOMUX_INTRTR0 | GPIOMUX_INTRTR0_OUTP_[63:0] | GIC500_SPI_IN_[447:392] | COMPUTE_CLUSTER0 | Module interrupt outputs [63:0] | Pulse |
GPIOMUX_INTRTR0_OUTP_[31:16] | R5FSS0_CORE0_INTR_IN_[191:176] | R5FSS0_CORE0 | |||
R5FSS0_CORE1_INTR_IN_[191:176] | R5FSS0_CORE1 | ||||
GPIOMUX_INTRTR0_OUTP_[15:0] | R5FSS0_CORE0_INTR_IN_[411:396] | R5FSS0_CORE0 | |||
R5FSS0_CORE1_INTR_IN_[411:396] | R5FSS0_CORE1 | ||||
GPIOMUX_INTRTR0_OUTP_[31:0] | MAIN2MCU_PLS_INTRTR0_IN_[94:63] | MAIN2MCU_PLS_INTRTR0 | |||
GPIOMUX_INTRTR0_OUTP_[7:0] | ESM0_PLS_IN_[639:632] | ESM0 |
Table 9-47 lists only the GPIOMUX_INTRTR0 interrupt outputs. The mapping of interrupt sources to GPIOMUX_INTRTR0 interrupt inputs is presented in Section 9.4.3.6.