SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-219 lists the memory-mapped registers for the UDMASS_UDMAP0_CFG. All register offset addresses not listed in Table 10-219 should be considered as reserved locations and the register contents should not be modified.
The UDMA-P Control /Status Registers region. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0000h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_UDMAP0_CFG Physical Address | MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG Physical Address |
---|---|---|---|---|
0h | UDMA_REVISION | Revision Register | 3115 0000h | 285C 0000h |
4h | UDMA_PERF_CTRL | Performance Control Register | 3115 0004h | 285C 0004h |
8h | UDMA_EMU_CTRL | Emulation Control Register | 3115 0008h | 285C 0008h |
10h | UDMA_PSIL_TO | PSI-L Proxy Timeout Register | 3115 0010h | 285C 0010h |
1Ch | UDMA_UTC_CTRL | External UTC Control Register | 3115 001Ch | 285C 001Ch |
20h | UDMA_CAP0 | Capabilities Register 0 | 3115 0020h | 285C 0020h |
24h | UDMA_CAP1 | Capabilities Register 1 | 3115 0024h | 285C 0024h |
28h | UDMA_CAP2 | Capabilities Register 2 | 3115 0028h | 285C 0028h |
2Ch | UDMA_CAP3 | Capabilities Register 3 | 3115 002Ch | 285C 002Ch |
40h | UDMA_PERF0 | mem0 Port Virtualization Tuning Register | 3115 0040h | 285C 0040h |
44h | UDMA_PERF1 | mem1 Port Virtualization Tuning Register | 3115 0044h | 285C 0044h |
48h | UDMA_PERF2 | memr Port Virtualization Tuning Register | 3115 0048h | 285C 0048h |
4Ch | UDMA_PERF3 | memw Port Virtualization Tuning Register | 3115 004Ch | 285C 004Ch |
78h | UDMA_DBGADDR | Debug Address Register | 3115 0078h | 285C 0078h |
7Ch | UDMA_DBGDATA | Debug Data Register | 3115 007Ch | 285C 007Ch |
80h | UDMA_RFLOWFWOES | Rx Flow ID Firewall Output Event Steering Register | 3115 0080h | 285C 0080h |
88h | UDMA_RFLOWFWSTAT | Rx Flow ID Firewall Status Register 0 | 3115 0088h | 285C 0088h |
UDMA_REVISION is shown in Figure 10-63 and described in Table 10-221.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0000h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R-4E5Ah | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-0h | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 4E5Ah | Module ID field |
15-11 | REVRTL | R | 0h | RTL revision |
10-8 | REVMAJ | R | 2h | Major |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | REVMIN | R | 0h | Minor |
UDMA_PERF_CTRL is shown in Figure 10-64 and described in Table 10-223.
Return to Summary Table.
The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0004h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-40h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TIMEOUT_CNT | R/W | 40h | This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1 (packet is to be preserved - no discard). If the Rx error handling bit in the flow table is cleared, this field will have no effect on the Rx operation. When this field is set to 0, the Rx engine will not force an Rx channel to wait after encountering a starvation event (the feature is disabled). When this field is set to a value other than 0, the Rx engine will force any channel whose associated flow had the Rx error handling bit asserted and which encounters starvation to wait for at least the specified # of clock cycles before coming into context again to check if entries have been added to the Free Queue. This is intended to control potentially debilitating effects on the Rx engine in the UDMA-P caused by scheduling channels which cannot perform work due to a lack of free descriptor/buffer resources. The exact # of clock cycles between scheduling attempts is not important and will not be exact. The only guarantee is that the # of cycles waited will be at least as large as the timeout_cnt. |
UDMA_EMU_CTRL is shown in Figure 10-65 and described in Table 10-225.
Return to Summary Table.
The emulation control register is used to control the behavior of the DMA when the emususp input is asserted.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0008h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | SOFT | R/W | 0h | Soft |
0 | FREE | R/W | 0h | Free |
UDMA_PSIL_TO is shown in Figure 10-66 and described in Table 10-227.
Return to Summary Table.
The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0010h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TOUT | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TOUT_CNT | |||||||
R/W-400h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOUT_CNT | |||||||
R/W-400h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | TOUT | R/W | 0h | Timeout occurred. When set indicates that a timeout has occurred on a config access |
30-16 | RESERVED | R/W | X | |
15-0 | TOUT_CNT | R/W | 400h | Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit |
UDMA_UTC_CTRL is shown in Figure 10-67 and described in Table 10-229.
Return to Summary Table.
The external UTC control register provides a mapping of logical to physical thread IDs .
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 001Ch |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | UTC_CHAN_START | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | UTC_CHAN_START | R/W | 0h | This field specifies the starting PSI-L thread number for the external UTC |
UDMA_CAP0 is shown in Figure 10-68 and described in Table 10-231.
Return to Summary Table.
The Capabilities Register 0 specifies which standard features this UDMA-P instance supports.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0020h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | GLOBAL_TRIG | LOCAL_TRIG | EOL | STATIC | |||
R-X | R-1h | R-0h | R-1h | R-1h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TYPE15 | TYPE14 | TYPE13 | TYPE12 | TYPE11 | TYPE10 | TYPE9 | TYPE8 |
R-1h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TYPE7 | TYPE6 | TYPE5 | TYPE4 | TYPE3 | TYPE2 | TYPE1 | TYPE0 |
R-0h | R-0h | R-0h | R-0h | R-1h | R-1h | R-1h | R-1h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | |
19 | GLOBAL_TRIG | R | 1h | Global triggers 0 and 1 are supported |
18 | LOCAL_TRIG | R | 0h | Dedicated local trigger is supported |
17 | EOL | R | 1h | EOL field is supported |
16 | STATIC | R | 1h | STATIC field is supported |
15 | TYPE15 | R | 1h | Type 15 TR is supported |
14 | TYPE14 | R | 0h | Type 14 TR is supported |
13 | TYPE13 | R | 0h | Type 13 TR is supported |
12 | TYPE12 | R | 0h | Type 12 TR is supported |
11 | TYPE11 | R | 0h | Type 11 TR is supported |
10 | TYPE10 | R | 0h | Type 10 TR is supported |
9 | TYPE9 | R | 0h | Type 9 TR is supported |
8 | TYPE8 | R | 0h | Type 8 TR is supported |
7 | TYPE7 | R | 0h | Type 7 TR is supported |
6 | TYPE6 | R | 0h | Type 6 TR is supported |
5 | TYPE5 | R | 0h | Type 5 TR is supported |
4 | TYPE4 | R | 0h | Type 4 TR is supported |
3 | TYPE3 | R | 1h | Type 3 TR is supported |
2 | TYPE2 | R | 1h | Type 2 TR is supported |
1 | TYPE1 | R | 1h | Type 1 TR is supported |
0 | TYPE0 | R | 1h | Type 0 TR is supported |
UDMA_CAP1 is shown in Figure 10-69 and described in Table 10-233.
Return to Summary Table.
The Capabilities Register 1 specifies which standard features this UDMA-P instance supports.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0024h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SECTR | DFMT | ELTYPE | AMODE | |||
R-X | R-0h | R-0h | R-0h | R-0h | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | X | |
3 | SECTR | R | 0h | Maximum second TR function that is supported |
2 | DFMT | R | 0h | Maximum data reformatting function that is supported |
1 | ELTYPE | R | 0h | Maximum element type value that is supported. |
0 | AMODE | R | 0h | The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE. |
UDMA_CAP2 is shown in Figure 10-70 and described in Table 10-235.
Return to Summary Table.
The Capabilities Register 2 specifies how many resources this UDMA-P instance supports.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0028h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RCHAN_CNT | ECHAN_CNT | TCHAN_CNT | ||||||||||||||||||||||||||||
R-X | R-X | R-X | R-X | ||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | X | |
26-18 | RCHAN_CNT | R | X | Rx internal channel count 3Ch in NAVSS030h in MCU_NAVSS0 |
17-9 | ECHAN_CNT | R | X | Tx external channel count 0h in NAVSS00h in MCU_NAVSS0 |
8-0 | TCHAN_CNT | R | X | Tx internal channel count 3Ch in NAVSS060h in MCU_NAVSS0 |
UDMA_CAP3 is shown in Figure 10-71 and described in Table 10-237.
Return to Summary Table.
The Capabilities Register 3 specifies how many resources this UDMA-P instance supports.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 002Ch |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCHAN_CNT | HCHAN_CNT | RFLOW_CNT | |||||||||||||||||||||||||||||
R-X | R-X | R-X | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | UCHAN_CNT | R | X | Tx ultra high capacity internal channel count 2h in NAVSS00h in MCU_NAVSS0 |
22-14 | HCHAN_CNT | R | X | Tx high capacity internal channel count 4h in NAVSS02 in MCU_NAVSS0 |
13-0 | RFLOW_CNT | R | X | Rx flow table entry count 96h in NAVSS060h in MCU_NAVSS0 |
UDMA_PERF0 is shown in Figure 10-72 and described in Table 10-239.
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This register provides thresholds for outstanding virtualized read/write commands from interface mem0
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0040h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | VRD_THRESH0 | ||||||||||||||
R/W-X | R/W-8h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VWR_THRESH0 | ||||||||||||||
R/W-X | R/W-8h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-16 | VRD_THRESH0 | R/W | 8h |
Virt read command
throttling threshold for mem0. |
15-8 | RESERVED | R/W | X | |
7-0 | VWR_THRESH0 | R/W | 8h |
Virt write command
throttling threshold for mem0. |
UDMA_PERF1 is shown in Figure 10-73 and described in Table 10-241.
Return to Summary Table.
This register provides thresholds for outstanding virtualized read/write commands from interface mem1
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0044h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | VRD_THRESH1 | ||||||||||||||
R/W-X | R/W-8h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VWR_THRESH1 | ||||||||||||||
R/W-X | R/W-8h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-16 | VRD_THRESH1 | R/W | 8h |
Virt read command
throttling threshold for mem1. |
15-8 | RESERVED | R/W | X | |
7-0 | VWR_THRESH1 | R/W | 8h |
Virt write command
throttling threshold for mem1. |
UDMA_PERF2 is shown in Figure 10-74 and described in Table 10-243.
Return to Summary Table.
This register provides thresholds for outstanding virtualized read commands from interface memr
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0048h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | VRD_THRESH2 | ||||||||||||||
R/W-X | R/W-10h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-16 | VRD_THRESH2 | R/W | 10h |
Virt read command
throttling threshold for memr. |
15-0 | RESERVED | R/W | X |
UDMA_PERF3 is shown in Figure 10-75 and described in Table 10-245.
Return to Summary Table.
This register provides thresholds for outstanding virtualized write commands from interface memw
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 004Ch |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VWR_THRESH3 | ||||||||||||||
R/W-X | R/W-10h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | VWR_THRESH3 | R/W | 10h |
Virt write command
throttling threshold for memw. |
UDMA_DBGADDR is shown in Figure 10-76 and described in Table 10-247.
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This register provides a writable address which allows debug information to be read from the Debug Data Register
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0078h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DBG_EN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DBG_UNIT | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG_ADDR | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | DBG_EN | R/W | 0h |
Debug enable |
30-16 | RESERVED | R/W | X | |
15-8 | DBG_UNIT | R/W | 0h |
Selects which unit to read debug information from |
7-0 | DBG_ADDR | R/W | 0h |
Selects offset within unit to access seperate debug registers |
UDMA_DBGDATA is shown in Figure 10-77 and described in Table 10-249.
Return to Summary Table.
This register provides read only debug data
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 007Ch |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 007Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG_DATA | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBG_DATA | R | 0h |
Provides debug
information from various internal units. |
UDMA_RFLOWFWOES is shown in Figure 10-78 and described in Table 10-251.
Return to Summary Table.
The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0080h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT_NUM | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | EVT_NUM | R/W | FFFFh | This is the global event number to be generated |
UDMA_RFLOWFWSTAT is shown in Figure 10-79 and described in Table 10-253.
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The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected until the pend bit is written back to 0
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG | 3115 0088h |
MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG | 285C 0088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PEND | RESERVED | FLOWID | |||||
R/W-0h | R/W-X | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FLOWID | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHANNEL | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHANNEL | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PEND | R/W | 0h | This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set, the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another exception to be captured. |
30 | RESERVED | R/W | X | |
29-16 | FLOWID | R/W | 0h | This is the flow ID that was received on the trapped packet |
15-9 | RESERVED | R/W | X | |
8-0 | CHANNEL | R/W | 0h | This is the channel number on which the trapped packet was received |