SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-275 lists the memory-mapped registers for the UDMASS_UDMAP0_CFG_RCHAN . All register offset addresses not listed in Table 10-275 should be considered as reserved locations and the register contents should not be modified.
The UDMA-P Rx Channel Configuration Registers region is accessed by setting the cdma_cfg_rsel signal to 3 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 0000h |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_UDMAP0_CFG_RCHAN Physical Address | MCU_NAVSS0_UDMASS_UDMAP0_RCHAN Physical Address |
---|---|---|---|---|
0h + formula | UDMA_RCFG_j | Rx Channel Configuration | 30C0 0000h + formula | 284C 0000h + formula |
14h + formula | UDMA_RCQ_j | Rx Channel Completion Queue | 30C0 0014h + formula | 284C 0014h + formula |
20h + formula | UDMA_ROES_j | Rx Channel Output Event Steering 0 | 30C0 0020h + formula | 284C 0020h + formula |
60h + formula | UDMA_REOES_j | Rx Channel Error Output Event Steering 0 | 30C0 0060h + formula | 284C 0060h + formula |
64h + formula | UDMA_RPRI_CTRL_j | Rx Channel Priority Control | 30C0 0064h + formula | 284C 0064h + formula |
68h + formula | UDMA_THREAD_j | Rx Channel Destination ThreadID Mapping | 30C0 0068h + formula | 284C 0068h + formula |
80h + formula | UDMA_RST_SCHED_j | Rx Channel Static Scheduler Config | 30C0 0080h + formula | 284C 0080h + formula |
F0h + formula | UDMA_RFLOW_RNG_j | Rx Channel Flow Range | 30C0 00F0h + formula | 284C 00F0h + formula |
UDMA_RCFG_j is shown in Figure 10-89 and described in Table 10-277.
Return to Summary Table.
The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0).
Offset = 0h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_RCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 0000h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PAUSE_ON_ERR | RESERVED | ATYPE | |||||
R/W-0h | R/W-X | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CHAN_TYPE | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IGNORE_SHORT | IGNORE_LONG | RESERVED | BURST_SIZE | RESERVED | |||
R/W-0h | R/W-0h | R/W-X | R/W-1h | R/W-X | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FETCH_SIZE | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PAUSE_ON_ERR | R/W | 0h | Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to investigate and un-pause the channel. |
30-26 | RESERVED | R/W | X | |
25-24 | ATYPE | R/W | 0h | This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate to physical transaction before they can be decoded 2 = Pointers are virtual addresses which require virtual to physical translation before they can be decoded. All transactions from this channel which are not destined to the Ring Accelerator will have the mem*_catype attribute set equal to the value given in this register field. Accesses to the RA will always use physical addresses. |
23-20 | RESERVED | R/W | X | |
19-16 | CHAN_TYPE | R/W | 0h | Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED 1 = RESERVED 2 = Channel performs packet oriented data transfers using pass by reference rings. Channels configured in this mode can only use Host and Monolithic descriptors and the pointers to those descriptors are passed from/to SW using rings in the Ring Accelerator. 3 = Channel performs packet oriented data transfers using pass by reference rings with single buffer packet mode enabled. Channels configured in this mode can only use Host descriptors and each descriptor will be processed as an independent packet (no buffer chaining). This is the only packet oriented mode that can be used with data sources that are infinite streams (no EOP) 4 - 9 = RESERVED 10 = Channel performs Third Party DMA control transfers using pass by reference rings. Channels configured in this mode can only use TR descriptors and the pointers to those descriptors are passed from/to SW using rings in the Ring Accelerator. 11 = Channel performs Third Party DMA control transfers using pass by value rings. Channels configured in this mode will directly pass individual Transfer Request/Transfer Response messages from/to SW using rings in the Ring Accelerator. 12 = Channel performs Third Party Block Copy DMA control transfers using pass by reference rings. Channels configured in this mode are linked to the same index Rx channel to form a bonded read/write channel 13 = Channel performs Third Party Block Copy DMA data transfers using pass by reference rings. Channels configured in this mode are linked to the same index Rx channel to form a bonded read/write channel 14 = Channel performs Third Party DMA data transfers using TRs provided via PSI-L (not supported in UDMA-P). 15 = Channel performs Third Party DMA data transfers using TRs provided via QDMA channel (not supported in UDMA-P) |
15 | IGNORE_SHORT | R/W | 0h | This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated as exceptions and handled appropriately. 1 = Short packets are ignored and the TR will continue to execute even if an EOP is encountered prematurely or the TR does not have EOP set. |
14 | IGNORE_LONG | R/W | 0h | This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as exceptions and handled appropriately. 1 = Long packets are ignored and the next TR will be fetched even if the current TR is marked or interpreted as EOP. |
13-12 | RESERVED | R/W | X | |
11-10 | BURST_SIZE | R/W | 1h | Specifies the nominal burst size and alignment for data
transfers on this channel. Receive Data fetches are not allowed to initiate unless sufficient accumulated data greater than or equal to the rx_burst_size value exists in the Rx Per Channel Buffer for that channel. Care must be taken to ensure that the nominal burst size field is not set larger than the implemented Rx Data Per Channel FIFO. Unless otherwise noted, it should be assumed that only HC/UHC channels can be programmed to use a burst size greater than 64 bytes. |
9-7 | RESERVED | R/W | X | |
6-0 | FETCH_SIZE | R/W | 0h | Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type. |
UDMA_RCQ_j is shown in Figure 10-90 and described in Table 10-279.
Return to Summary Table.
The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0).
Offset = 14h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_RCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 0014h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 0014h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXCQ_QNUM | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RXCQ_QNUM | R/W | 0h | Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to. |
UDMA_ROES_j is shown in Figure 10-91 and described in Table 10-281.
Return to Summary Table.
The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the corresponding register will be generated. This register is provided in order to allow security SW to lock down which events in the global space any given channel/ thread is allowed to generate.
Offset = 20h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_RCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 0020h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 0020h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT_NUM | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | EVT_NUM | R/W | FFFFh | This is the global event number to be generated |
UDMA_REOES_j is shown in Figure 10-92 and described in Table 10-283.
Return to Summary Table.
The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the corresponding register will be generated. This register is provided in order to allow security SW to lock down which events in the global space any given channel/ thread is allowed to generate.
Offset = 60h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_RCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 0060h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT_NUM | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | EVT_NUM | R/W | FFFFh | This is the global event number to be generated |
UDMA_RPRI_CTRL_j is shown in Figure 10-93 and described in Table 10-285.
Return to Summary Table.
The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface.
Offset = 64h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_RCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 0064h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 0064h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRIORITY | RESERVED | QOS | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ORDERID | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | PRIORITY | R/W | 0h | Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel. |
27-19 | RESERVED | R/W | X | |
18-16 | QOS | R/W | 0h | Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel. |
15-4 | RESERVED | R/W | X | |
3-0 | ORDERID | R/W | 0h | Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel. |
UDMA_THREAD_j is shown in Figure 10-94 and described in Table 10-287.
Return to Summary Table.
The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register.
Offset = 68h + (j * 100h); where j = 0h to 95h
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_RCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 0068h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 0068h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ID | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | ID | R/W | 0h | Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel. |
UDMA_RST_SCHED_j is shown in Figure 10-95 and described in Table 10-289.
Return to Summary Table.
The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this register are as follows:
Offset = 80h + (j * 100h); where j = 0h to 95h
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_RCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 0080h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 0080h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRIORITY | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | PRIORITY | R/W | 0h | Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority 3 = Low priority Arbitration between bins is performed in a strict priority fashion. High priority channels will always be serviced first. If no high priority channels are requesting then all medium-high priority channels will be serviced next. If no high priority or medium-high priority channels are requesting then all medium-low priority channels will be serviced next. When no other channels are requesting, the low priority channels will be serviced. All channels within a given bin are serviced in a round robin order. Only channels which are enabled and which have sufficient free space in their Per Channel FIFO will be included in the round robin arbitration. |
UDMA_RFLOW_RNG_j is shown in Figure 10-96 and described in Table 10-291.
Return to Summary Table.
The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel.
Offset = F0h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_RCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN | 30C0 00F0h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_RCHAN | 284C 00F0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | FLOWID_CNT | ||||||
R/W-X | R/W-4000h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FLOWID_CNT | |||||||
R/W-4000h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FLOWID_START | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLOWID_START | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-16 | FLOWID_CNT | R/W | 4000h | Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.. |
15-14 | RESERVED | R/W | X | |
13-0 | FLOWID_START | R/W | 0h | Rx Starting Flow ID: Beyond the default flow ID, each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.. |