SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes the GTC integration in the device, including information about clocks, resets, and hardware requests.
Figure 12-2824 shows the GTC integration.
Table 12-5393 through Table 12-5395 summarize the GTC integration.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
GTC0 | PSC0 | PD0 | LPSC9 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
GTC0 | GTC_CLK | MAIN_PLL3_HSDIV1_CLKOUT (default) | PLL3_HSDIV1 | GTC0 functional and interface clock. Source clock selection is done through a mux which is controlled via CTRLMMR_GTC_CLKSEL[2-0] CLK_SEL register bit field (see Figure 12-2824). |
MAIN_PLL0_HSDIV6_CLKOUT | PLL0_HSDIV6 | |||
MCU_CPTS_RFT_CLK | I/O pin | |||
CPTS_RFT_CLK | I/O pin | |||
MCU_EXT_REFCLK0 | I/O pin | |||
EXT_REFCLK1 | I/O pin | |||
SERDES0_IP2_LN0_TXMCLK | SERDES0, lane 0 | |||
SERDES0_IP2_LN1_TXMCLK | SERDES0, lane 1 | |||
SERDES0_IP2_LN2_TXMCLK | SERDES0, lane 2 | |||
SERDES0_IP2_LN3_TXMCLK | SERDES0, lane 3 | |||
MCU_PLL2_HSDIV1_CLKOUT | MCU_PLL2_HSDIV1 | |||
SYSCLK0 | PLLCTRL0 | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
GTC0 | GTC_POR_RST | MOD_POR_RST | LPSC9 | GTC0 power-on-reset (affects GTC0 counter logic) |
GTC_RST | MOD_G_RST | LPSC9 | GTC0 MMR reset (affects GTC0 registers) |
Time Sync Events | |||||
Module Instance | Module Sync Output | Destination Sync Input | Destination | Description | Type |
GTC0 | GTC0_GTC_PUSH_EVENT_0 | TIMESYNC_INTRTR0_IN_1 | TIMESYNC_INTRTR0 | GTC hardware push event | Pulse |
GTC hardware push event is further described in Section 12.6.1.3.4, GTC Push Event Generation.