SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are ten UART modules integrated in the device MAIN domain - UART0, UART1, UART2, UART3, UART4, UART5, UART6, UART7, UART8, and UART9. Figure 12-406 shows the integration of UART[0-9].
Table 12-738 through Table 12-740 summarize the integration of UART[0-9] in the device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
UART0 | PSC0 | PD2 | LPSC54 | CBASS0 |
UART1 | PSC0 | PD2 | LPSC54 | CBASS0 |
UART2 | PSC0 | PD2 | LPSC55 | CBASS0 |
UART3 | PSC0 | PD2 | LPSC55 | CBASS0 |
UART4 | PSC0 | PD2 | LPSC56 | CBASS0 |
UART5 | PSC0 | PD2 | LPSC56 | CBASS0 |
UART6 | PSC0 | PD2 | LPSC56 | CBASS0 |
UART7 | PSC0 | PD2 | LPSC56 | CBASS0 |
UART8 | PSC0 | PD2 | LPSC56 | CBASS0 |
UART9 | PSC0 | PD2 | LPSC55 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
UART0 | UART0_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART0 interface clock |
UART0_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART0 functional clock | |
UART1 | UART1_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART1 interface clock |
UART1_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART1 functional clock | |
UART2 | UART2_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART2 interface clock |
UART2_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART2 functional clock | |
UART3 | UART3_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART3 interface clock |
UART3_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART3 functional clock | |
UART4 | UART4_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART4 interface clock |
UART4_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART4 functional clock | |
UART5 | UART5_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART5 interface clock |
UART5_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART5 functional clock | |
UART6 | UART6_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART6 interface clock |
UART6_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART6 functional clock | |
UART7 | UART7_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART7 interface clock |
UART7_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART7 functional clock | |
UART8 | UART8_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART8 interface clock |
UART8_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART8 functional clock | |
UART9 | UART9_CLK | MAIN_SYSCLK0/4 | PLLCTRL0 | UART9 interface clock |
UART9_FCLK | MAIN_PLL1_HSDIV0_CLKOUT/DIV(1) | PLL1 | UART9 functional clock | |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
UART0 | UART0_RST | MOD_G_RST | LPSC54 | UART0 reset |
UART1 | UART1_RST | MOD_G_RST | LPSC54 | UART1 reset |
UART2 | UART2_RST | MOD_G_RST | LPSC55 | UART2 reset |
UART3 | UART3_RST | MOD_G_RST | LPSC55 | UART3 reset |
UART4 | UART4_RST | MOD_G_RST | LPSC56 | UART4 reset |
UART5 | UART5_RST | MOD_G_RST | LPSC56 | UART5 reset |
UART6 | UART6_RST | MOD_G_RST | LPSC56 | UART6 reset |
UART7 | UART7_RST | MOD_G_RST | LPSC56 | UART7 reset |
UART8 | UART8_RST | MOD_G_RST | LPSC56 | UART8 reset |
UART9 | UART9_RST | MOD_G_RST | LPSC56 | UART9 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
UART0 | UART0_USART_IRQ_0 | GIC500_SPI_IN_224 | COMPUTE_CLUSTER0 | UART0 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_96 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_158 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_158 | R5FSS0_CORE1 | ||||
UART1 | UART1_USART_IRQ_0 | GIC500_SPI_IN_225 | COMPUTE_CLUSTER0 | UART1 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_97 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_159 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_159 | R5FSS0_CORE1 | ||||
UART2 | UART2_USART_IRQ_0 | GIC500_SPI_IN_226 | COMPUTE_CLUSTER0 | UART2 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_98 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_160 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_160 | R5FSS0_CORE1 | ||||
UART3 | UART3_USART_IRQ_0 | GIC500_SPI_IN_227 | COMPUTE_CLUSTER0 | UART3 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_99 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_261 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_261 | R5FSS0_CORE1 | ||||
UART4 | UART4_USART_IRQ_0 | GIC500_SPI_IN_228 | COMPUTE_CLUSTER0 | UART4 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_100 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_262 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_262 | R5FSS0_CORE1 | ||||
UART5 | UART5_USART_IRQ_0 | GIC500_SPI_IN_229 | COMPUTE_CLUSTER0 | UART5 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_101 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_263 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_263 | R5FSS0_CORE1 | ||||
UART6 | UART6_USART_IRQ_0 | GIC500_SPI_IN_230 | COMPUTE_CLUSTER0 | UART6 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_102 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_264 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_264 | R5FSS0_CORE1 | ||||
UART7 | UART7_USART_IRQ_0 | GIC500_SPI_IN_231 | COMPUTE_CLUSTER0 | UART7 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_103 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_265 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_265 | R5FSS0_CORE1 | ||||
UART8 | UART8_USART_IRQ_0 | GIC500_SPI_IN_280 | COMPUTE_CLUSTER0 | UART8 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_104 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_266 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_266 | R5FSS0_CORE1 | ||||
UART9 | UART9_USART_IRQ_0 | GIC500_SPI_IN_281 | COMPUTE_CLUSTER0 | UART9 interrupt request | Level |
MAIN2MCU_LVL_INTRTR0_IN_105 | MAIN2MCU_LVL_INTRTR0 | ||||
R5FSS0_CORE0_INTR_IN_267 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_267 | R5FSS0_CORE1 | ||||
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
UART0 | USART0_DMA0 | USART0_TX | PDMA_USART_G0 | UART0 transmit request line | Level |
USART0_DMA1 | USART0_RX | PDMA_USART_G0 | UART0 receive request line | Level | |
UART1 | USART1_DMA0 | USART1_TX | PDMA_USART_G0 | UART1 transmit request line | Level |
USART1_DMA1 | USART1_RX | PDMA_USART_G0 | UART1 receive request line | Level | |
UART2 | USART2_DMA0 | USART2_TX | PDMA_USART_G1 | UART2 transmit request line | Level |
USART2_DMA1 | USART2_RX | PDMA_USART_G1 | UART2 receive request line | Level | |
UART3 | USART3_DMA0 | USART3_TX | PDMA_USART_G1 | UART3 transmit request line | Level |
USART3_DMA1 | USART3_RX | PDMA_USART_G1 | UART3 receive request line | Level | |
UART4 | USART4_DMA0 | USART4_TX | PDMA_USART_G2 | UART4 transmit request line | Level |
USART4_DMA1 | USART4_RX | PDMA_USART_G2 | UART4 receive request line | Level | |
UART5 | USART5_DMA0 | USART5_TX | PDMA_USART_G2 | UART5 transmit request line | Level |
USART5_DMA1 | USART5_RX | PDMA_USART_G2 | UART5 receive request line | Level | |
UART6 | USART6_DMA0 | USART6_TX | PDMA_USART_G2 | UART6 transmit request line | Level |
USART6_DMA1 | USART6_RX | PDMA_USART_G2 | UART6 receive request line | Level | |
UART7 | USART7_DMA0 | USART7_TX | PDMA_USART_G2 | UART7 transmit request line | Level |
USART7_DMA1 | USART7_RX | PDMA_USART_G2 | UART7 receive request line | Level | |
UART8 | USART8_DMA0 | USART8_TX | PDMA_USART_G2 | UART8 transmit request line | Level |
USART8_DMA1 | USART8_RX | PDMA_USART_G2 | UART8 receive request line | Level | |
UART9 | USART9_DMA0 | USART9_TX | PDMA_USART_G2 | UART9 transmit request line | Level |
USART9_DMA1 | USART9_RX | PDMA_USART_G2 | UART9 receive request line | Level |