SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The information on configuration, Provisional ID, BCR and DCR of each device connected to the I3C bus is stored by the I3C master in a set of retaining registers divided into Device ID sections associated with each device. Application host take any action to guarantee maintaining this information anytime the bus topology changes.
The retaining register space is divided to up to 12 sections (depending on selected configuration), from I3C_DEV_ID0 to I3C_DEV_ID11. Each containing three 32-bit registers to hold whole necessary information on I3C devices connected to the bus (e.g. hot-join device is attached, some of DA are reset to new value, etc.).
The AMBA APB interface address space for retaining registers starts at 0x080 and is divided into 12 quadruplets.
The map organization is presented in Table 12-333 below.
Register | Address | Contents |
---|---|---|
I3C_DEV_ID0_RR0 | 0x080 | Configuration register which stores settings for device that needs to be programmed by application host. |
I3C_DEV_ID0_RR1 | 0x084 | Register stores MSB of Provisional ID (1) |
I3C_DEV_ID0_RR2 | 0x088 | Register stores LSB of Provisional ID, DCR, BCR (1) |
I3C_DEV_ID1_RR0 | 0x090 | Configuration register which stores settings for device that needs to be programmed by application host. |
I3C_DEV_ID1_RR1 | 0x094 | Register stores MSB of Provisional ID (1) |
I3C_DEV_ID1_RR2 | 0x098 | Register stores LSB of Provisional ID, DCR, BCR (1) |
I3C_DEV_ID2_RR0 | 0x0A0 | Configuration register which stores settings for device that needs to be programmed by application host. |
I3C_DEV_ID2_RR1 | 0x0A4 | Register stores MSB of Provisional ID (1) |
I3C_DEV_ID2_RR2 | 0x0A8 | Register stores LSB of Provisional ID, DCR, BCR (1) |
... | ... | ... |
I3C_DEV_ID11_RR0 | 0x130 | Configuration register which stores settings for device that needs to be programmed by application host. |
I3C_DEV_ID11_RR1 | 0x134 | Register stores MSB of Provisional ID (1) |
I3C_DEV_ID11_RR2 | 0x138 | Register stores LSB of Provisional ID, DCR, BCR (1) |
A special device control register (I3C_DEVS_CTRL) is provided to store information on devices currently connected to the bus. Each DeviceID section contains configuration register and two registers holding Provisional ID, BCR and DCR of the corresponding device. The active state bit is set automatically by hardware after Dynamic Address is assigned to given device. Firmware shall set it for devices enumerated with SETDASA CCC command after their Retaining Registers are configured and before any transaction to these devices is initiated.
The clearing bits need to be set by firmware every time RSTDAA CCC is send to corresponding devices (firmware should clear all of them for broadcast RSTDAA) or controller constantly receives NACK response and application recognizes device as no longer connected to the bus.