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数据转换器
模数转换器 (ADC)
高速 ADC (≥10 MSPS)

ADS6425

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四通道、12 位、125MSPS 模数转换器 (ADC)

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ADS6425

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产品详情

Sample rate (max) (Msps) 125 Resolution (Bits) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1650 Architecture Pipeline SNR (dB) 70.9 ENOB (Bits) 11.4 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1650 Architecture Pipeline SNR (dB) 70.9 ENOB (Bits) 11.4 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 1.65-W Total Power
  • Simultaneous Sample and Hold
  • 70.3 dBFS SNR at Fin = 50 MHz
  • 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
  • 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp Differential
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64 QFN Package (9 mm × 9 mm)
  • Pin Compatible 14-Bit Family (ADS644X - SLAS532)
  • APPLICATIONS
    • Base-Station IF Receivers
    • Diversity Receivers
    • Medical Imaging
    • Test Equipment
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 1.65-W Total Power
  • Simultaneous Sample and Hold
  • 70.3 dBFS SNR at Fin = 50 MHz
  • 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
  • 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp Differential
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64 QFN Package (9 mm × 9 mm)
  • Pin Compatible 14-Bit Family (ADS644X - SLAS532)
  • APPLICATIONS
    • Base-Station IF Receivers
    • Diversity Receivers
    • Medical Imaging
    • Test Equipment

The ADS6425 is a high performance 12-bit, 125-MSPS quad channel ADC. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes a 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC's data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS6425 also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes, and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS6425 has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (-40°C to 85°C).

The ADS6425 is a high performance 12-bit, 125-MSPS quad channel ADC. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes a 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC's data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS6425 also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes, and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS6425 has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (-40°C to 85°C).

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Quad Channel 12-Bit 125-MSPS ADC W/Serial LVDS Interface 数据表 (Rev. B) 2009年 6月 10日
应用手册 QFN 和 SON PCB 连接 (Rev. C) PDF | HTML 英语版 (Rev.C) PDF | HTML 2024年 1月 5日
应用手册 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
应用手册 Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
应用手册 Band-Pass Filter Design Techniques for High-Speed ADCs 2012年 2月 27日
应用手册 Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010年 9月 10日
应用手册 Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009年 4月 28日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 模数规格和性能特性术语表 (Rev. A) 最新英语版本 (Rev.B) 2008年 10月 16日
应用手册 高速数据转换 英语版 2008年 10月 16日
应用手册 CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
用户指南 ADS6245EVM and Lattice ECP2/M Interface Demo User Guide 2008年 1月 14日
应用手册 QFN Layout Guidelines 2006年 7月 28日

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