ADS62P43

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双通道、14 位、80MSPS 模数转换器 (ADC)

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数据表

document-pdfAcrobat DUAL CHANNEL 14-BITS 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS 数据表 (Rev. C) (英语)

用户指南

document-pdfAcrobat
Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) (英语)

ADS62P43

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数据表

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产品详情

Sample rate (max) (Msps)

80

Resolution (Bits)

14

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

450

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

587

Architecture

Pipeline

SNR (dB)

74.8

ENOB (Bits)

12

SFDR (dB)

93

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

80

Resolution (Bits)

14

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

450

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

587

Architecture

Pipeline

SNR (dB)

74.8

ENOB (Bits)

12

SFDR (dB)

93

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Maximum Sample Rate: 125 MSPS
14-Bit Resolution with No Missing Codes
95 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine Gain
up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block with:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable 24-Tap Low-/High-/
  Band-Pass Filters
Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
Amplitude Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference; Supports External Reference also
64-QFN Package (9mm × 9mm)
Pin Compatible 12-Bit Family (ADS62P2X)

Maximum Sample Rate: 125 MSPS
14-Bit Resolution with No Missing Codes
95 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine Gain
up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block with:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable 24-Tap Low-/High-/
  Band-Pass Filters
Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
Amplitude Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference; Supports External Reference also
64-QFN Package (9mm × 9mm)
Pin Compatible 12-Bit Family (ADS62P2X)

ADS62P4X is a dual channel 14-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P4X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P4X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62P4X is a dual channel 14-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P4X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P4X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

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顶层文档	类型	标题	日期
*	数据表	DUAL CHANNEL 14-BITS 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS 数据表 (Rev. C)	2012-2-9
*	用户指南	Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)	2012-7-10
	应用手册	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	2015-5-22
	应用手册	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	2013-7-19
	用户指南	TSW4200 Demonstration Kit User's Guide (Rev. C)	2012-10-31
	应用手册	Band-Pass Filter Design Techniques for High-Speed ADCs	2012-2-27
	应用手册	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	2010-9-10
	应用手册	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	2009-4-28
	用户指南	ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A)	2009-4-2
	应用手册	CDCE62005 as Clock Solution for High-Speed ADCs	2008-9-4
	应用手册	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	2008-6-8
	应用手册	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2008-6-2
	应用手册	QFN Layout Guidelines	2006-7-28

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用户可以向 DATACONVERTERPRO-SW 提供自定义图形以加载到 TI DAC。支持从 ADC 捕获导出 (...)

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