产品详细信息

Sample rate (Max) (MSPS) 40 Resolution (Bits) 12 Number of input channels 4 Interface type Parallel LVDS Analog input BW (MHz) 300 Features Low Power Rating Catalog Input range (Vp-p) 1 Power consumption (Typ) (mW) 607 Architecture Pipeline SNR (dB) 70.5 ENOB (Bits) 11.3 SFDR (dB) 87 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 40 Resolution (Bits) 12 Number of input channels 4 Interface type Parallel LVDS Analog input BW (MHz) 300 Features Low Power Rating Catalog Input range (Vp-p) 1 Power consumption (Typ) (mW) 607 Architecture Pipeline SNR (dB) 70.5 ENOB (Bits) 11.3 SFDR (dB) 87 Operating temperature range (C) -40 to 85 Input buffer No
HTQFP (PAP) 64 100 mm² 10 x 10
  • Maximum Sample Rate: 40MSPS
  • 12-Bit Resolution
  • No Missing Codes
  • Total Power Dissipation:
    Internal Reference: 584mW
    External Reference: 518mW
  • CMOS Technology
  • Simultaneous Sample-and-Hold
  • 70.5dBFS SNR at 10MHz IF
  • 3.3V Digital/Analog Supply
  • Serialized LVDS Outputs
  • Integrated Frame and Bit Patterns
  • Option to Double LVDS Clock Output Currents
  • Four Current Modes for LVDS
  • Pin- and Format-Compatible Family
  • HTQFP-64 PowerPAD Package
  • APPLICATIONS
    • Portable Ultrasound Systems
    • Tape Drives
    • Test Equipment
    • Optical Networking
    • Communications

PowerPAD Is a trademark of Texas Instruments
All other trademarks are the property of their respective owners

  • Maximum Sample Rate: 40MSPS
  • 12-Bit Resolution
  • No Missing Codes
  • Total Power Dissipation:
    Internal Reference: 584mW
    External Reference: 518mW
  • CMOS Technology
  • Simultaneous Sample-and-Hold
  • 70.5dBFS SNR at 10MHz IF
  • 3.3V Digital/Analog Supply
  • Serialized LVDS Outputs
  • Integrated Frame and Bit Patterns
  • Option to Double LVDS Clock Output Currents
  • Four Current Modes for LVDS
  • Pin- and Format-Compatible Family
  • HTQFP-64 PowerPAD Package
  • APPLICATIONS
    • Portable Ultrasound Systems
    • Tape Drives
    • Test Equipment
    • Optical Networking
    • Communications

PowerPAD Is a trademark of Texas Instruments
All other trademarks are the property of their respective owners

The ADS5240 is a high-performance, 40MSPS, 4-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size.

An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the four data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock.

The ADS5240 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode.

The device is available in an HTQFP-64 PowerPAD package and is specified over a -40°C to +85°C operating range.

The ADS5240 is a high-performance, 40MSPS, 4-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size.

An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the four data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock.

The ADS5240 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode.

The device is available in an HTQFP-64 PowerPAD package and is specified over a -40°C to +85°C operating range.

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技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface 数据表 (Rev. E) 2009年 1月 6日
技术文章 Keys to quick success using high-speed data converters 2020年 10月 13日
技术文章 How to achieve fast frequency hopping 2019年 3月 3日
技术文章 RF sampling: Learning more about latency 2017年 2月 9日
技术文章 Why phase noise matters in RF sampling converters 2016年 11月 28日
应用手册 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
应用手册 Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
应用手册 Driving High Speed A/D Converters (Rev. A) 2010年 9月 10日
应用手册 Smart Selection of ADC/DAC enables better design of Software Defined Radio (SDR) 2009年 4月 28日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 模数规格和性能特性术语表 (Rev. A) 下载最新的英文版本 (Rev.B) 2008年 10月 16日
应用手册 高速数据转换 下载英文版本 2008年 10月 16日
应用手册 CDCE62005 Application Report 2008年 9月 4日
应用手册 CDCE72010 as clocking solution for High Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
用户指南 ADS5240/5242 EVM User's Guide 2005年 10月 20日
应用手册 Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x 2005年 2月 23日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

仿真模型

ADS5240 IBIS Model

SBAM003.ZIP (19 KB) - IBIS Model
仿真工具

PSPICE-FOR-TI — PSPICE® for TI design and simulation tool

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入门

  1. 申请使用 PSPICE-FOR-TI 仿真器
  2. 下载并安装
  3. 观看有关仿真入门的培训
计算工具

ADC-HARMONIC-CALC — 模数转换器 (ADC) 谐波计算器

    ADC 谐波计算工具是基于 excel 的计算器,用于确定当模数转换器中出现奈奎斯特混叠后高次谐波的频率空间的位置。

    如果给定 ADC 采样速率和有用信号的范围,该计算器可以确定第 2 至第 9 谐波是否会返送到有用信号的频带中。图表以图形方式显示了在出现奈奎斯特混叠后基本信号以及第 2 至第 9 谐波的位置。

计算工具

JITTER-SNR-CALC — 用于 ADC 的抖动和 SNR 计算器

JITTER-SNR-CALC 可用于根据输入频率和时钟抖动来计算 ADC 的理论信噪比 (SNR) 性能。
封装 引脚 下载
HTQFP (PAP) 64 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

视频