ADS4146

正在供货

14 位、160MSPS 模数转换器 (ADC)

立即订购

数据表

document-pdfAcrobat 12-/14-Bit, 160/250MSPS, Ultralow-Power ADC 数据表 (Rev. G) (英语)

用户指南

document-pdfAcrobat
Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) (英语)

ADS4146

正在供货

数据表

立即订购

产品详情

Sample rate (max) (Msps)

160

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

800

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

200

Architecture

Pipeline

SNR (dB)

72.2

ENOB (Bits)

11.5

SFDR (dB)

88

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

160

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

800

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

200

Architecture

Pipeline

SNR (dB)

72.2

ENOB (Bits)

11.5

SFDR (dB)

88

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGZ)

48

49 mm² (7 mm × 7 mm)

Maximum Sample Rate: 250MSPS
Ultralow Power with 1.8V Single Supply:
- 201mW Total Power at 160MSPS
- 265mW Total Power at 250MSPS
High Dynamic Performance:
- SNR: 70.6dBFS at 170MHz
- SFDR: 84dBc at 170MHz
Dynamic Power Scaling with Sample Rate
Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100Ω Termination
  - 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude Down To 200mV_PP
Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

Maximum Sample Rate: 250MSPS
Ultralow Power with 1.8V Single Supply:
- 201mW Total Power at 160MSPS
- 265mW Total Power at 250MSPS
High Dynamic Performance:
- SNR: 70.6dBFS at 170MHz
- SFDR: 84dBc at 170MHz
Dynamic Power Scaling with Sample Rate
Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100Ω Termination
  - 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude Down To 200mV_PP
Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

The ADS412x/4x are a family of 12-bit/14-bit analog-to-digital converters (ADCs) with sampling rates up to 250MSPS. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x/4x have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x/4x are available in a compact QFN-48 package and are specified over the industrial temperature range (–40°C to +85°C)

The ADS412x/4x are a family of 12-bit/14-bit analog-to-digital converters (ADCs) with sampling rates up to 250MSPS. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x/4x have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x/4x are available in a compact QFN-48 package and are specified over the industrial temperature range (–40°C to +85°C)

filter

查找其他高速 ADC (≥10 MSPS)

下载观看带字幕的视频视频

您可能感兴趣的相似产品

open-in-new

比较替代产品

功能与比较器件相同且具有相同引脚。

ADS4126

正在供货

12 位、160MSPS 模数转换器 (ADC) This product is a lower priced, pin-to-pin 12-bit ADC.

技术文档

未找到结果。请清除搜索并重试。

查看全部 13

顶层文档	类型	标题	日期
*	数据表	12-/14-Bit, 160/250MSPS, Ultralow-Power ADC 数据表 (Rev. G)	2011-1-20
*	用户指南	Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)	2012-7-10
	应用手册	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	2015-5-22
	应用手册	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	2013-7-19
	应用手册	Band-Pass Filter Design Techniques for High-Speed ADCs	2012-2-27
	应用手册	High-Speed, Analog-to-Digital Converter Basics	2012-1-11
	应用手册	Power Supply Design for the ADS41xx (Rev. A)	2011-12-29
	应用手册	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	2010-9-10
	应用手册	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	2009-4-28
	应用手册	CDCE62005 as Clock Solution for High-Speed ADCs	2008-9-4
	应用手册	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	2008-6-8
	应用手册	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2008-6-2
	应用手册	QFN Layout Guidelines	2006-7-28

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估模块 (EVM) 用 GUI

DATACONVERTERPRO-SW — 高速数据转换器专业 GUI 安装程序，v5.31

该高速数据转换器专业版 GUI 是一款 PC（与 Windows® XP/7/10 兼容）程序，旨在帮助评估大多数 TI 高速数据转换器 [模数转换器 (ADC) 和数模转换器 (DAC)] 和模拟前端 (AFE) 平台。DATACONVERTERPRO-SW 支持整个 TSW14xxx 系列的数据采集和图形生成卡，为分析时域和频域中的数据转换器提供了快速强大的解决方案以及单音、多音和调制信号支持。此 GUI 还兼容用于快速合成单音、多音和调制信号的 TI 图形生成 GUI。

用户可以向 DATACONVERTERPRO-SW 提供自定义图形以加载到 TI DAC。支持从 ADC 捕获导出 (...)

支持的产品和硬件

下载选项

评估模块 (EVM) 用 GUI