ADS61B23
- Maximum Sample Rate: 80 MSPS
- 12-bit Resolution with No Missing Codes
- Buffered Analog Inputs with
- Very Low Input Capacitance (< 2 pF)
- High DC Resistance (5 k
)
- 82 dBc SFDR and 70 dBFS SNR
(-1 BFS or 1.8 Vpp input) - 85 dBc SFDR (-6 dBFS or 1 Vpp input)
- 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR and SFDR Trade-Off
- Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
- Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
- Clock Duty Cycle Stabilizer
- Internal Reference with Support for External Reference
- External Decoupling Eliminated for References
- Programmable Output Clock Position and Drive Strength to Ease Data Capture
- 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
- 32-pin QFN Package (5 mm × 5 mm)
- Pin Compatible 12-Bit Family (ADS612X)
- Temperature range -40°C to 85°C
- APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.
ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability.
The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so the device starts in the desired state after power-up.
ADS61B23 includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 12Bits 80MSPS ADC with Buffered Analog Inputs 数据表 | 2008-2-7 | |||
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015-5-22 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013-7-19 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008-9-4 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 | ||||
| 应用手册 | QFN Layout Guidelines | 2006-7-28 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
SBAC120 — TIGAR Support Files
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
模拟工程师计算器旨在加快模拟电路设计工程师经常运用的许多重复性计算。该基于 PC 的工具提供图形界面，其中显示各种常见计算列表，从使用反馈电阻器设置运算放大器增益到选择合适的电路设计元件，以稳定模数转换器 (ADC) 驱动器缓冲器电路。
除了可用作独立工具之外，该计算器还能很好地与模拟工程师口袋参考中所述的概念配合使用。
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
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