双通道、16 位、500MSPS、1x-16x 内插数模转换器 (DAC)

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参数

Resolution (Bits) 16 Number of DAC channels (#) 2 Interface type Parallel CMOS Sample/update rate (MSPS) 500 Features High Performance Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (Typ) (mW) 445 SFDR (dB) 89 Architecture Current Sink Operating temperature range (C) -40 to 85 Reference type Int open-in-new 查找其它 高速 DACs (>10MSPS)

封装|引脚|尺寸

HTQFP (PZP) 100 256 mm² 16 x 16 open-in-new 查找其它 高速 DACs (>10MSPS)

特性

  • 500-MSPS Maximum-Update-Rate DAC
  • WCDMA ACPR
    • 1 Carrier: 76 dB Centered at 30.72-MHz IF, 245.76 MSPS
    • 1 Carrier: 73 dB Centered at 61.44-MHz IF, 245.76 MSPS
    • 2 Carrier: 72 dB Centered at 30.72-MHz IF, 245.76 MSPS
    • 4 Carrier: 64 dB Centered at 92.16-MHz IF, 491.52 MSPS
  • Selectable 2×, 4×, 8×, and 16× Interpolation
    • Linear Phase
    • 0.05-dB Pass-Band Ripple
    • 80-dB Stop-Band Attenuation
    • Stop-Band Transition 0.4-0.6 fDATA
  • 32-Bit Programmable NCO
  • On-Chip 2× - 16× PLL Clock Multiplier With Bypass Mode
  • Differential Scalable Current Outputs: 2 mA to 20 mA
  • On-Chip 1.2-V Reference
  • 1.8-V Digital and 3.3-V Analog Supplies
  • 1.8-V/3.3-V CMOS-Compatible Interface
  • Power Dissipation: 950 mW at Full Maximum Operating Conditions
  • Package: 100-Pin HTQFP
  • APPLICATIONS
    • Cellular Base Transceiver Station Transmit Channel
      • CDMA: W-CDMA, CDMA2000, IS-95
      • TDMA: GSM, IS-136, EDGE/UWC-136
    • Baseband I and Q Transmit
    • Input Interface: Quadrature Modulation for Interfacing With Baseband Complex Mixing ASICs
    • Single-Sideband Up-Conversion
    • Diversity Transmit
    • Cable Modem Termination System

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners

open-in-new 查找其它 高速 DACs (>10MSPS)

描述

The DAC5686 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2×, 4×, 8×, and 16× interpolation filters, a numerically controlled oscillator (NCO), onboard clock multiplier, and on-chip voltage reference. The DAC5686 has been specifically designed to allow for low input data rates between the DAC and ASIC, or FPGA, and high output transmit intermediate frequencies (IF). Target applications include high-speed digital data transmission in wired and wireless communication systems and high-frequency direct-digital synthesis DDS.

The DAC5686 provides three modes of operation: dual-channel, single-sideband, and quadrature modulation. In dual-channel mode, interpolation filtering increases the DAC update rate, which reduces sinx/x rolloff and enables the use of relaxed analog post-filtering.

Single-sideband mode provides an alternative interface to the analog quadrature modulators. Channel carrier selection is performed at baseband by mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which in turn performs a complex mix resulting in Hilbert transform pairs at the outputs of the DAC5686's two DACs. An external RF quadrature modulator then performs the final single-sideband up-conversion. The DAC5686's complex mixing frequencies are flexibly chosen with the 32-bit programmable NCO.

Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local oscillator feedthrough. Each DAC in the DAC5686 has an 11-bit offset adjustment and 12-bit gain adjustment, which compensate for quadrature modulator input imbalances, thus reducing RF filtering requirements.

In quadrature modulation mode, on-chip mixing provides baseband-to-IF up-conversion. Mixing frequencies are flexibly chosen with a 32-bit programmable NCO. Channel carrier selection is performed at baseband by complex mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which interpolates the low data-rate signal to higher data rates. The single DAC output from the DAC5686 is the final IF single-sideband spectrum presented to RF.

The 2×, 4×, 8×, and 16× interpolation filters are implemented as a cascade of half-band 2× interpolation filters. Unused filters for interpolation rates of less than 16× are shut off to reduce power consumption. The DAC5686 provides a full bypass mode, which enables the user to bypass all the interpolation and mixing.

The DAC5686 PLL clock multiplier controls all internal clocks for the digital filters and the DAC cores. The differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

The DAC5686 operates with an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. Digital I/Os are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 950 mW at maximum operating conditions. The DAC5686 provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The device has been specifically designed for a differential transformer-coupled output with a 50- doubly terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (-2-dBm output power) are supported.

The DAC5686 operational modes are configured by programming registers through a serial interface. The serial interface can be configured to either a 3- or 4-pin interface allowing it to communicate with many industry-standard microprocessors and microcontrollers. Data (I and Q) can be input to the DAC5686 as separate parallel streams on two data buses, or as a single interleaved data stream on one data bus.

An accurate on-chip 1.2-V temperature-compensated band-gap reference and control amplifier allows the user to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage can be applied for maximum flexibility. The device features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby minimizing the system power consumption.

The DAC5686 is available in a 100-pin HTQFP package. The device is characterized for operation over the industrial temperature range of -40°C to 85°C.

open-in-new 查找其它 高速 DACs (>10MSPS)
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技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 16-Bit 500 MSPS 2x-16x Interpolating Dual-Channel DAC 数据表 (Rev. F) 2009年 6月 3日
技术文章 Keys to quick success using high-speed data converters 2020年 10月 13日
应用手册 Q3 2009 Issue Analog Applications Journal 2018年 9月 24日
技术文章 Digital signal processing in RF sampling DACs – part 2 2017年 4月 4日
技术文章 Digital signal processing in RF sampling DACs - part 1 2017年 2月 13日
技术文章 Why phase noise matters in RF sampling converters 2016年 11月 28日
应用手册 High Speed, Digital-to-Analog Converters Basics (Rev. A) 2012年 10月 23日
用户指南 DAC5686 EVM User's Guide (Rev. F) 2010年 8月 24日
应用手册 Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs 2009年 7月 14日
应用手册 Passive Interface for Current Output DACs 2008年 11月 10日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 高速数据转换 下载英文版本 2008年 10月 16日
应用手册 CDCE72010 as clocking solution for High Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
用户指南 TSW3003 Demonstration Kit (Rev. D) 2007年 8月 28日
用户指南 TSW3000 Demo Kit (Rev. B) 2005年 11月 20日
用户指南 TSW3000 Demo Kit (Rev. A) 2005年 9月 26日
应用手册 DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A) 2005年 7月 21日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

软件开发

支持软件 下载
High Speed Data Converter Pro 软件
DATACONVERTERPRO-SW 此高速数据转换器专业 GUI 是一款 PC 程序(兼容 Windows® XP/7),有助于评估大多数 TI 高速数据转换器和模拟前端 (AFE) 平台。DATACONVERTERPRO-SW 支持整个 TSW14xxx 系列的数据采集和模式生成卡,为分析时域和频域中的数据转换器提供了快速强大的解决方案以及单音调、多音调和调制信号支持。此 GUI 还兼容用于快速合成单音调、多音调和调制信号的 TI 模式生成 GUI。

用户可以为 DATACONVERTERPRO-SW 提供可加载到 TI 数模转换器 (DAC) 中的定制模式。支持从模数转换器 (ADC) 采集内导出 CSV 文件,以进行外部分析。

DATACONVERTERPRO-SW 兼容相关器件部分中列出的所有 ADC 和 DAC。如果不清楚 TSW1400 是否支持相关的器件,请在数据转换器的 e2e 论坛上提问。

特性
  • 兼容 TSW1400、TSW1405、TSW1406 和 TSW14J10、TSW14J50、TSW14J56 和 TSW14J57 模式生成和数据采集平台
  • 适用于所有的 TI 高速 DAC、ADC 和 AFE 产品
  • 提供时域和频域分析
  • 支持单音调、多音调和调制信号性能分析
  • 同时支持多达 16 个转换器通道
  • 兼容 TI 模式生成 GUI

设计工具和仿真

仿真模型 下载
SLWC058A.ZIP (18 KB) - IBIS Model
仿真工具 下载
PSPICE® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。 

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI 器件、了解产品系列、打开测试台并对您的设计进行仿真,从而进一步分析选定的器件。您还可对多个 TI 器件进行联合仿真,以更好地展现您的系统。

除了一个完整的预加载模型库之外,您还可以在 PSPICE-FOR-TI 工具中轻松访问 TI 器件的全新技术资料。在您确认找到适合您应用的器件后,可访问 TI store 购买产品。 

借助 PSpice for TI,您可使用合适的工具来满足您在整个设计周期(从电路探索到设计开发和验证)的仿真需求。免费获取、轻松入门。立即下载 PSpice 设计和仿真套件,开始您的设计。

入门

  1. 申请使用 PSPICE-FOR-TI 仿真器
  2. 下载并安装
  3. 观看有关仿真入门的培训
特性
  • 利用 Cadence PSpice 技术
  • 带有一套数字模型的预装库可在最坏情形下进行时序分析
  • 动态更新确保您可以使用全新的器件型号
  • 针对仿真速度进行了优化,且不会降低精度
  • 支持对多个产品进行同步分析
  • 基于 OrCAD Capture 框架,提供对业界广泛使用的原理图捕获和仿真环境的访问权限
  • 可离线使用
  • 在各种工作条件和器件容许范围内验证设计,包括
    • 自动测量和后处理
    • Monte Carlo 分析
    • 最坏情形分析
    • 热分析
计算工具 下载
SCAC057.ZIP (2 KB)

CAD/CAE 符号

封装 引脚 下载
HTQFP (PZP) 100 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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