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数据转换器
模数转换器 (ADC)
高速 ADC (≥10 MSPS)

ADS58C28

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双通道、11 位、200MSPS 模数转换器 (ADC)

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ADS58C28

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产品详情

Sample rate (max) (Msps) 200 Resolution (Bits) 11 Number of input channels 2 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 600 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 505 Architecture Pipeline SNR (dB) 66.8 ENOB (Bits) 10.7 SFDR (dB) 84 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 200 Resolution (Bits) 11 Number of input channels 2 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 600 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 505 Architecture Pipeline SNR (dB) 66.8 ENOB (Bits) 10.7 SFDR (dB) 84 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 200MSPS
  • High Dynamic Performance:
    • 83dBc SFDR at 140MHz
    • 72.5dBFS SNR with 60MHz BW Using SNRBoost3G Technology
  • SNRBoost3G Highlights:
    • Supports Wide Bandwidth (up to 60MHz)
    • Programmable Bandwidths:
      20MHz, 30MHz, and 40MHz
    • Flat Noise Floor within the Band
    • Independent SNRBoost3G Coefficients for Both Channels
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω termination
      • 2× Strength: 50Ω termination
    • Compatible with GC6016
    • 1.8V Parallel CMOS Interface Also Supported
  • Ultralow Power with Single 1.8V Supply:
    • 470mW Total Power
    • 710mW Total Power (200MSPS) with SNRBoost3G on Both Channels
  • Programmable Gain up to 6dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-64 (9mm × 9mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners
  • Maximum Sample Rate: 200MSPS
  • High Dynamic Performance:
    • 83dBc SFDR at 140MHz
    • 72.5dBFS SNR with 60MHz BW Using SNRBoost3G Technology
  • SNRBoost3G Highlights:
    • Supports Wide Bandwidth (up to 60MHz)
    • Programmable Bandwidths:
      20MHz, 30MHz, and 40MHz
    • Flat Noise Floor within the Band
    • Independent SNRBoost3G Coefficients for Both Channels
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω termination
      • 2× Strength: 50Ω termination
    • Compatible with GC6016
    • 1.8V Parallel CMOS Interface Also Supported
  • Ultralow Power with Single 1.8V Supply:
    • 470mW Total Power
    • 710mW Total Power (200MSPS) with SNRBoost3G on Both Channels
  • Programmable Gain up to 6dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-64 (9mm × 9mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners

The ADS58C28 is a dual-channel, 11-bit analog-to-digital converter (ADC) with sampling rates up to 200MSPS. The device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This architecture makes it well-suited for multi-carrier, wide bandwidth communications applications.

The ADS58C28 uses third-generation SNRBoost3G technology to overcome SNR limitation as a result of quantization noise (for bandwidths less than Nyquist, fS/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60MHz). In addition, separate SNRBoost3G coefficients can also be programmed for each channel.

The device has a digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as double data rate (DDR) low-voltage differential signaling (LVDS) together with an LVDS clock output. The low data rate of this interface (400MBPS at 200MSPS sample rate) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The strength of the LVDS output buffers can be increased to support 50Ω differential termination. This increase allows the output clock signal to be connected to two separate receiver chips with an effective 50Ω termination (such as the two clock ports of the GC5330). The same digital output pins can also be configured as a parallel 1.8V CMOS interface.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS58C28 is specified over the industrial temperature range (–40°C to +85°C).

The ADS58C28 is a dual-channel, 11-bit analog-to-digital converter (ADC) with sampling rates up to 200MSPS. The device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This architecture makes it well-suited for multi-carrier, wide bandwidth communications applications.

The ADS58C28 uses third-generation SNRBoost3G technology to overcome SNR limitation as a result of quantization noise (for bandwidths less than Nyquist, fS/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60MHz). In addition, separate SNRBoost3G coefficients can also be programmed for each channel.

The device has a digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as double data rate (DDR) low-voltage differential signaling (LVDS) together with an LVDS clock output. The low data rate of this interface (400MBPS at 200MSPS sample rate) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The strength of the LVDS output buffers can be increased to support 50Ω differential termination. This increase allows the output clock signal to be connected to two separate receiver chips with an effective 50Ω termination (such as the two clock ports of the GC5330). The same digital output pins can also be configured as a parallel 1.8V CMOS interface.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS58C28 is specified over the industrial temperature range (–40°C to +85°C).
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Dual Channel IF Receiver with SNRBoost3G 数据表 (Rev. B) 2010年 10月 29日
应用手册 Band-Pass Filter Design Techniques for High-Speed ADCs 2012年 2月 27日
应用手册 High-Speed, Analog-to-Digital Converter Basics 2012年 1月 11日
应用手册 Power Supply Design for the ADS41xx (Rev. A) 2011年 12月 29日
应用手册 Understanding Low-Amplitude Behavior of 11-bit ADCs 2011年 10月 22日
应用手册 Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010年 9月 10日
应用手册 Using Windowing With SNRBoost 3G Technology 2010年 8月 30日
应用手册 Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009年 4月 28日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 模数规格和性能特性术语表 (Rev. A) 最新英语版本 (Rev.B) 2008年 10月 16日
应用手册 高速数据转换 英语版 2008年 10月 16日
应用手册 CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
应用手册 QFN Layout Guidelines 2006年 7月 28日

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

ADS58C28EVM — ADS58C28 双通道 11 位 200MSPS 模数转换器评估模块

ADS58C28EVM 是一款电路板，设计者可将其用于评估德州仪器 (TI) ADS58C28 器件的性能。该器件是一款双通道 11 位 200MSPS 模数转换器，采用了 TI 的 SNRBoost 技术。ADC EVM 具有 DDR LVDS 数据输出，能与 TI 的 TSW1200 数据采集卡兼容，可进行快速评估。该 EVM 提供了可在各种时钟、输入和电源条件下测试 ADS58C28 的灵活环境。

评估模块在转换器的四个输入端均设计了背靠背宽带平衡-非平衡转换器。这使得各种单端输入信号都能输入到 ADC 的任意通道中。ADS58C28EVM 还兼容 FMC-ADC 适配器和 (...)

用户指南: PDF
TI.com 上无现货
评估模块 (EVM) 用 GUI

ADS58C28SPIGUI-SW — ADS42xxx SPI GUI

ADS58C28SPIGUI-SW is the installation package for ADS58C28_ADS42xx_GUI which is used to access or write internal registers of ADS58C28 through an on-board USB port.
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评估模块 (EVM) 用 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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支持软件

SBAC120 — TIGAR Support Files

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计算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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计算工具

JITTER-SNR-CALC — Jitter and SNR calculator

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

支持的产品和硬件

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设计工具

SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

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原理图

ADS42XX_58C28EVM DesignPkg (Rev. B)

SLAC459B.ZIP (6548 KB)
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模拟工具

PSPICE-FOR-TI — PSpice® for TI 设计和仿真工具

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。 

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
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封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RGC) 64 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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