产品详情

Sample rate (max) (Msps) 250 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.5 Power consumption (typ) (mW) 350 Architecture Pipeline SNR (dB) 69.7 ENOB (Bits) 11.2 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 250 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.5 Power consumption (typ) (mW) 350 Architecture Pipeline SNR (dB) 69.7 ENOB (Bits) 11.2 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGZ) 48 49 mm² 7 x 7
  • ADS41B49: 14-Bit, 250 MSPS
    ADS41B29: 12-Bit, 250 MSPS
  • Integrated High-Impedance
    Analog Input Buffer:
    • Input Capacitance: 2 pF
    • 200-MHz Input Resistance: 3 kΩ
  • Maximum Sample Rate: 250 MSPS
  • Ultralow Power:
    • 1.8-V Analog Power: 180 mW
    • 3.3-V Buffer Power: 96 mW
    • I/O Power: 135 mW (DDR LVDS)
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 82.5 dBc at 170 MHz
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2x Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR, SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: VQFN-48 (7 mm × 7 mm)
  • ADS41B49: 14-Bit, 250 MSPS
    ADS41B29: 12-Bit, 250 MSPS
  • Integrated High-Impedance
    Analog Input Buffer:
    • Input Capacitance: 2 pF
    • 200-MHz Input Resistance: 3 kΩ
  • Maximum Sample Rate: 250 MSPS
  • Ultralow Power:
    • 1.8-V Analog Power: 180 mW
    • 3.3-V Buffer Power: 96 mW
    • I/O Power: 135 mW (DDR LVDS)
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 82.5 dBc at 170 MHz
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2x Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR, SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: VQFN-48 (7 mm × 7 mm)

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.

The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.

The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 ADS41Bx9 14- and 12-Bit, 250-MSPS, Ultralow-Power ADCs with Analog Buffers 数据表 (Rev. F) PDF | HTML 2016年 2月 11日
应用手册 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
应用手册 Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
用户指南 Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 2012年 7月 10日
应用手册 Band-Pass Filter Design Techniques for High-Speed ADCs 2012年 2月 27日
应用手册 High-Speed, Analog-to-Digital Converter Basics 2012年 1月 11日
应用手册 Power Supply Design for the ADS41xx (Rev. A) 2011年 12月 29日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 模数规格和性能特性术语表 (Rev. A) 最新英语版本 (Rev.B) 2008年 10月 16日
应用手册 高速数据转换 英语版 2008年 10月 16日
应用手册 CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
应用手册 QFN Layout Guidelines 2006年 7月 28日

设计与开发

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评估模块 (EVM) 用 GUI

SLAC384 ADS41xx SPI GUI rev1.6

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支持软件

SBAC120 TIGAR Support Files

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仿真模型

ADS414x, ADS412x, ADS58B1x, IBIS MODEL

SBAM091.ZIP (318 KB) - IBIS Model
仿真模型

ADS414x, ADS412x, ADS58B1x, IBIS MODEL (Rev. A)

SBAM091A.ZIP (318 KB) - IBIS Model
物料清单 (BOM)

ADS41xx EVM BOM, Schematic, and PCB

SLAR048.ZIP (2222 KB)
计算工具

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计算工具

JITTER-SNR-CALC Jitter and SNR calculator

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

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设计工具

SBAC119 TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

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模拟工具

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封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RGZ) 48 Ultra Librarian

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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