The ADS556x is a high-performance 16-bit family of ADCs with sampling rates up to 80 MSPS. The device supports very-high SNR for input frequencies in the first Nyquist zone. The device includes a low-frequency noise suppression mode that improves the noise from DC to about 1 MHz.
In addition to high performance, the device offers several flexible features such as output interface (either Double Data Rate [DDR] LVDS or parallel CMOS) and fine gain in 1-dB steps until 6-dB maximum gain.
Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling capacitors, have been used to achieve significant savings in pin count. This innovation results in a compact 7-mm × 7-mm 48-pin VQFN package.
The device can be put in an external reference mode, where the VCM pin behaves as the external reference input. For applications where power is important, the ADS556x device offers power down modes and automatic power scaling at lower sample rates.
The device is specified over the industrial temperature range of –40°C to 85°C.
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | ADS556x 16-Bit, 40 and 80 MSPS ADCs With DDR LVDS and CMOS Outputs 数据表 (Rev. B) | PDF | HTML | 2016年 1月 13日 | ||
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015年 5月 22日 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013年 7月 19日 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010年 9月 10日 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009年 4月 28日 | ||||
| 应用手册 | 所选封装材料的热学和电学性质 | 2008年 10月 16日 | ||||
| 应用手册 | 模数规格和性能特性术语表 (Rev. A) | 最新英语版本 (Rev.B) | 2008年 10月 16日 | |||
| 应用手册 | 高速数据转换 | 英语版 | 2008年 10月 16日 | |||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008年 6月 8日 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008年 6月 2日 | ||||
| 应用手册 | QFN Layout Guidelines | 2006年 7月 28日 |
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
ADS5560EVM 是能让设计者评估德州仪器 (TI) ADS5560 器件（具有高 SNR 性能的低功耗 16 位 80MSPS 模数转换器）的电路板。ADC 具有可配置的并行 DDR LVDS 或 CMOS 输出。EVM 提供了可在各种时钟、输入和电源条件下测试 ADS5562 的灵活环境。
ADS5560EVM 还包括开放式插槽和德州仪器 (TI) 的新款 10 路输出低抖动时钟同步器和抖动消除器器件 - CDCE72010，它可驱动 ADS5560 的时钟输入。我们为外部 VCXO 和晶体带通滤波器提供了开放式插槽，允许对组合的高性能 ADC (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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