DAC5682Z
- 16-Bit Digital-to-Analog Converter (DAC)
- 1.0 GSPS Update Rate
- 16-Bit Wideband Input LVDS Data Bus
- 8 Sample Input FIFO
- Interleaved I/Q Data for Dual-DAC Mode
- High Performance
- 73-dBc ACLR WCDMA TM1 at 180 MHz
- 2x-32x Clock Multiplying PLL/VCO
- 2x or 4x Interpolation Filters
- Stopband Transition 0.4 to 0.6 Fdata
- Filters Configurable in Either Low-Pass or High-Pass
Mode Allows Selection of Higher Order Image
- Fs/4 Coarse Mixer
- On-Chip 1.2-V Reference
- Differential Scalable Output: 2 to 20 mA
- Package: 64-Pin 9-mm × 9-mm QFN
- APPLICATIONS
- Cellular Base Stations
- Broadband Wireless Access (BWA)
- WiMAX 802.16
- Fixed Wireless Backhaul
- Cable Modem Termination System (CMTS)
All other trademarks are the property of their respective owners
The DAC5682Z is a dual-channel 16-bit 1.0 GSPS DAC with wideband LVDS data input, integrated 2x/4x interpolation filters, onboard clock multiplier, and internal voltage reference. The DAC5682Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.
The DAC5682Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by onboard 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.
The DAC5682Z allows both complex or real output. An optional Fs/4 coarse mixer in complex mode provides coarse frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. An external RF quadrature modulator then performs the final single sideband up-conversion. The interpolation filters and complex coarse mixers efficiently provide frequency plan flexibility while enabling higher output DAC rates to simplify image rejection filtering.
The DAC5682Z is characterized for operation over the industrial temperature range of 40°C to 85°C and is available in a 64-pin QFN package. Other single-channel members of the family include the interpolating DAC5681Z and the noninterpolating DAC5681.
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设计和开发
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DAC5681EVM — DAC5681 评估模块
DAC5681ZEVM — DAC5681Z 16 位、1.0GSPS、1x-4x 插值数模转换器评估模块
DAC5681ZEVM 是能让设计者评估德州仪器 (TI) 的单通道 16 位 1.0GSPS 数模转换器 (DAC) 的电路板,它具有 fll 1GSPS DDR LVDS 接口、集成 2x/4x 内插滤波器、板载时钟乘法器和内部参考电压。EVM 提供了可在各种时钟、输入条件下测试 DAC5681Z 的灵活环境。
它能与 TSW3100 配合使用以执行各种测试程序。TSW3100 生成了测试模式,该模式将通过 1GSPS LVDS 接口被馈送至 DAC5681ZEVM。DAC5681ZEVM 具有可使 TSW3100 板与 DAC5681ZEVM 同步的可编程时钟芯片。
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封装 | 引脚数 | 下载 |
---|---|---|
VQFN (RGC) | 64 | 了解详情 |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 认证摘要
- 持续可靠性监测
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