主页 数据转换器 模数转换器 (ADC) 高速 ADC (≥10 MSPS)
主页
数据转换器
模数转换器 (ADC)
高速 ADC (≥10 MSPS)

ADS58B18

正在供货

11 位、200MSPS 模数转换器 (ADC)

立即订购
数据表

ADS58B18

正在供货
数据表 立即订购

产品详情

Sample rate (max) (Msps) 200 Resolution (Bits) 11 Number of input channels 1 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 310 Architecture Pipeline SNR (dB) 66.3 ENOB (Bits) 10.6 SFDR (dB) 87.5 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 200 Resolution (Bits) 11 Number of input channels 1 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 310 Architecture Pipeline SNR (dB) 66.3 ENOB (Bits) 10.6 SFDR (dB) 87.5 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGZ) 48 49 mm² 7 x 7
  • ADS58B18: 11-Bit, 200MSPS
  • ADS58B19: 9-Bit, 250MSPS
  • Integrated High-Impedance Analog Input Buffer
  • Ultralow Power:
    • Analog Power: 258mW at 200MSPS
    • I/O Power: 69mW (DDR LVDS, low LVDS swing)
  • High Dynamic Performance:
    • ADS58B18: 66dBFS SNR and 81dBc SFDR at 150MHz
    • ADS58B19: 55.7dBFS SNR and 76dBc SFDR at 150MHz
  • Enhanced SNR Using TI-Proprietary SNRBoost Technology (ADS58B18 Only)
    • –77.7dBFS SNR in 20MHz Bandwidth
  • Dynamic Power Scaling with Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω Termination
      • 2x Strength: 50Ω Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
  • ADS58B18: 11-Bit, 200MSPS
  • ADS58B19: 9-Bit, 250MSPS
  • Integrated High-Impedance Analog Input Buffer
  • Ultralow Power:
    • Analog Power: 258mW at 200MSPS
    • I/O Power: 69mW (DDR LVDS, low LVDS swing)
  • High Dynamic Performance:
    • ADS58B18: 66dBFS SNR and 81dBc SFDR at 150MHz
    • ADS58B19: 55.7dBFS SNR and 76dBc SFDR at 150MHz
  • Enhanced SNR Using TI-Proprietary SNRBoost Technology (ADS58B18 Only)
    • –77.7dBFS SNR in 20MHz Bandwidth
  • Dynamic Power Scaling with Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω Termination
      • 2x Strength: 50Ω Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2).

Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.

The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).

The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2).

Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.

The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).
filter 查找其他 高速 ADC (≥10 MSPS)
下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 13
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer 数据表 (Rev. D) 2011年 1月 28日
用户指南 Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 2012年 7月 10日
应用手册 High-Speed, Analog-to-Digital Converter Basics 2012年 1月 11日
应用手册 Power Supply Design for the ADS41xx (Rev. A) 2011年 12月 29日
应用手册 Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010年 9月 10日
应用手册 Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009年 4月 28日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 模数规格和性能特性术语表 (Rev. A) 最新英语版本 (Rev.B) 2008年 10月 16日
应用手册 高速数据转换 英语版 2008年 10月 16日
应用手册 CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
应用手册 QFN Layout Guidelines 2006年 7月 28日

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

ADS58B18EVM — ADS58B18 11 位 200MSPS 模数转换器评估模块

ADS58B18EVM 是一款电路板，设计者能将其用于评估德州仪器 (TI) ADS58B18 器件之性能。该器件是一款超低功耗的 11 位 200MSPS 模数转换器。ADC 具有缓冲模拟输入和可配置的并行 DDR LVDS 或 CMOS 输出。该 EVM 提供了可在各种时钟、输入和电源条件下测试 ADS58B18 的灵活环境。

ADS58B18EVM 还包括德州仪器 (TI) 的新款 10 路输出低抖动时钟同步器和抖动消除器器件 - CDCE72010，它可用于驱动 ADS58B18 的时钟输入。为外部 VCXO 和晶体带通滤波器提供开放式插槽，可快速评估组合的高性能 ADC (...)

用户指南: PDF | HTML
英语版 (Rev.D): PDF | HTML
TI.com 上无现货
评估模块 (EVM) 用 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

支持的产品和硬件

支持的产品和硬件
下载
评估模块 (EVM) 用 GUI

SLAC384 — ADS41xx SPI GUI rev1.6

支持的产品和硬件

支持的产品和硬件
下载
仿真模型

ADS414x, ADS412x, ADS58B1x, IBIS MODEL

SBAM091.ZIP (318 KB) - IBIS Model
下载
仿真模型

ADS414x, ADS412x, ADS58B1x, IBIS MODEL (Rev. A)

SBAM091A.ZIP (318 KB) - IBIS Model
下载
物料清单 (BOM)

ADS41xx EVM BOM, Schematic, and PCB

SLAR048.ZIP (2222 KB)
下载
计算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

支持的产品和硬件

支持的产品和硬件
启动 下载
计算工具

JITTER-SNR-CALC — Jitter and SNR calculator

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

支持的产品和硬件

支持的产品和硬件
下载
模拟工具

PSPICE-FOR-TI — PSpice® for TI 设计和仿真工具

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。 

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
发送申请
封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RGZ) 48 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频